diff options
Diffstat (limited to 'arch/arm/mach-stm32mp/stm32mp1/cpu.c')
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp1/cpu.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 64480da9f8d..62cc98910a7 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -57,7 +57,7 @@ void dram_bank_mmu_setup(int bank) bool use_lmb = false; enum dcache_option option; - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* STM32_SYSRAM_BASE exist only when SPL is supported */ #ifdef CONFIG_SPL start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); @@ -133,7 +133,7 @@ int mach_cpu_init(void) if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; - else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) + else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD)) debug_uart_init(); return 0; @@ -143,6 +143,11 @@ void enable_caches(void) { /* I-cache is already enabled in start.S: icache_enable() not needed */ + /* keep D-cache configuration done before relocation, wait arch_early_init_r*/ +} + +int arch_early_init_r(void) +{ /* deactivate the data cache, early enabled in arch_cpu_init() */ dcache_disable(); /* @@ -150,6 +155,8 @@ void enable_caches(void) * warning: the TLB location udpated in board_f.c::reserve_mmu */ dcache_enable(); + + return 0; } static void setup_boot_mode(void) @@ -339,7 +346,7 @@ uintptr_t get_stm32mp_bl2_dtb(void) return nt_fw_dtb; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); |