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Diffstat (limited to 'arch/arm/mach-stm32mp/stm32mp1/cpu.c')
-rw-r--r--arch/arm/mach-stm32mp/stm32mp1/cpu.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index 478c3efae73..64480da9f8d 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -30,8 +30,6 @@
*/
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
-struct lmb lmb;
-
u32 get_bootmode(void)
{
/* read bootmode from TAMP backup register */
@@ -80,7 +78,7 @@ void dram_bank_mmu_setup(int bank)
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
i++) {
option = DCACHE_DEFAULT_OPTION;
- if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
+ if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP))
option = 0; /* INVALID ENTRY in TLB */
set_section_dcache(i, option);
}
@@ -143,9 +141,6 @@ int mach_cpu_init(void)
void enable_caches(void)
{
- /* parse device tree when data cache is still activated */
- lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
-
/* I-cache is already enabled in start.S: icache_enable() not needed */
/* deactivate the data cache, early enabled in arch_cpu_init() */