diff options
Diffstat (limited to 'arch/arm/mach-stm32mp/stm32mp1')
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp1/psci.c | 21 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp1/spl.c | 4 |
2 files changed, 23 insertions, 2 deletions
diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 7772546b2fe..bfbf420fdb5 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -809,6 +809,27 @@ void __secure psci_system_suspend(u32 __always_unused function_id, clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); /* + * Make sure the OS would not get any spurious IWDG pretimeout IRQ + * right after the system wakes up. This may happen in case the SoC + * got woken up by another source than the IWDG pretimeout and the + * pretimeout IRQ arrived immediately afterward, but too late to be + * handled by the main loop above. In case either of the IWDG is + * enabled, ping it first and then return to the OS. + */ + + /* Ping IWDG1 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(22)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(23)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + + /* * The system has resumed successfully. Rewrite LR register stored * on stack with 'ep' value, so that on return from this PSCI call, * the code would jump to that 'ep' resume entry point code path diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 7a8fd3178ad..6eae5c2f557 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -118,7 +118,7 @@ static int optee_get_reserved_memory(uint32_t *start, uint32_t *size) node = ofnode_path("/reserved-memory/optee"); if (!ofnode_valid(node)) - return 0; + return -ENOENT; fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); *start = fdt_start; @@ -134,7 +134,7 @@ void stm32_init_tzc_for_optee(void) { const uint32_t dram_size = stm32mp_get_dram_size(); const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1); - uint32_t optee_base, optee_size, tee_shmem_base; + u32 optee_base = 0, optee_size = 0, tee_shmem_base; const uintptr_t tzc = STM32_TZC_BASE; int ret; |