diff options
Diffstat (limited to 'arch/arm/mach-stm32mp/stm32mp2')
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/cpu.c | 170 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/rifsc.c | 364 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c | 31 |
4 files changed, 547 insertions, 19 deletions
diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile index b579ce5a800..5dbf75daa76 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -5,5 +5,6 @@ obj-y += cpu.o obj-y += arm64-mmu.o +obj-y += rifsc.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c index 9530aa8534b..c3b87d7f981 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -24,7 +24,7 @@ * early TLB into the .data section so that it not get cleared * with 16kB alignment */ -#define EARLY_TLB_SIZE 0xA000 +#define EARLY_TLB_SIZE 0x10000 u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); /* @@ -55,6 +55,19 @@ int arch_cpu_init(void) return 0; } +int mach_cpu_init(void) +{ + u32 boot_mode; + + boot_mode = get_bootmode(); + + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && + (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + + return 0; +} + void enable_caches(void) { /* deactivate the data cache, early enabled in arch_cpu_init() */ @@ -67,14 +80,6 @@ void enable_caches(void) dcache_enable(); } -int arch_misc_init(void) -{ - setup_serial_number(); - setup_mac_address(); - - return 0; -} - /* * Force data-section, as .bss will not be valid * when save_boot_params is invoked. @@ -97,3 +102,150 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, save_boot_params_ret(); } + +u32 get_bootmode(void) +{ + /* read bootmode from TAMP backup register */ + return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> + TAMP_BOOT_MODE_SHIFT; +} + +static void setup_boot_mode(void) +{ + const u32 serial_addr[] = { + STM32_USART1_BASE, + STM32_USART2_BASE, + STM32_USART3_BASE, + STM32_UART4_BASE, + STM32_UART5_BASE, + STM32_USART6_BASE, + STM32_UART7_BASE, + STM32_UART8_BASE, + STM32_UART9_BASE + }; + const u32 sdmmc_addr[] = { + STM32_SDMMC1_BASE, + STM32_SDMMC2_BASE, + STM32_SDMMC3_BASE + }; + char cmd[60]; + u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); + u32 boot_mode = + (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; + unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; + u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); + struct udevice *dev; + + log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", + __func__, boot_ctx, boot_mode, instance, forced_mode); + switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_SERIAL_UART: + if (instance > ARRAY_SIZE(serial_addr)) + break; + /* serial : search associated node in devicetree */ + sprintf(cmd, "serial@%x", serial_addr[instance]); + if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { + /* restore console on error */ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + log_err("uart%d = %s not found in device tree!\n", + instance + 1, cmd); + break; + } + sprintf(cmd, "%d", dev_seq(dev)); + env_set("boot_device", "serial"); + env_set("boot_instance", cmd); + + /* restore console on uart when not used */ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + log_info("serial boot with console enabled!\n"); + } + break; + case BOOT_SERIAL_USB: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + if (instance > ARRAY_SIZE(sdmmc_addr)) + break; + /* search associated sdmmc node in devicetree */ + sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); + if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) { + printf("mmc%d = %s not found in device tree!\n", + instance, cmd); + break; + } + sprintf(cmd, "%d", dev_seq(dev)); + env_set("boot_device", "mmc"); + env_set("boot_instance", cmd); + break; + case BOOT_FLASH_NAND: + env_set("boot_device", "nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SPINAND: + env_set("boot_device", "spi-nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_NOR: + env_set("boot_device", "nor"); + if (IS_ENABLED(CONFIG_SYS_MAX_FLASH_BANKS)) + sprintf(cmd, "%d", CONFIG_SYS_MAX_FLASH_BANKS); + else + sprintf(cmd, "%d", 0); + env_set("boot_instance", cmd); + break; + case BOOT_FLASH_HYPERFLASH: + env_set("boot_device", "nor"); + env_set("boot_instance", "0"); + break; + default: + env_set("boot_device", "invalid"); + env_set("boot_instance", ""); + log_err("unexpected boot mode = %x\n", boot_mode); + break; + } + + switch (forced_mode) { + case BOOT_FASTBOOT: + log_info("Enter fastboot!\n"); + env_set("preboot", "env set preboot; fastboot 0"); + break; + case BOOT_STM32PROG: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_UMS_MMC0: + case BOOT_UMS_MMC1: + case BOOT_UMS_MMC2: + log_info("Enter UMS!\n"); + instance = forced_mode - BOOT_UMS_MMC0; + sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); + env_set("preboot", cmd); + break; + case BOOT_RECOVERY: + env_set("preboot", "env set preboot; run altbootcmd"); + break; + case BOOT_NORMAL: + break; + default: + log_debug("unexpected forced boot mode = %x\n", forced_mode); + break; + } + + /* clear TAMP for next reboot */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); +} + +int arch_misc_init(void) +{ + setup_boot_mode(); + setup_serial_number(); + setup_mac_address(); + + return 0; +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c new file mode 100644 index 00000000000..50dececf77b --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include <dm.h> +#include <asm/io.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/lists.h> +#include <linux/bitfield.h> +#include <mach/rif.h> + +/* RIFSC offset register */ +#define RIFSC_RISC_SECCFGR0(id) (0x10 + 0x4 * (id)) +#define RIFSC_RISC_PER0_CIDCFGR(id) (0x100 + 0x8 * (id)) +#define RIFSC_RISC_PER0_SEMCR(id) (0x104 + 0x8 * (id)) + +/* + * SEMCR register + */ +#define SEMCR_MUTEX BIT(0) + +/* RIFSC miscellaneous */ +#define RIFSC_RISC_SCID_MASK GENMASK(6, 4) +#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16) + +#define IDS_PER_RISC_SEC_PRIV_REGS 32 + +/* + * CIDCFGR register fields + */ +#define CIDCFGR_CFEN BIT(0) +#define CIDCFGR_SEMEN BIT(1) + +#define SEMWL_SHIFT 16 + +#define STM32MP25_RIFSC_ENTRIES 178 + +/* Compartiment IDs */ +#define RIF_CID0 0x0 +#define RIF_CID1 0x1 + +/* + * struct stm32_rifsc_plat: Information about RIFSC device + * + * @base: Base address of RIFSC + */ +struct stm32_rifsc_plat { + void *base; +}; + +/* + * struct stm32_rifsc_child_plat: Information about each child + * + * @domain_id: Domain id + */ +struct stm32_rifsc_child_plat { + u32 domain_id; +}; + +static bool stm32_rif_is_semaphore_available(void *base, u32 id) +{ + void *addr = base + RIFSC_RISC_PER0_SEMCR(id); + + return !(readl(addr) & SEMCR_MUTEX); +} + +static int stm32_rif_acquire_semaphore(void *base, u32 id) +{ + void *addr = base + RIFSC_RISC_PER0_SEMCR(id); + + /* Check that the semaphore is available */ + if (!stm32_rif_is_semaphore_available(base, id)) + return -EACCES; + + setbits_le32(addr, SEMCR_MUTEX); + + /* Check that CID1 has the semaphore */ + if (stm32_rif_is_semaphore_available(base, id) || + FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1)) + return -EACCES; + + return 0; +} + +static int stm32_rif_release_semaphore(void *base, u32 id) +{ + void *addr = base + RIFSC_RISC_PER0_SEMCR(id); + + if (stm32_rif_is_semaphore_available(base, id)) + return 0; + + clrbits_le32(addr, SEMCR_MUTEX); + + /* Ok if another compartment takes the semaphore before the check */ + if (!stm32_rif_is_semaphore_available(base, id) && + FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) == RIF_CID1)) + return -EACCES; + + return 0; +} + +static int rifsc_parse_access_controller(ofnode node, struct ofnode_phandle_args *args) +{ + int ret; + + ret = ofnode_parse_phandle_with_args(node, "access-controllers", + "#access-controller-cells", 0, + 0, args); + if (ret) { + log_debug("failed to parse access-controller (%d)\n", ret); + return ret; + } + + if (args->args_count != 1) { + log_debug("invalid domain args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args[0] >= STM32MP25_RIFSC_ENTRIES) { + log_err("Invalid sys bus ID for %s\n", ofnode_get_name(node)); + return -EINVAL; + } + + return 0; +} + +static int rifsc_check_access(void *base, u32 id) +{ + u32 reg_offset, reg_id, sec_reg_value, cid_reg_value, sem_reg_value; + + /* + * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for + * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register + * per peripheral + */ + reg_id = id / IDS_PER_RISC_SEC_PRIV_REGS; + reg_offset = id % IDS_PER_RISC_SEC_PRIV_REGS; + sec_reg_value = readl(base + RIFSC_RISC_SECCFGR0(reg_id)); + cid_reg_value = readl(base + RIFSC_RISC_PER0_CIDCFGR(id)); + sem_reg_value = readl(base + RIFSC_RISC_PER0_SEMCR(id)); + + /* + * First check conditions for semaphore mode, which doesn't take into + * account static CID. + */ + if (cid_reg_value & CIDCFGR_SEMEN) + goto skip_cid_check; + + /* + * Skip cid check if CID filtering isn't enabled or filtering is enabled on CID0, which + * corresponds to whatever CID. + */ + if (!(cid_reg_value & CIDCFGR_CFEN) || + FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0) + goto skip_cid_check; + + /* Coherency check with the CID configuration */ + if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) { + log_debug("Invalid CID configuration for peripheral %d\n", id); + return -EACCES; + } + + /* Check semaphore accesses */ + if (cid_reg_value & CIDCFGR_SEMEN) { + if (!(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { + log_debug("Not in semaphore whitelist for peripheral %d\n", id); + return -EACCES; + } + if (!stm32_rif_is_semaphore_available(base, id) && + !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) { + log_debug("Semaphore unavailable for peripheral %d\n", id); + return -EACCES; + } + } + +skip_cid_check: + /* Check security configuration */ + if (sec_reg_value & BIT(reg_offset)) { + log_debug("Invalid security configuration for peripheral %d\n", id); + return -EACCES; + } + + return 0; +} + +int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id) +{ + struct ofnode_phandle_args args; + int err; + + if (id >= STM32MP25_RIFSC_ENTRIES) + return -EINVAL; + + err = rifsc_parse_access_controller(device_node, &args); + if (err) + return err; + + return rifsc_check_access((void *)ofnode_get_addr(args.node), id); +} + +int stm32_rifsc_check_access(ofnode device_node) +{ + struct ofnode_phandle_args args; + int err; + + err = rifsc_parse_access_controller(device_node, &args); + if (err) + return err; + + return rifsc_check_access((void *)ofnode_get_addr(args.node), args.args[0]); +} + +static int stm32_rifsc_child_pre_probe(struct udevice *dev) +{ + struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent); + struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + u32 cid_reg_value; + int err; + u32 id = child_plat->domain_id; + + cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id)); + + /* + * If the peripheral is in semaphore mode, take the semaphore so that + * the CID1 has the ownership. + */ + if (cid_reg_value & CIDCFGR_SEMEN && + (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { + err = stm32_rif_acquire_semaphore(plat->base, id); + if (err) { + dev_err(dev, "Couldn't acquire RIF semaphore for peripheral %d (%d)\n", + id, err); + return err; + } + dev_dbg(dev, "Acquiring semaphore for peripheral %d\n", id); + } + + return 0; +} + +static int stm32_rifsc_child_post_remove(struct udevice *dev) +{ + struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent); + struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + u32 cid_reg_value; + int err; + u32 id = child_plat->domain_id; + + cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id)); + + /* + * If the peripheral is in semaphore mode, release the semaphore so that + * there's no ownership. + */ + if (cid_reg_value & CIDCFGR_SEMEN && + (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { + err = stm32_rif_release_semaphore(plat->base, id); + if (err) + dev_err(dev, "Couldn't release rif semaphore for peripheral %d (%d)\n", + id, err); + } + + return 0; +} + +static int stm32_rifsc_child_post_bind(struct udevice *dev) +{ + struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + struct ofnode_phandle_args args; + int ret; + + if (!dev_has_ofnode(dev)) + return -EPERM; + + ret = rifsc_parse_access_controller(dev_ofnode(dev), &args); + if (ret) + return ret; + + child_plat->domain_id = args.args[0]; + + return 0; +} + +static int stm32_rifsc_bind(struct udevice *dev) +{ + struct stm32_rifsc_plat *plat = dev_get_plat(dev); + struct ofnode_phandle_args args; + int ret = 0, err = 0; + ofnode node; + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) { + dev_err(dev, "can't get registers base address\n"); + return -ENOENT; + } + + for (node = ofnode_first_subnode(dev_ofnode(dev)); + ofnode_valid(node); + node = ofnode_next_subnode(node)) { + const char *node_name = ofnode_get_name(node); + + if (!ofnode_is_enabled(node)) + continue; + + err = rifsc_parse_access_controller(node, &args); + if (err) { + dev_dbg(dev, "%s failed to parse child on bus (%d)\n", node_name, err); + continue; + } + + err = rifsc_check_access(plat->base, args.args[0]); + if (err) { + dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err); + continue; + } + + err = lists_bind_fdt(dev, node, NULL, NULL, + gd->flags & GD_FLG_RELOC ? false : true); + if (err && !ret) { + ret = err; + dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret); + } + } + + if (ret) + dev_err(dev, "Some child failed to bind (%d)\n", ret); + + return ret; +} + +static int stm32_rifsc_remove(struct udevice *bus) +{ + struct udevice *dev; + + /* Deactivate all child devices not yet removed */ + for (device_find_first_child(bus, &dev); dev; device_find_next_child(&dev)) + if (device_active(dev)) + stm32_rifsc_child_post_remove(dev); + + return 0; +} + +static const struct udevice_id stm32_rifsc_ids[] = { + { .compatible = "st,stm32mp25-rifsc" }, + {}, +}; + +U_BOOT_DRIVER(stm32_rifsc) = { + .name = "stm32_rifsc", + .id = UCLASS_NOP, + .of_match = stm32_rifsc_ids, + .bind = stm32_rifsc_bind, + .remove = stm32_rifsc_remove, + .child_post_bind = stm32_rifsc_child_post_bind, + .child_pre_probe = stm32_rifsc_child_pre_probe, + .child_post_remove = stm32_rifsc_child_post_remove, + .plat_auto = sizeof(struct stm32_rifsc_plat), + .per_child_plat_auto = sizeof(struct stm32_rifsc_child_plat), + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c index 7f896a0d65d..12b43ea5cdf 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@ -15,8 +15,10 @@ #define SYSCFG_DEVICEID_OFFSET 0x6400 #define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) #define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 -#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16) -#define SYSCFG_DEVICEID_REV_ID_SHIFT 16 + +/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/ +#define REVID_SHIFT 0 +#define REVID_MASK GENMASK(5, 0) /* Device Part Number (RPN) = OTP9 */ #define RPN_SHIFT 0 @@ -24,8 +26,8 @@ /* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines * - 000: Custom package - * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm - * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 011: VFBGA424 => AK = 14x14, 424 balls pith 0.5mm * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm * - others: Reserved */ @@ -46,7 +48,7 @@ u32 get_cpu_dev(void) u32 get_cpu_rev(void) { - return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT; + return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK); } /* Get Device Part Number (RPN) from OTP */ @@ -164,12 +166,21 @@ void get_soc_name(char name[SOC_NAME_SIZE]) } /* REVISION */ switch (get_cpu_rev()) { - case CPU_REV1: + case OTP_REVID_1: cpu_r = "A"; break; - case CPU_REV2: + case OTP_REVID_1_1: + cpu_r = "Z"; + break; + case OTP_REVID_2: cpu_r = "B"; break; + case OTP_REVID_2_1: + cpu_r = "Y"; + break; + case OTP_REVID_2_2: + cpu_r = "X"; + break; default: break; } @@ -178,13 +189,13 @@ void get_soc_name(char name[SOC_NAME_SIZE]) case STM32MP25_PKG_CUSTOM: package = "XX"; break; - case STM32MP25_PKG_AL_TBGA361: + case STM32MP25_PKG_AL_VFBGA361: package = "AL"; break; - case STM32MP25_PKG_AK_TBGA424: + case STM32MP25_PKG_AK_VFBGA424: package = "AK"; break; - case STM32MP25_PKG_AI_TBGA436: + case STM32MP25_PKG_AI_TFBGA436: package = "AI"; break; default: |