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-rw-r--r--arch/arm/mach-stm32mp/Kconfig2
-rw-r--r--arch/arm/mach-stm32mp/Makefile2
-rw-r--r--arch/arm/mach-stm32mp/bsec.c12
-rw-r--r--arch/arm/mach-stm32mp/dram_init.c30
-rw-r--r--arch/arm/mach-stm32mp/stm32mp1/Makefile4
-rw-r--r--arch/arm/mach-stm32mp/stm32mp1/cpu.c13
-rw-r--r--arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c4
7 files changed, 37 insertions, 30 deletions
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index d5934a92771..25663a99464 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -39,6 +39,7 @@ choice
config STM32MP13X
bool "Support STMicroelectronics STM32MP13x Soc"
+ select ARCH_EARLY_INIT_R
select ARM_SMCCC
select CPU_V7A
select CPU_V7_HAS_NONSEC
@@ -57,6 +58,7 @@ config STM32MP13X
config STM32MP15X
bool "Support STMicroelectronics STM32MP15x Soc"
+ select ARCH_EARLY_INIT_R
select ARCH_SUPPORT_PSCI
select BINMAN
select CPU_V7A
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index ee8a5428feb..db7ed19bd91 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_STM32MP13X) += stm32mp1/
obj-$(CONFIG_STM32MP25X) += stm32mp2/
obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += cmd_stm32prog/
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
obj-$(CONFIG_TFABOOT) += boot_params.o
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 9ba7a6c9a89..9cbe6a52623 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -409,7 +409,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
u32 tmp_data = 0;
int ret;
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_OTP,
otp, 0, val);
@@ -440,7 +440,7 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_SHADOW,
otp, 0, val);
@@ -469,7 +469,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_PROG_OTP,
otp, val);
@@ -484,7 +484,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRITE_SHADOW,
otp, val);
@@ -504,7 +504,7 @@ static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
return 0; /* nothing to do */
}
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRLOCK_OTP,
otp, 0);
@@ -762,7 +762,7 @@ static int stm32mp_bsec_probe(struct udevice *dev)
* update unlocked shadow for OTP cleared by the rom code
* only executed in SPL, it is done in TF-A for TFABOOT
*/
- if (IS_ENABLED(CONFIG_SPL_BUILD) && !data->ta) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD) && !data->ta) {
plat = dev_get_plat(dev);
/* here 57 is the value for STM32MP15x ROM code, only MPU with SPL support*/
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 198785353f1..b06105768b3 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -25,8 +25,11 @@ int optee_get_reserved_memory(u32 *start, u32 *size)
ofnode node;
node = ofnode_path("/reserved-memory/optee");
- if (!ofnode_valid(node))
- return -ENOENT;
+ if (!ofnode_valid(node)) {
+ node = ofnode_path("/reserved-memory/optee_core");
+ if (!ofnode_valid(node))
+ return -ENOENT;
+ }
fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
*start = fdt_start;
@@ -62,7 +65,6 @@ int dram_init(void)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
- int ret;
phys_size_t size;
phys_addr_t reg;
u32 optee_start, optee_size;
@@ -75,10 +77,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
* if the effective available memory is bigger
*/
gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
+
+ /* add 8M for U-Boot reserved memory: display, fdt, gd,... */
size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
- ret = optee_get_reserved_memory(&optee_start, &optee_size);
- reg = (!ret ? optee_start : gd->ram_top) - size;
+ reg = gd->ram_top - size;
+
+ /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */
+ if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) {
+ if (!optee_get_reserved_memory(&optee_start, &optee_size))
+ reg = ALIGN(optee_start - size, MMU_SECTION_SIZE);
+ }
/* before relocation, mark the U-Boot memory as cacheable by default */
if (!(gd->flags & GD_FLG_RELOC))
@@ -86,14 +95,3 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return reg + size;
}
-
-void efi_add_known_memory(void)
-{
- if (IS_ENABLED(CONFIG_EFI_LOADER))
- /*
- * Memory over ram_top is reserved to OPTEE.
- * Declare to EFI only memory area below ram_top
- */
- efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base,
- EFI_CONVENTIONAL_MEMORY);
-}
diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile
index ebae50f66c9..db160c24cbc 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/Makefile
+++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile
@@ -8,12 +8,12 @@ obj-y += cpu.o
obj-$(CONFIG_STM32MP13X) += stm32mp13x.o
obj-$(CONFIG_STM32MP15X) += stm32mp15x.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-y += tzc400.o
else
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
-obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
+obj-$(CONFIG_$(XPL_)STM32MP15_PWR) += pwr_regulator.o
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index 64480da9f8d..62cc98910a7 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -57,7 +57,7 @@ void dram_bank_mmu_setup(int bank)
bool use_lmb = false;
enum dcache_option option;
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
/* STM32_SYSRAM_BASE exist only when SPL is supported */
#ifdef CONFIG_SPL
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
@@ -133,7 +133,7 @@ int mach_cpu_init(void)
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
- else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
+ else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD))
debug_uart_init();
return 0;
@@ -143,6 +143,11 @@ void enable_caches(void)
{
/* I-cache is already enabled in start.S: icache_enable() not needed */
+ /* keep D-cache configuration done before relocation, wait arch_early_init_r*/
+}
+
+int arch_early_init_r(void)
+{
/* deactivate the data cache, early enabled in arch_cpu_init() */
dcache_disable();
/*
@@ -150,6 +155,8 @@ void enable_caches(void)
* warning: the TLB location udpated in board_f.c::reserve_mmu
*/
dcache_enable();
+
+ return 0;
}
static void setup_boot_mode(void)
@@ -339,7 +346,7 @@ uintptr_t get_stm32mp_bl2_dtb(void)
return nt_fw_dtb;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_stm32_t)(u32 romapi);
diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
index ca202bec8ee..4f1d783649b 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
@@ -214,13 +214,13 @@ static void update_bootmode(void)
/* weak function: STM32MP15x mach init for boot without TFA */
void stm32mp_cpu_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
security_init();
update_bootmode();
}
/* reset copro state in SPL, when used, or in U-Boot */
- if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_XPL_BUILD)) {
/* Reset Coprocessor state unless it wakes up from Standby power mode */
if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
generated by cgit v1.2.3 (git 2.0.4) at 2025-09-20 07:49:14 +0000