diff options
Diffstat (limited to 'arch/arm/mach-stm32mp')
43 files changed, 9653 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig new file mode 100644 index 00000000000..002da2e3d3b --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig @@ -0,0 +1,183 @@ +if ARCH_STM32MP + +config SPL + select SPL_BOARD_INIT + select SPL_CLK + select SPL_DM + select SPL_DM_SEQ_ALIAS + select SPL_DRIVERS_MISC + select SPL_FRAMEWORK + select SPL_GPIO + select SPL_LIBCOMMON_SUPPORT + select SPL_LIBGENERIC_SUPPORT + select SPL_OF_CONTROL + select SPL_OF_TRANSLATE + select SPL_PINCTRL + select SPL_REGMAP + select SPL_DM_RESET + select SPL_SERIAL + select SPL_SYSCON + select SPL_WATCHDOG if WATCHDOG + imply BOOTSTAGE_STASH if SPL_BOOTSTAGE + imply SPL_BOOTSTAGE if BOOTSTAGE + imply SPL_DISPLAY_PRINT + imply SPL_LIBDISK_SUPPORT + imply SPL_SPI_LOAD if SPL_SPI + +config SYS_SOC + default "stm32mp" + +config SYS_MALLOC_LEN + default 0x2000000 + +config ENV_SIZE + default 0x2000 + +choice + prompt "Select STMicroelectronics STM32MPxxx Soc" + default STM32MP15X + +config STM32MP13X + bool "Support STMicroelectronics STM32MP13x Soc" + select ARCH_EARLY_INIT_R + select ARM_SMCCC + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select OF_BOARD + select OF_BOARD_SETUP + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SYS_ARCH_TIMER + imply CMD_NVEDIT_INFO + help + support of STMicroelectronics SOC STM32MP13x family + STMicroelectronics MPU with core ARMv7 + +config STM32MP15X + bool "Support STMicroelectronics STM32MP15x Soc" + select ARCH_EARLY_INIT_R + select ARCH_SUPPORT_PSCI + select BINMAN + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select OF_BOARD if TFABOOT + select OF_BOARD_SETUP + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SUPPORT_SPL + select SYS_ARCH_TIMER + imply CMD_NVEDIT_INFO + help + support of STMicroelectronics SOC STM32MP15x family + STM32MP157, STM32MP153 or STM32MP151 + STMicroelectronics MPU with core ARMv7 + dual core A7 for STM32MP157/3, monocore for STM32MP151 + +config STM32MP25X + bool "Support STMicroelectronics STM32MP25x Soc" + select ARM64 + select CLK_STM32MP25 + select OF_BOARD + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SYS_ARCH_TIMER + select TFABOOT + imply CLK_SCMI + imply CMD_NVEDIT_INFO + imply DM_REGULATOR + imply DM_REGULATOR_SCMI + imply OPTEE + imply RESET_SCMI + imply SYSRESET_PSCI + imply TEE + imply VERSION_VARIABLE + help + Support of STMicroelectronics SOC STM32MP25x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core +endchoice + +config NR_DRAM_BANKS + default 1 + +config DDR_CACHEABLE_SIZE + hex "Size of the DDR marked cacheable in pre-reloc stage" + default 0x40000000 + help + Define the size of the DDR marked as cacheable in U-Boot + pre-reloc stage. + This option can be useful to avoid speculatif access + to secured area of DDR used by TF-A or OP-TEE before U-Boot + initialization. + The areas marked "no-map" in device tree should be located + before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. + +config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 + hex "Partition on MMC2 to use to load U-Boot from" + depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + default 1 + help + Partition on the second MMC to load U-Boot from when the MMC is being + used in raw mode + +config STM32_ETZPC + bool "STM32 Extended TrustZone Protection" + depends on STM32MP15X || STM32MP13X + default y + imply BOOTP_SERVERIP + help + Say y to enable STM32 Extended TrustZone Protection + +config STM32_ECDSA_VERIFY + bool "STM32 ECDSA verification via the ROM API" + depends on SPL_ECDSA_VERIFY + default y + help + Say y to enable the uclass driver for ECDSA verification using the + ROM API provided on STM32MP. + The ROM API is only available during SPL for now. + +config CMD_STM32KEY + bool "command stm32key to fuse public key hash" + depends on CMDLINE + help + fuse public key hash in corresponding fuse used to authenticate + binary. + This command is used to evaluate the secure boot on stm32mp SOC, + it is deactivated by default in real products. + +config MFD_STM32_TIMERS + bool "STM32 multifonction timer support" + help + Select this to enable support for the multifunction timer found on + STM32 devices. + +source "arch/arm/mach-stm32mp/Kconfig.13x" +source "arch/arm/mach-stm32mp/Kconfig.15x" +source "arch/arm/mach-stm32mp/Kconfig.25x" +source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" + +config STM32MP15_PWR + bool "Enable driver for STM32MP15x PWR" + depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X) + default y if STM32MP15X + help + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR. + +config SPL_STM32MP15_PWR + bool "Enable driver for STM32MP15x PWR in SPL" + depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X) + default y if STM32MP15X + help + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR in SPL. + +endif diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-stm32mp/Kconfig.13x new file mode 100644 index 00000000000..bc8b3f8cf77 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.13x @@ -0,0 +1,54 @@ +if STM32MP13X + +choice + prompt "STM32MP13x board select" + optional + +config TARGET_ST_STM32MP13X + bool "STMicroelectronics STM32MP13x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + target the STMicroelectronics board with SOC STM32MP13x + managed by board/st/stm32mp1. + The difference between board are managed with devicetree + +endchoice + +config TEXT_BASE + default 0xC0000000 + +config PRE_CON_BUF_ADDR + default 0xC0800000 + +config PRE_CON_BUF_SZ + default 4096 + +if BOOTCOUNT_GENERIC +config SYS_BOOTCOUNT_SINGLEWORD + default y + +# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(31) +config SYS_BOOTCOUNT_ADDR + default 0x5C00A17C +endif + +if DEBUG_UART + +# debug on UART4 by default +config DEBUG_UART_BASE + default 0x40010000 + +# clock source is HSI on reset +config DEBUG_UART_CLOCK + default 48000000 if STM32_FPGA + default 64000000 +endif + +source "board/st/stm32mp1/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x new file mode 100644 index 00000000000..42da36a73e8 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.15x @@ -0,0 +1,116 @@ +if STM32MP15X + +config STM32MP15X_STM32IMAGE + bool "Support STM32 image for generated U-Boot image" + depends on TFABOOT + help + Support of STM32 image generation for SOC STM32MP15x + for TF-A boot when FIP container is not used + +choice + prompt "STM32MP15x board select" + optional + +config TARGET_ST_STM32MP15X + bool "STMicroelectronics STM32MP15x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + target the STMicroelectronics board with SOC STM32MP15x + managed by board/st/stm32mp1: + Evalulation board (EV1) or Discovery board (DK1 and DK2). + The difference between board are managed with devicetree + +config TARGET_DH_STM32MP1_PDK2 + bool "DH STM32MP1 PDK2" + help + Target the DH PDK2 development kit with STM32MP15x SoM. + +config TARGET_MICROGEA_STM32MP1 + bool "Engicam MicroGEA STM32MP1 SOM" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. + + MicroGEA STM32MP1 MicroDev 2.0: + * MicroDev 2.0 is a general purpose miniature carrier board with CAN, + LTE and LVDS panel interfaces. + * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board + for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. + + MicroGEA STM32MP1 MicroDev 2.0 7" OF: + * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS + panel and toucscreen. + * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with + pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" + Open Frame Solution board. + +config TARGET_ICORE_STM32MP1 + bool "Engicam i.Core STM32MP1 SOM" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. + + i.Core STM32MP1 EDIMM2.2: + * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. + * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for + creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. + + i.Core STM32MP1 C.TOUCH 2.0 + * C.TOUCH 2.0 is a general purpose Carrier board. + * i.Core STM32MP1 needs to mount on top of this Carrier board + for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. + +endchoice + +config TEXT_BASE + default 0xC0100000 + +config PRE_CON_BUF_ADDR + default 0xC02FF000 + +config PRE_CON_BUF_SZ + default 4096 + +if BOOTCOUNT_GENERIC +config SYS_BOOTCOUNT_SINGLEWORD + default y + +# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) +config SYS_BOOTCOUNT_ADDR + default 0x5C00A154 +endif + +if DEBUG_UART + +config DEBUG_UART_BOARD_INIT + default y if SPL + +# debug on UART4 by default +config DEBUG_UART_BASE + default 0x40010000 + +# clock source is HSI on reset +config DEBUG_UART_CLOCK + default 64000000 +endif + +source "board/st/stm32mp1/Kconfig" +source "board/dhelectronics/dh_stm32mp1/Kconfig" +source "board/engicam/stm32mp1/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Kconfig.25x b/arch/arm/mach-stm32mp/Kconfig.25x new file mode 100644 index 00000000000..7d2d8171845 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.25x @@ -0,0 +1,40 @@ +if STM32MP25X + +choice + prompt "STM32MP25x board select" + optional + +config TARGET_ST_STM32MP25X + bool "STMicroelectronics STM32MP25x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + help + target the STMicroelectronics board with SOC STM32MP25x + managed by board/st/stm32mp2 + The difference between board are managed with devicetree + +endchoice + +config TEXT_BASE + default 0x84000000 + +config PRE_CON_BUF_ADDR + default 0x84800000 + +config PRE_CON_BUF_SZ + default 4096 + +if DEBUG_UART + +config DEBUG_UART_BOARD_INIT + default y + +# debug on USART2 by default +config DEBUG_UART_BASE + default 0x400e0000 + +endif + +source "board/st/stm32mp2/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile new file mode 100644 index 00000000000..103e3410ad9 --- /dev/null +++ b/arch/arm/mach-stm32mp/Makefile @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +obj-y += dram_init.o +obj-y += syscon.o +obj-y += bsec.o +obj-y += soc.o + +obj-$(CONFIG_STM32MP15X) += stm32mp1/ +obj-$(CONFIG_STM32MP13X) += stm32mp1/ +obj-$(CONFIG_STM32MP25X) += stm32mp2/ + +obj-$(CONFIG_MFD_STM32_TIMERS) += timers.o +obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o +ifndef CONFIG_XPL_BUILD +obj-y += cmd_stm32prog/ +obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o +obj-$(CONFIG_TFABOOT) += boot_params.o +endif diff --git a/arch/arm/mach-stm32mp/boot_params.c b/arch/arm/mach-stm32mp/boot_params.c new file mode 100644 index 00000000000..2d058edc419 --- /dev/null +++ b/arch/arm/mach-stm32mp/boot_params.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <config.h> +#include <errno.h> +#include <log.h> +#include <linux/libfdt.h> +#include <asm/arch/sys_proto.h> +#include <asm/sections.h> +#include <asm/system.h> + +/* + * Use the saved FDT address provided by TF-A at boot time (NT_FW_CONFIG = + * Non Trusted Firmware configuration file) when the pointer is valid + */ +int board_fdt_blob_setup(void **fdtp) +{ + unsigned long nt_fw_dtb = get_stm32mp_bl2_dtb(); + + log_debug("%s: nt_fw_dtb=%lx\n", __func__, nt_fw_dtb); + + /* use external device tree only if address is valid */ + if (nt_fw_dtb < STM32_DDR_BASE || + fdt_magic(nt_fw_dtb) != FDT_MAGIC) { + log_debug("DTB not found.\n"); + log_debug("fall back to builtin DTB, %p\n", _end); + + return -EEXIST; + } + + *fdtp = (void *)nt_fw_dtb; + + return 0; +} diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c new file mode 100644 index 00000000000..9cbe6a52623 --- /dev/null +++ b/arch/arm/mach-stm32mp/bsec.c @@ -0,0 +1,845 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_MISC + +#include <clk.h> +#include <dm.h> +#include <log.h> +#include <misc.h> +#include <tee.h> +#include <asm/io.h> +#include <asm/arch/bsec.h> +#include <asm/arch/stm32mp1_smc.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <linux/arm-smccc.h> +#include <linux/iopoll.h> +#include <linux/printk.h> + +#define BSEC_OTP_UPPER_START 32 +#define BSEC_TIMEOUT_US 10000 + +/* BSEC REGISTER OFFSET (base relative) */ +#define BSEC_OTP_CONF_OFF 0x000 +#define BSEC_OTP_CTRL_OFF 0x004 +#define BSEC_OTP_WRDATA_OFF 0x008 +#define BSEC_OTP_STATUS_OFF 0x00C +#define BSEC_OTP_LOCK_OFF 0x010 +#define BSEC_DENABLE_OFF 0x014 +#define BSEC_DISTURBED_OFF 0x01C +#define BSEC_ERROR_OFF 0x034 +#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */ +#define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */ +#define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */ +#define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */ +#define BSEC_OTP_DATA_OFF 0x200 + +/* BSEC_CONFIGURATION Register MASK */ +#define BSEC_CONF_POWER_UP 0x001 + +/* BSEC_CONTROL Register */ +#define BSEC_READ 0x000 +#define BSEC_WRITE 0x100 +#define BSEC_LOCK 0x200 + +/* LOCK Register */ +#define OTP_LOCK_MASK 0x1F +#define OTP_LOCK_BANK_SHIFT 0x05 +#define OTP_LOCK_BIT_MASK 0x01 + +/* STATUS Register */ +#define BSEC_MODE_BUSY_MASK 0x08 +#define BSEC_MODE_PROGFAIL_MASK 0x10 +#define BSEC_MODE_PWR_MASK 0x20 + +/* DENABLE Register */ +#define BSEC_DENABLE_DBGSWENABLE BIT(10) + +/* + * OTP Lock services definition + * Value must corresponding to the bit number in the register + */ +#define BSEC_LOCK_PROGRAM 0x04 + +#define PTA_BSEC_UUID { 0x94cf71ad, 0x80e6, 0x40b5, \ + { 0xa7, 0xc6, 0x3d, 0xc5, 0x01, 0xeb, 0x28, 0x03 } } + +/* + * Read OTP memory + * + * [in] value[0].a OTP start offset in byte + * [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock) + * [out] memref[1].buffer Output buffer to store read values + * [out] memref[1].size Size of OTP to be read + * + * Return codes: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller + */ +#define PTA_BSEC_READ_MEM 0x0 + +/* + * Write OTP memory + * + * [in] value[0].a OTP start offset in byte + * [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock) + * [in] memref[1].buffer Input buffer to read values + * [in] memref[1].size Size of OTP to be written + * + * Return codes: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller + */ +#define PTA_BSEC_WRITE_MEM 0x1 + +/* value of PTA_BSEC access type = value[in] b */ +#define SHADOW_ACCESS 0 +#define FUSE_ACCESS 1 +#define LOCK_ACCESS 2 + +/** + * bsec_lock() - manage lock for each type SR/SP/SW + * @address: address of bsec IP register + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: true if locked else false + */ +static bool bsec_read_lock(void __iomem *address, u32 otp) +{ + u32 bit; + u32 bank; + + bit = 1 << (otp & OTP_LOCK_MASK); + bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); + + return !!(readl((address + bank)) & bit); +} + +/** + * bsec_check_error() - Check status of one otp + * @base: base address of bsec IP + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: 0 if no error, -EAGAIN or -ENOTSUPP + */ +static u32 bsec_check_error(void __iomem *base, u32 otp) +{ + u32 bit; + u32 bank; + + bit = 1 << (otp & OTP_LOCK_MASK); + bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); + + if (readl(base + BSEC_DISTURBED_OFF + bank) & bit) + return -EAGAIN; + else if (readl(base + BSEC_ERROR_OFF + bank) & bit) + return -ENOTSUPP; + + return 0; +} + +/** + * bsec_read_SR_lock() - read SR lock (Shadowing) + * @base: base address of bsec IP + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: true if locked else false + */ +static bool bsec_read_SR_lock(void __iomem *base, u32 otp) +{ + return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp); +} + +/** + * bsec_read_SP_lock() - read SP lock (program Lock) + * @base: base address of bsec IP + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: true if locked else false + */ +static bool bsec_read_SP_lock(void __iomem *base, u32 otp) +{ + return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp); +} + +/** + * bsec_SW_lock() - manage SW lock (Write in Shadow) + * @base: base address of bsec IP + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: true if locked else false + */ +static bool bsec_read_SW_lock(void __iomem *base, u32 otp) +{ + return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp); +} + +/** + * bsec_power_safmem() - Activate or deactivate safmem power + * @base: base address of bsec IP + * @power: true to power up , false to power down + * Return: 0 if succeed + */ +static int bsec_power_safmem(void __iomem *base, bool power) +{ + u32 val; + u32 mask; + + if (power) { + setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP); + mask = BSEC_MODE_PWR_MASK; + } else { + clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP); + mask = 0; + } + + /* waiting loop */ + return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF, + val, (val & BSEC_MODE_PWR_MASK) == mask, + BSEC_TIMEOUT_US); +} + +/** + * bsec_shadow_register() - copy safmen otp to bsec data + * @dev: bsec IP device + * @base: base address of bsec IP + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: 0 if no error + */ +static int bsec_shadow_register(struct udevice *dev, void __iomem *base, u32 otp) +{ + u32 val; + int ret; + bool power_up = false; + + /* check if shadowing of otp is locked */ + if (bsec_read_SR_lock(base, otp)) + dev_dbg(dev, "OTP %d is locked and refreshed with 0\n", + otp); + + /* check if safemem is power up */ + val = readl(base + BSEC_OTP_STATUS_OFF); + if (!(val & BSEC_MODE_PWR_MASK)) { + ret = bsec_power_safmem(base, true); + if (ret) + return ret; + power_up = true; + } + /* set BSEC_OTP_CTRL_OFF with the otp value*/ + writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF); + + /* check otp status*/ + ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF, + val, (val & BSEC_MODE_BUSY_MASK) == 0, + BSEC_TIMEOUT_US); + if (ret) + return ret; + + ret = bsec_check_error(base, otp); + + if (power_up) + bsec_power_safmem(base, false); + + return ret; +} + +/** + * bsec_read_shadow() - read an otp data value from shadow + * @dev: bsec IP device + * @base: base address of bsec IP + * @val: read value + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: 0 if no error + */ +static int bsec_read_shadow(struct udevice *dev, void __iomem *base, u32 *val, + u32 otp) +{ + *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32)); + + return bsec_check_error(base, otp); +} + +/** + * bsec_write_shadow() - write value in BSEC data register in shadow + * @dev: bsec IP device + * @base: base address of bsec IP + * @val: value to write + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: 0 if no error + */ +static int bsec_write_shadow(struct udevice *dev, void __iomem *base, u32 val, u32 otp) +{ + /* check if programming of otp is locked */ + if (bsec_read_SW_lock(base, otp)) + dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp); + + writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32)); + + return bsec_check_error(base, otp); +} + +/** + * bsec_program_otp() - program a bit in SAFMEM + * @dev: bsec IP device + * @base: base address of bsec IP + * @val: value to program + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * after the function the otp data is not refreshed in shadow + * Return: 0 if no error + */ +static int bsec_program_otp(struct udevice *dev, void __iomem *base, u32 val, u32 otp) +{ + u32 ret; + bool power_up = false; + + if (bsec_read_SP_lock(base, otp)) + dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp); + + if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM)) + dev_dbg(dev, "Global lock, prog will be ignore\n"); + + /* check if safemem is power up */ + if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) { + ret = bsec_power_safmem(base, true); + if (ret) + return ret; + + power_up = true; + } + /* set value in write register*/ + writel(val, base + BSEC_OTP_WRDATA_OFF); + + /* set BSEC_OTP_CTRL_OFF with the otp value */ + writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF); + + /* check otp status*/ + ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF, + val, (val & BSEC_MODE_BUSY_MASK) == 0, + BSEC_TIMEOUT_US); + if (ret) + return ret; + + if (val & BSEC_MODE_PROGFAIL_MASK) + ret = -EACCES; + else + ret = bsec_check_error(base, otp); + + if (power_up) + bsec_power_safmem(base, false); + + return ret; +} + +/** + * bsec_permanent_lock_otp() - permanent lock of OTP in SAFMEM + * @dev: bsec IP device + * @base: base address of bsec IP + * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) + * Return: 0 if no error + */ +static int bsec_permanent_lock_otp(struct udevice *dev, void __iomem *base, uint32_t otp) +{ + int ret; + bool power_up = false; + u32 val, addr; + + /* check if safemem is power up */ + if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) { + ret = bsec_power_safmem(base, true); + if (ret) + return ret; + + power_up = true; + } + + /* + * low OTPs = 2 bits word for low OTPs, 1 bits per word for upper OTP + * and only 16 bits used in WRDATA + */ + if (otp < BSEC_OTP_UPPER_START) { + addr = otp / 8; + val = 0x03 << ((otp * 2) & 0xF); + } else { + addr = BSEC_OTP_UPPER_START / 8 + + ((otp - BSEC_OTP_UPPER_START) / 16); + val = 0x01 << (otp & 0xF); + } + + /* set value in write register*/ + writel(val, base + BSEC_OTP_WRDATA_OFF); + + /* set BSEC_OTP_CTRL_OFF with the otp addr and lock request*/ + writel(addr | BSEC_WRITE | BSEC_LOCK, base + BSEC_OTP_CTRL_OFF); + + /* check otp status*/ + ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF, + val, (val & BSEC_MODE_BUSY_MASK) == 0, + BSEC_TIMEOUT_US); + if (ret) + return ret; + + if (val & BSEC_MODE_PROGFAIL_MASK) + ret = -EACCES; + else + ret = bsec_check_error(base, otp); + + if (power_up) + bsec_power_safmem(base, false); + + return ret; +} + +/* BSEC MISC driver *******************************************************/ +struct stm32mp_bsec_plat { + void __iomem *base; +}; + +struct stm32mp_bsec_priv { + struct udevice *tee; +}; + +struct stm32mp_bsec_drvdata { + int size; + bool ta; +}; + +static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) +{ + struct stm32mp_bsec_plat *plat; + u32 tmp_data = 0; + int ret; + + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) + return stm32_smc(STM32_SMC_BSEC, + STM32_SMC_READ_OTP, + otp, 0, val); + + plat = dev_get_plat(dev); + + /* read current shadow value */ + ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp); + if (ret) + return ret; + + /* copy otp in shadow */ + ret = bsec_shadow_register(dev, plat->base, otp); + if (ret) + return ret; + + ret = bsec_read_shadow(dev, plat->base, val, otp); + if (ret) + return ret; + + /* restore shadow value */ + ret = bsec_write_shadow(dev, plat->base, tmp_data, otp); + + return ret; +} + +static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) +{ + struct stm32mp_bsec_plat *plat; + + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) + return stm32_smc(STM32_SMC_BSEC, + STM32_SMC_READ_SHADOW, + otp, 0, val); + + plat = dev_get_plat(dev); + + return bsec_read_shadow(dev, plat->base, val, otp); +} + +static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) +{ + struct stm32mp_bsec_plat *plat = dev_get_plat(dev); + u32 wrlock; + + /* return OTP permanent write lock status */ + wrlock = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp); + + *val = 0; + if (wrlock) + *val = BSEC_LOCK_PERM; + + return 0; +} + +static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) +{ + struct stm32mp_bsec_plat *plat; + + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) + return stm32_smc_exec(STM32_SMC_BSEC, + STM32_SMC_PROG_OTP, + otp, val); + + plat = dev_get_plat(dev); + + return bsec_program_otp(dev, plat->base, val, otp); + +} + +static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) +{ + struct stm32mp_bsec_plat *plat; + + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) + return stm32_smc_exec(STM32_SMC_BSEC, + STM32_SMC_WRITE_SHADOW, + otp, val); + + plat = dev_get_plat(dev); + + return bsec_write_shadow(dev, plat->base, val, otp); +} + +static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) +{ + struct stm32mp_bsec_plat *plat; + + /* only permanent write lock is supported in U-Boot */ + if (!(val & BSEC_LOCK_PERM)) { + dev_dbg(dev, "lock option without BSEC_LOCK_PERM: %x\n", val); + return 0; /* nothing to do */ + } + + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) + return stm32_smc_exec(STM32_SMC_BSEC, + STM32_SMC_WRLOCK_OTP, + otp, 0); + + plat = dev_get_plat(dev); + + return bsec_permanent_lock_otp(dev, plat->base, otp); +} + +static int bsec_pta_open_session(struct udevice *tee, u32 *tee_session) +{ + const struct tee_optee_ta_uuid uuid = PTA_BSEC_UUID; + struct tee_open_session_arg arg; + int rc; + + memset(&arg, 0, sizeof(arg)); + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + arg.clnt_login = TEE_LOGIN_REE_KERNEL; + rc = tee_open_session(tee, &arg, 0, NULL); + if (rc < 0) + return -ENODEV; + + *tee_session = arg.session; + + return 0; +} + +static int bsec_optee_open(struct udevice *dev) +{ + struct stm32mp_bsec_priv *priv = dev_get_priv(dev); + struct udevice *tee; + u32 tee_session; + int rc; + + tee = tee_find_device(NULL, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + /* try to open the STM32 BSEC TA */ + rc = bsec_pta_open_session(tee, &tee_session); + if (rc) + return rc; + + tee_close_session(tee, tee_session); + + priv->tee = tee; + + return 0; +} + +static int bsec_optee_pta(struct udevice *dev, int cmd, int type, int offset, + void *buff, ulong size) +{ + struct stm32mp_bsec_priv *priv = dev_get_priv(dev); + u32 tee_session; + struct tee_invoke_arg arg; + struct tee_param param[2]; + struct tee_shm *fw_shm; + int rc; + + rc = bsec_pta_open_session(priv->tee, &tee_session); + if (rc) + return rc; + + rc = tee_shm_register(priv->tee, buff, size, 0, &fw_shm); + if (rc) + goto close_session; + + memset(&arg, 0, sizeof(arg)); + arg.func = cmd; + arg.session = tee_session; + + memset(param, 0, sizeof(param)); + + param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT; + param[0].u.value.a = offset; + param[0].u.value.b = type; + + if (cmd == PTA_BSEC_WRITE_MEM) + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + else + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT; + + param[1].u.memref.shm = fw_shm; + param[1].u.memref.size = size; + + rc = tee_invoke_func(priv->tee, &arg, 2, param); + if (rc < 0 || arg.ret != 0) { + dev_err(priv->tee, + "PTA_BSEC invoke failed TEE err: %x, err:%x\n", + arg.ret, rc); + if (!rc) + rc = -EIO; + } + + tee_shm_free(fw_shm); + +close_session: + tee_close_session(priv->tee, tee_session); + + return rc; +} + +static int stm32mp_bsec_read(struct udevice *dev, int offset, + void *buf, int size) +{ + struct stm32mp_bsec_priv *priv = dev_get_priv(dev); + struct stm32mp_bsec_drvdata *data = (struct stm32mp_bsec_drvdata *)dev_get_driver_data(dev); + int ret; + int i; + bool shadow = true, lock = false; + int nb_otp = size / sizeof(u32); + int otp, cmd; + unsigned int offs = offset; + + if (offs >= STM32_BSEC_LOCK_OFFSET) { + offs -= STM32_BSEC_LOCK_OFFSET; + lock = true; + } else if (offs >= STM32_BSEC_OTP_OFFSET) { + offs -= STM32_BSEC_OTP_OFFSET; + shadow = false; + } + + if ((offs % 4) || (size % 4) || !size) + return -EINVAL; + + if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) { + cmd = FUSE_ACCESS; + if (shadow) + cmd = SHADOW_ACCESS; + if (lock) + cmd = LOCK_ACCESS; + ret = bsec_optee_pta(dev, PTA_BSEC_READ_MEM, cmd, offs, buf, size); + if (ret) + return ret; + + return size; + } + + otp = offs / sizeof(u32); + + for (i = otp; i < (otp + nb_otp) && i < data->size; i++) { + u32 *addr = &((u32 *)buf)[i - otp]; + + if (lock) + ret = stm32mp_bsec_read_lock(dev, addr, i); + else if (shadow) + ret = stm32mp_bsec_read_shadow(dev, addr, i); + else + ret = stm32mp_bsec_read_otp(dev, addr, i); + + if (ret) + break; + } + if (ret) + return ret; + else + return (i - otp) * 4; +} + +static int stm32mp_bsec_write(struct udevice *dev, int offset, + const void *buf, int size) +{ + struct stm32mp_bsec_priv *priv = dev_get_priv(dev); + struct stm32mp_bsec_drvdata *data = (struct stm32mp_bsec_drvdata *)dev_get_driver_data(dev); + int ret = 0; + int i; + bool shadow = true, lock = false; + int nb_otp = size / sizeof(u32); + int otp, cmd; + unsigned int offs = offset; + + if (offs >= STM32_BSEC_LOCK_OFFSET) { + offs -= STM32_BSEC_LOCK_OFFSET; + lock = true; + } else if (offs >= STM32_BSEC_OTP_OFFSET) { + offs -= STM32_BSEC_OTP_OFFSET; + shadow = false; + } + + if ((offs % 4) || (size % 4) || !size) + return -EINVAL; + + if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) { + cmd = FUSE_ACCESS; + if (shadow) + cmd = SHADOW_ACCESS; + if (lock) + cmd = LOCK_ACCESS; + ret = bsec_optee_pta(dev, PTA_BSEC_WRITE_MEM, cmd, offs, (void *)buf, size); + if (ret) + return ret; + + return size; + } + + otp = offs / sizeof(u32); + + for (i = otp; i < otp + nb_otp && i < data->size; i++) { + u32 *val = &((u32 *)buf)[i - otp]; + + if (lock) + ret = stm32mp_bsec_write_lock(dev, *val, i); + else if (shadow) + ret = stm32mp_bsec_write_shadow(dev, *val, i); + else + ret = stm32mp_bsec_write_otp(dev, *val, i); + if (ret) + break; + } + if (ret) + return ret; + else + return (i - otp) * 4; +} + +static const struct misc_ops stm32mp_bsec_ops = { + .read = stm32mp_bsec_read, + .write = stm32mp_bsec_write, +}; + +static int stm32mp_bsec_of_to_plat(struct udevice *dev) +{ + struct stm32mp_bsec_plat *plat = dev_get_plat(dev); + + plat->base = dev_read_addr_ptr(dev); + + return 0; +} + +static int stm32mp_bsec_probe(struct udevice *dev) +{ + struct stm32mp_bsec_drvdata *data = (struct stm32mp_bsec_drvdata *)dev_get_driver_data(dev); + int otp; + struct stm32mp_bsec_plat *plat; + struct clk_bulk clk_bulk; + int ret; + + ret = clk_get_bulk(dev, &clk_bulk); + if (!ret) { + ret = clk_enable_bulk(&clk_bulk); + if (ret) + return ret; + } + + if (IS_ENABLED(CONFIG_OPTEE)) + ret = bsec_optee_open(dev); + else + ret = -ENOTSUPP; + /* failed if OP-TEE TA is required */ + if (data->ta && !ret) + return ret; + + /* + * update unlocked shadow for OTP cleared by the rom code + * only executed in SPL, it is done in TF-A for TFABOOT + */ + if (IS_ENABLED(CONFIG_XPL_BUILD) && !data->ta) { + plat = dev_get_plat(dev); + + /* here 57 is the value for STM32MP15x ROM code, only MPU with SPL support*/ + for (otp = 57; otp < data->size; otp++) + if (!bsec_read_SR_lock(plat->base, otp)) + bsec_shadow_register(dev, plat->base, otp); + } + + return 0; +} + +static const struct stm32mp_bsec_drvdata stm32mp13_data = { + .size = 96, + .ta = true, +}; + +static const struct stm32mp_bsec_drvdata stm32mp15_data = { + .size = 96, + .ta = false, +}; + +static const struct stm32mp_bsec_drvdata stm32mp25_data = { + .size = 368, /* 384 but no access to HWKEY and STM32PRVKEY */ + .ta = true, +}; + +static const struct udevice_id stm32mp_bsec_ids[] = { + { .compatible = "st,stm32mp13-bsec", .data = (ulong)&stm32mp13_data}, + { .compatible = "st,stm32mp15-bsec", .data = (ulong)&stm32mp15_data}, + { .compatible = "st,stm32mp25-bsec", .data = (ulong)&stm32mp25_data}, + {} +}; + +U_BOOT_DRIVER(stm32mp_bsec) = { + .name = "stm32mp_bsec", + .id = UCLASS_MISC, + .of_match = stm32mp_bsec_ids, + .of_to_plat = stm32mp_bsec_of_to_plat, + .plat_auto = sizeof(struct stm32mp_bsec_plat), + .priv_auto = sizeof(struct stm32mp_bsec_priv), + .ops = &stm32mp_bsec_ops, + .probe = stm32mp_bsec_probe, +}; + +bool bsec_dbgswenable(void) +{ + struct udevice *dev; + struct stm32mp_bsec_plat *plat; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret || !dev) { + log_debug("bsec driver not available\n"); + return false; + } + + plat = dev_get_plat(dev); + if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE) + return true; + + return false; +} + +u32 get_otp(int index, int shift, int mask) +{ + int ret; + struct udevice *dev; + u32 otp = 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), + &dev); + + if (!ret) + ret = misc_read(dev, STM32_BSEC_SHADOW(index), + &otp, sizeof(otp)); + + return (otp >> shift) & mask; +} diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c new file mode 100644 index 00000000000..040a70f581c --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#include <command.h> +#include <console.h> +#include <log.h> +#include <misc.h> +#include <asm/arch/bsec.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <linux/printk.h> + +/* + * Closed device: OTP0 + * STM32MP15x: bit 6 of OPT0 + * STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device + */ +#define STM32_OTP_CLOSE_ID 0 +#define STM32_OTP_STM32MP13X_CLOSE_MASK 0x3F +#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6) + +/* PKH is the first element of the key list */ +#define STM32KEY_PKH 0 + +struct stm32key { + char *name; + char *desc; + u8 start; + u8 size; +}; + +const struct stm32key stm32mp13_list[] = { + [STM32KEY_PKH] = { + .name = "PKHTH", + .desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm)", + .start = 24, + .size = 8, + }, + { + .name = "EDMK", + .desc = "Encryption/Decryption Master Key", + .start = 92, + .size = 4, + } +}; + +const struct stm32key stm32mp15_list[] = { + [STM32KEY_PKH] = { + .name = "PKH", + .desc = "Hash of the ECC Public Key (ECDSA is the authentication algorithm)", + .start = 24, + .size = 8, + } +}; + +/* index of current selected key in stm32key list, 0 = PKH by default */ +static u8 stm32key_index; + +static u8 get_key_nb(void) +{ + if (IS_ENABLED(CONFIG_STM32MP13X)) + return ARRAY_SIZE(stm32mp13_list); + + if (IS_ENABLED(CONFIG_STM32MP15X)) + return ARRAY_SIZE(stm32mp15_list); +} + +static const struct stm32key *get_key(u8 index) +{ + if (IS_ENABLED(CONFIG_STM32MP13X)) + return &stm32mp13_list[index]; + + if (IS_ENABLED(CONFIG_STM32MP15X)) + return &stm32mp15_list[index]; +} + +static u32 get_otp_close_mask(void) +{ + if (IS_ENABLED(CONFIG_STM32MP13X)) + return STM32_OTP_STM32MP13X_CLOSE_MASK; + + if (IS_ENABLED(CONFIG_STM32MP15X)) + return STM32_OTP_STM32MP15X_CLOSE_MASK; +} + +static int get_misc_dev(struct udevice **dev) +{ + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), dev); + if (ret) + log_err("Can't find stm32mp_bsec driver\n"); + + return ret; +} + +static void read_key_value(const struct stm32key *key, u32 addr) +{ + int i; + + for (i = 0; i < key->size; i++) { + printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i, + addr, __be32_to_cpu(*(u32 *)addr)); + addr += 4; + } +} + +static int read_key_otp(struct udevice *dev, const struct stm32key *key, bool print, bool *locked) +{ + int i, word, ret; + int nb_invalid = 0, nb_zero = 0, nb_lock = 0, nb_lock_err = 0; + u32 val, lock; + bool status; + + for (i = 0, word = key->start; i < key->size; i++, word++) { + ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); + if (ret != 4) + val = ~0x0; + ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); + if (ret != 4) + lock = BSEC_LOCK_ERROR; + if (print) + printf("%s OTP %i: %08x lock : %08x\n", key->name, word, val, lock); + if (val == ~0x0) + nb_invalid++; + else if (val == 0x0) + nb_zero++; + if (lock & BSEC_LOCK_PERM) + nb_lock++; + if (lock & BSEC_LOCK_ERROR) + nb_lock_err++; + } + + status = nb_lock_err || (nb_lock == key->size); + if (locked) + *locked = status; + if (nb_lock_err && print) + printf("%s lock is invalid!\n", key->name); + else if (!status && print) + printf("%s is not locked!\n", key->name); + + if (nb_invalid == key->size) { + if (print) + printf("%s is invalid!\n", key->name); + return -EINVAL; + } + if (nb_zero == key->size) { + if (print) + printf("%s is free!\n", key->name); + return -ENOENT; + } + + return 0; +} + +static int read_close_status(struct udevice *dev, bool print, bool *closed) +{ + int word, ret, result; + u32 val, lock, mask; + bool status; + + result = 0; + word = STM32_OTP_CLOSE_ID; + ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4); + if (ret < 0) + result = ret; + if (ret != 4) + val = 0x0; + + ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4); + if (ret < 0) + result = ret; + if (ret != 4) + lock = BSEC_LOCK_ERROR; + + mask = get_otp_close_mask(); + status = (val & mask) == mask; + if (closed) + *closed = status; + if (print) + printf("OTP %d: closed status: %d lock : %08x\n", word, status, lock); + + return result; +} + +static int fuse_key_value(struct udevice *dev, const struct stm32key *key, u32 addr, bool print) +{ + u32 word, val; + int i, ret; + + for (i = 0, word = key->start; i < key->size; i++, word++, addr += 4) { + val = __be32_to_cpu(*(u32 *)addr); + if (print) + printf("Fuse %s OTP %i : %08x\n", key->name, word, val); + + ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4); + if (ret != 4) { + log_err("Fuse %s OTP %i failed\n", key->name, word); + return ret; + } + /* on success, lock the OTP for the key */ + val = BSEC_LOCK_PERM; + ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4); + if (ret != 4) { + log_err("Lock %s OTP %i failed\n", key->name, word); + return ret; + } + } + + return 0; +} + +static int confirm_prog(void) +{ + puts("Warning: Programming fuses is an irreversible operation!\n" + " This may brick your system.\n" + " Use this command only if you are sure of what you are doing!\n" + "\nReally perform this fuse programming? <y/N>\n"); + + if (confirm_yesno()) + return 1; + + puts("Fuse programming aborted\n"); + return 0; +} + +static void display_key_info(const struct stm32key *key) +{ + printf("%s : %s\n", key->name, key->desc); + printf("\tOTP%d..%d\n", key->start, key->start + key->size); +} + +static int do_stm32key_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int i; + + for (i = 0; i < get_key_nb(); i++) + display_key_info(get_key(i)); + + return CMD_RET_SUCCESS; +} + +static int do_stm32key_select(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct stm32key *key; + int i; + + if (argc == 1) { + printf("Selected key:\n"); + key = get_key(stm32key_index); + display_key_info(key); + return CMD_RET_SUCCESS; + } + + for (i = 0; i < get_key_nb(); i++) { + key = get_key(i); + if (!strcmp(key->name, argv[1])) { + printf("%s selected\n", key->name); + stm32key_index = i; + return CMD_RET_SUCCESS; + } + } + + printf("Unknown key %s\n", argv[1]); + + return CMD_RET_FAILURE; +} + +static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct stm32key *key; + struct udevice *dev; + u32 addr; + int ret, i; + int result; + + ret = get_misc_dev(&dev); + + if (argc == 1) { + if (ret) + return CMD_RET_FAILURE; + key = get_key(stm32key_index); + ret = read_key_otp(dev, key, true, NULL); + if (ret != -ENOENT) + return CMD_RET_FAILURE; + return CMD_RET_SUCCESS; + } + + if (!strcmp("-a", argv[1])) { + if (ret) + return CMD_RET_FAILURE; + result = CMD_RET_SUCCESS; + for (i = 0; i < get_key_nb(); i++) { + key = get_key(i); + ret = read_key_otp(dev, key, true, NULL); + if (ret != -ENOENT) + result = CMD_RET_FAILURE; + } + ret = read_close_status(dev, true, NULL); + if (ret) + result = CMD_RET_FAILURE; + + return result; + } + + addr = hextoul(argv[1], NULL); + if (!addr) + return CMD_RET_USAGE; + + key = get_key(stm32key_index); + printf("Read %s at 0x%08x\n", key->name, addr); + read_key_value(key, addr); + + return CMD_RET_SUCCESS; +} + +static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct stm32key *key = get_key(stm32key_index); + struct udevice *dev; + u32 addr; + int ret; + bool yes = false, lock; + + if (argc < 2) + return CMD_RET_USAGE; + + if (argc == 3) { + if (strcmp(argv[1], "-y")) + return CMD_RET_USAGE; + yes = true; + } + + addr = hextoul(argv[argc - 1], NULL); + if (!addr) + return CMD_RET_USAGE; + + ret = get_misc_dev(&dev); + if (ret) + return CMD_RET_FAILURE; + + if (read_key_otp(dev, key, !yes, &lock) != -ENOENT) { + printf("Error: can't fuse again the OTP\n"); + return CMD_RET_FAILURE; + } + if (lock) { + printf("Error: %s is locked\n", key->name); + return CMD_RET_FAILURE; + } + + if (!yes) { + printf("Writing %s with\n", key->name); + read_key_value(key, addr); + } + + if (!yes && !confirm_prog()) + return CMD_RET_FAILURE; + + if (fuse_key_value(dev, key, addr, !yes)) + return CMD_RET_FAILURE; + + printf("%s updated !\n", key->name); + + return CMD_RET_SUCCESS; +} + +static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct stm32key *key; + bool yes, lock, closed; + struct udevice *dev; + u32 val; + int ret; + + yes = false; + if (argc == 2) { + if (strcmp(argv[1], "-y")) + return CMD_RET_USAGE; + yes = true; + } + + ret = get_misc_dev(&dev); + if (ret) + return CMD_RET_FAILURE; + + if (read_close_status(dev, !yes, &closed)) + return CMD_RET_FAILURE; + + if (closed) { + printf("Error: already closed!\n"); + return CMD_RET_FAILURE; + } + + /* check PKH status before to close */ + key = get_key(STM32KEY_PKH); + ret = read_key_otp(dev, key, !yes, &lock); + if (ret) { + if (ret == -ENOENT) + printf("Error: %s not programmed!\n", key->name); + return CMD_RET_FAILURE; + } + if (!lock) + printf("Warning: %s not locked!\n", key->name); + + if (!yes && !confirm_prog()) + return CMD_RET_FAILURE; + + val = get_otp_close_mask(); + ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4); + if (ret != 4) { + printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID); + return CMD_RET_FAILURE; + } + + printf("Device is closed !\n"); + + return CMD_RET_SUCCESS; +} + +U_BOOT_LONGHELP(stm32key, + "list : list the supported key with description\n" + "stm32key select [<key>] : Select the key identified by <key> or display the key used for read/fuse command\n" + "stm32key read [<addr> | -a ] : Read the curent key at <addr> or current / all (-a) key in OTP\n" + "stm32key fuse [-y] <addr> : Fuse the current key at addr in OTP\n" + "stm32key close [-y] : Close the device\n"); + +U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text, + U_BOOT_SUBCMD_MKENT(list, 1, 0, do_stm32key_list), + U_BOOT_SUBCMD_MKENT(select, 2, 0, do_stm32key_select), + U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read), + U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse), + U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close)); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig new file mode 100644 index 00000000000..589276282e4 --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -0,0 +1,41 @@ +config CMD_STM32PROG + bool "command stm32prog for STM32CudeProgrammer" + select DFU + select DFU_RAM + select DFU_VIRT + select PARTITION_TYPE_GUID + imply CMD_GPT if MMC + imply CMD_MTD if MTD + imply DFU_MMC if MMC + imply DFU_MTD if MTD + help + activate a specific command stm32prog for STM32MP soc family + witch update the device with the tools STM32CubeProgrammer + NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based + on U-Boot DFU framework + +config CMD_STM32PROG_USB + bool "support stm32prog over USB" + depends on CMD_STM32PROG + depends on USB_GADGET_DOWNLOAD + default y + help + activate the command "stm32prog usb" for STM32MP soc family + witch update the device with the tools STM32CubeProgrammer, + using USB with DFU protocol + +config CMD_STM32PROG_SERIAL + bool "support stm32prog over UART" + depends on CMD_STM32PROG + default y + help + activate the command "stm32prog serial" for STM32MP soc family + with the tools STM32CubeProgrammer using U-Boot serial device + and UART protocol. + +config CMD_STM32PROG_OTP + bool "support stm32prog for OTP update" + depends on CMD_STM32PROG + default y if ARM_SMCCC || OPTEE + help + Support the OTP update with the command "stm32prog" for STM32MP diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile b/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile new file mode 100644 index 00000000000..b57e1bf870b --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020, STMicroelectronics - All Rights Reserved +# + +obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog.o +obj-$(CONFIG_CMD_STM32PROG) += stm32prog.o +obj-$(CONFIG_CMD_STM32PROG_SERIAL) += stm32prog_serial.o +obj-$(CONFIG_CMD_STM32PROG_USB) += stm32prog_usb.o diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c new file mode 100644 index 00000000000..04640e476e6 --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +#include <bootm.h> +#include <command.h> +#include <dfu.h> +#include <image.h> +#include <asm/arch/stm32prog.h> +#include <linux/printk.h> +#include "stm32prog.h" + +struct stm32prog_data *stm32prog_data; + +static void enable_vidconsole(void) +{ + char *stdname; + char buf[64]; + + stdname = env_get("stdout"); + if (!stdname || !strstr(stdname, "vidconsole")) { + if (!stdname) + snprintf(buf, sizeof(buf), "serial,vidconsole"); + else + snprintf(buf, sizeof(buf), "%s,vidconsole", stdname); + env_set("stdout", buf); + } + + stdname = env_get("stderr"); + if (!stdname || !strstr(stdname, "vidconsole")) { + if (!stdname) + snprintf(buf, sizeof(buf), "serial,vidconsole"); + else + snprintf(buf, sizeof(buf), "%s,vidconsole", stdname); + env_set("stderr", buf); + } +} + +static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + ulong addr, size; + int dev, ret; + enum stm32prog_link_t link = LINK_UNDEFINED; + bool reset = false; + struct image_header_s header; + struct stm32prog_data *data; + + if (argc < 3 || argc > 5) + return CMD_RET_USAGE; + + if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) && !strcmp(argv[1], "usb")) + link = LINK_USB; + else if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && !strcmp(argv[1], "serial")) + link = LINK_SERIAL; + + if (link == LINK_UNDEFINED) { + log_err("not supported link=%s\n", argv[1]); + return CMD_RET_USAGE; + } + + dev = (int)dectoul(argv[2], NULL); + + addr = CONFIG_SYS_LOAD_ADDR; + size = 0; + if (argc > 3) { + addr = hextoul(argv[3], NULL); + if (!addr) + return CMD_RET_FAILURE; + } + if (argc > 4) + size = hextoul(argv[4], NULL); + + /* check STM32IMAGE presence */ + if (size == 0) { + stm32prog_header_check(addr, &header); + if (header.type == HEADER_STM32IMAGE) { + size = header.image_length + header.length; + } + } + + if (IS_ENABLED(CONFIG_VIDEO)) + enable_vidconsole(); + + data = (struct stm32prog_data *)malloc(sizeof(*data)); + + if (!data) { + log_err("Alloc failed."); + return CMD_RET_FAILURE; + } + stm32prog_data = data; + + ret = stm32prog_init(data, addr, size); + if (ret) + log_debug("Invalid or missing layout file at 0x%lx.\n", addr); + + /* prepare DFU for device read/write */ + ret = stm32prog_dfu_init(data); + if (ret) + goto cleanup; + + switch (link) { + case LINK_SERIAL: + ret = stm32prog_serial_init(data, dev); + if (ret) + goto cleanup; + reset = stm32prog_serial_loop(data); + break; + case LINK_USB: + reset = stm32prog_usb_loop(data, dev); + break; + default: + goto cleanup; + } + + stm32prog_clean(data); + free(stm32prog_data); + stm32prog_data = NULL; + + puts("Download done\n"); + + if (data->uimage) { + char boot_addr_start[20]; + char dtb_addr[20]; + char initrd_addr[40]; + char *fdt_arg, *initrd_arg; + const void *uimage = (void *)data->uimage; + const void *dtb = (void *)data->dtb; + const void *initrd = (void *)data->initrd; + struct bootm_info bmi; + + fdt_arg = dtb_addr; + if (!dtb) + fdt_arg = env_get("fdtcontroladdr"); + else + snprintf(dtb_addr, sizeof(dtb_addr) - 1, "0x%p", dtb); + + snprintf(boot_addr_start, sizeof(boot_addr_start) - 1, + "0x%p", uimage); + + initrd_arg = NULL; + if (initrd) { + snprintf(initrd_addr, sizeof(initrd_addr) - 1, + "0x%p:0x%zx", initrd, data->initrd_size); + initrd_arg = initrd_addr; + } + + printf("Booting kernel at %s %s %s...\n\n\n", boot_addr_start, + initrd_arg ?: "-", fdt_arg); + + bootm_init(&bmi); + bmi.addr_img = boot_addr_start; + bmi.conf_ramdisk = initrd_arg; + bmi.conf_fdt = fdt_arg; + + /* Try bootm for legacy and FIT format image */ + if (genimg_get_format(uimage) != IMAGE_FORMAT_INVALID) + bootm_run(&bmi); + else if (IS_ENABLED(CONFIG_CMD_BOOTZ)) + bootz_run(&bmi); + } + if (data->script) + cmd_source_script(data->script, NULL, NULL); + + if (reset) { + puts("Reset...\n"); + run_command("reset", 0); + } + + return CMD_RET_SUCCESS; + +cleanup: + stm32prog_clean(data); + free(stm32prog_data); + stm32prog_data = NULL; + + return CMD_RET_FAILURE; +} + +U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog, + "start communication with tools STM32Cubeprogrammer", + "<link> <dev> [<addr>] [<size>]\n" + " <link> = serial|usb\n" + " <dev> = device instance\n" + " <addr> = address of flashlayout\n" + " <size> = size of flashlayout (optional for image with STM32 header)\n" +); + +bool stm32prog_get_fsbl_nor(void) +{ + if (stm32prog_data) + return stm32prog_data->fsbl_nor_detected; + + return false; +} diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c new file mode 100644 index 00000000000..353aecc09de --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -0,0 +1,2064 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +#include <command.h> +#include <console.h> +#include <dfu.h> +#include <image.h> +#include <malloc.h> +#include <misc.h> +#include <mmc.h> +#include <part.h> +#include <tee.h> +#include <asm/arch/stm32mp1_smc.h> +#include <asm/global_data.h> +#include <dm/device_compat.h> +#include <dm/uclass.h> +#include <jffs2/load_kernel.h> +#include <linux/list.h> +#include <linux/list_sort.h> +#include <linux/mtd/mtd.h> +#include <linux/printk.h> +#include <linux/sizes.h> + +#include "stm32prog.h" + +/* Primary GPT header size for 128 entries : 17kB = 34 LBA of 512B */ +#define GPT_HEADER_SZ 34 + +#define OPT_SELECT BIT(0) +#define OPT_EMPTY BIT(1) +#define OPT_DELETE BIT(2) + +#define IS_SELECT(part) ((part)->option & OPT_SELECT) +#define IS_EMPTY(part) ((part)->option & OPT_EMPTY) +#define IS_DELETE(part) ((part)->option & OPT_DELETE) + +#define ALT_BUF_LEN SZ_1K + +#define ROOTFS_MMC0_UUID \ + EFI_GUID(0xE91C4E10, 0x16E6, 0x4C0E, \ + 0xBD, 0x0E, 0x77, 0xBE, 0xCF, 0x4A, 0x35, 0x82) + +#define ROOTFS_MMC1_UUID \ + EFI_GUID(0x491F6117, 0x415D, 0x4F53, \ + 0x88, 0xC9, 0x6E, 0x0D, 0xE5, 0x4D, 0xEA, 0xC6) + +#define ROOTFS_MMC2_UUID \ + EFI_GUID(0xFD58F1C7, 0xBE0D, 0x4338, \ + 0x88, 0xE9, 0xAD, 0x8F, 0x05, 0x0A, 0xEB, 0x18) + +/* RAW partition (binary / bootloader) used Linux - reserved UUID */ +#define LINUX_RESERVED_UUID "8DA63339-0007-60C0-C436-083AC8230908" + +/* + * unique partition guid (uuid) for partition named "rootfs" + * on each MMC instance = SD Card or eMMC + * allow fixed kernel bootcmd: "rootf=PARTUID=e91c4e10-..." + */ +static const efi_guid_t uuid_mmc[3] = { + ROOTFS_MMC0_UUID, + ROOTFS_MMC1_UUID, + ROOTFS_MMC2_UUID +}; + +/* + * GUID value defined in the FWU specification for identification + * of the FWU metadata partition. + */ +#define FWU_MDATA_UUID "8a7a84a0-8387-40f6-ab41-a8b9a5a60d23" + +/* FIP type partition UUID used by TF-A*/ +#define FIP_TYPE_UUID "19D5DF83-11B0-457B-BE2C-7559C13142A5" + +/* unique partition guid (uuid) for FIP partitions A/B */ +#define FIP_A_UUID \ + EFI_GUID(0x4FD84C93, 0x54EF, 0x463F, \ + 0xA7, 0xEF, 0xAE, 0x25, 0xFF, 0x88, 0x70, 0x87) + +#define FIP_B_UUID \ + EFI_GUID(0x09C54952, 0xD5BF, 0x45AF, \ + 0xAC, 0xEE, 0x33, 0x53, 0x03, 0x76, 0x6F, 0xB3) + +static const char * const fip_part_name[] = { + "fip-a", + "fip-b" +}; + +static const efi_guid_t fip_part_uuid[] = { + FIP_A_UUID, + FIP_B_UUID +}; + +/* order of column in flash layout file */ +enum stm32prog_col_t { + COL_OPTION, + COL_ID, + COL_NAME, + COL_TYPE, + COL_IP, + COL_OFFSET, + COL_NB_STM32 +}; + +#define FIP_TOC_HEADER_NAME 0xAA640001 + +struct fip_toc_header { + u32 name; + u32 serial_number; + u64 flags; +}; + +#define TA_NVMEM_UUID { 0x1a8342cc, 0x81a5, 0x4512, \ + { 0x99, 0xfe, 0x9e, 0x2b, 0x3e, 0x37, 0xd6, 0x26 } } + +/* + * Read NVMEM memory for STM32CubeProgrammer + * + * [in] value[0].a: Type (0 for OTP access) + * [out] memref[1].buffer Output buffer to return all read values + * [out] memref[1].size Size of buffer to be read + * + * Return codes: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + */ +#define TA_NVMEM_READ 0x0 + +/* + * Write NVMEM memory for STM32CubeProgrammer + * + * [in] value[0].a Type (0 for OTP access) + * [in] memref[1].buffer Input buffer with the values to write + * [in] memref[1].size Size of buffer to be written + * + * Return codes: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + */ +#define TA_NVMEM_WRITE 0x1 + +/* value of TA_NVMEM type = value[in] a */ +#define NVMEM_OTP 0 + +DECLARE_GLOBAL_DATA_PTR; + +/* OPTEE TA NVMEM open helper */ +static int optee_ta_open(struct stm32prog_data *data) +{ + const struct tee_optee_ta_uuid uuid = TA_NVMEM_UUID; + struct tee_open_session_arg arg; + struct udevice *tee = NULL; + int rc; + + if (data->tee) + return 0; + + tee = tee_find_device(NULL, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + memset(&arg, 0, sizeof(arg)); + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + rc = tee_open_session(tee, &arg, 0, NULL); + if (rc < 0) + return -ENODEV; + + data->tee = tee; + data->tee_session = arg.session; + + return 0; +} + +/* OPTEE TA NVMEM invoke helper */ +static int optee_ta_invoke(struct stm32prog_data *data, int cmd, int type, + void *buff, ulong size) +{ + struct tee_invoke_arg arg; + struct tee_param param[2]; + struct tee_shm *buff_shm; + int rc; + + rc = tee_shm_register(data->tee, buff, size, 0, &buff_shm); + if (rc) + return rc; + + memset(&arg, 0, sizeof(arg)); + arg.func = cmd; + arg.session = data->tee_session; + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT; + param[0].u.value.a = type; + + if (cmd == TA_NVMEM_WRITE) + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + else + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT; + + param[1].u.memref.shm = buff_shm; + param[1].u.memref.size = size; + + rc = tee_invoke_func(data->tee, &arg, 2, param); + if (rc < 0 || arg.ret != 0) { + dev_err(data->tee, + "TA_NVMEM invoke failed TEE err: %x, err:%x\n", + arg.ret, rc); + if (!rc) + rc = -EIO; + } + + tee_shm_free(buff_shm); + + return rc; +} + +char *stm32prog_get_error(struct stm32prog_data *data) +{ + static const char error_msg[] = "Unspecified"; + + if (strlen(data->error) == 0) + strcpy(data->error, error_msg); + + return data->error; +} + +static bool stm32prog_is_fip_header(struct fip_toc_header *header) +{ + return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number; +} + +static bool stm32prog_is_stm32_header_v1(struct stm32_header_v1 *header) +{ + unsigned int i; + + if (header->magic_number != + (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { + log_debug("%s:invalid magic number : 0x%x\n", + __func__, header->magic_number); + return false; + } + if (header->header_version != 0x00010000) { + log_debug("%s:invalid header version : 0x%x\n", + __func__, header->header_version); + return false; + } + + if (header->reserved1 || header->reserved2) { + log_debug("%s:invalid reserved field\n", __func__); + return false; + } + for (i = 0; i < sizeof(header->padding); i++) { + if (header->padding[i] != 0) { + log_debug("%s:invalid padding field\n", __func__); + return false; + } + } + + return true; +} + +static bool stm32prog_is_stm32_header_v2(struct stm32_header_v2 *header) +{ + unsigned int i; + + if (header->magic_number != + (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { + log_debug("%s:invalid magic number : 0x%x\n", + __func__, header->magic_number); + return false; + } + if (header->header_version != 0x00020000) { + log_debug("%s:invalid header version : 0x%x\n", + __func__, header->header_version); + return false; + } + if (header->reserved1 || header->reserved2) + return false; + + for (i = 0; i < sizeof(header->padding); i++) { + if (header->padding[i] != 0) { + log_debug("%s:invalid padding field\n", __func__); + return false; + } + } + + return true; +} + +void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header) +{ + struct stm32_header_v1 *v1_header = (struct stm32_header_v1 *)raw_header; + struct stm32_header_v2 *v2_header = (struct stm32_header_v2 *)raw_header; + + if (!raw_header || !header) { + log_debug("%s:no header data\n", __func__); + return; + } + + if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) { + header->type = HEADER_FIP; + header->length = 0; + return; + } + if (stm32prog_is_stm32_header_v1(v1_header)) { + header->type = HEADER_STM32IMAGE; + header->image_checksum = le32_to_cpu(v1_header->image_checksum); + header->image_length = le32_to_cpu(v1_header->image_length); + header->length = sizeof(struct stm32_header_v1); + return; + } + if (stm32prog_is_stm32_header_v2(v2_header)) { + header->type = HEADER_STM32IMAGE_V2; + header->image_checksum = le32_to_cpu(v2_header->image_checksum); + header->image_length = le32_to_cpu(v2_header->image_length); + header->length = sizeof(struct stm32_header_v1) + + v2_header->extension_headers_length; + return; + } + + header->type = HEADER_NONE; + header->image_checksum = 0x0; + header->image_length = 0x0; +} + +static u32 stm32prog_header_checksum(uintptr_t addr, struct image_header_s *header) +{ + u32 i, checksum; + u8 *payload; + + /* compute checksum on payload */ + payload = (u8 *)addr; + checksum = 0; + for (i = header->image_length; i > 0; i--) + checksum += *(payload++); + + return checksum; +} + +/* FLASHLAYOUT PARSING *****************************************/ +static int parse_option(struct stm32prog_data *data, + int i, char *p, struct stm32prog_part_t *part) +{ + int result = 0; + char *c = p; + + part->option = 0; + if (!strcmp(p, "-")) + return 0; + + while (*c) { + switch (*c) { + case 'P': + part->option |= OPT_SELECT; + break; + case 'E': + part->option |= OPT_EMPTY; + break; + case 'D': + part->option |= OPT_DELETE; + break; + default: + result = -EINVAL; + stm32prog_err("Layout line %d: invalid option '%c' in %s)", + i, *c, p); + return -EINVAL; + } + c++; + } + if (!(part->option & OPT_SELECT)) { + stm32prog_err("Layout line %d: missing 'P' in option %s", i, p); + return -EINVAL; + } + + return result; +} + +static int parse_id(struct stm32prog_data *data, + int i, char *p, struct stm32prog_part_t *part) +{ + int result = 0; + unsigned long value; + + result = strict_strtoul(p, 0, &value); + part->id = value; + if (result || value > PHASE_LAST_USER) { + stm32prog_err("Layout line %d: invalid phase value = %s", i, p); + result = -EINVAL; + } + + return result; +} + +static int parse_name(struct stm32prog_data *data, + int i, char *p, struct stm32prog_part_t *part) +{ + int result = 0; + + if (strlen(p) < sizeof(part->name)) { + strcpy(part->name, p); + } else { + stm32prog_err("Layout line %d: partition name too long [%zd]: %s", + i, strlen(p), p); + result = -EINVAL; + } + + return result; +} + +static int parse_type(struct stm32prog_data *data, + int i, char *p, struct stm32prog_part_t *part) +{ + int result = 0; + int len = 0; + + part->bin_nb = 0; + if (!strncmp(p, "Binary", 6)) { + part->part_type = PART_BINARY; + + /* search for Binary(X) case */ + len = strlen(p); + part->bin_nb = 1; + if (len > 6) { + if (len < 8 || + (p[6] != '(') || + (p[len - 1] != ')')) + result = -EINVAL; + else + part->bin_nb = + dectoul(&p[7], NULL); + } + } else if (!strcmp(p, "FIP")) { + part->part_type = PART_FIP; + } else if (!strcmp(p, "FWU_MDATA")) { + part->part_type = PART_FWU_MDATA; + } else if (!strcmp(p, "ENV")) { + part->part_type = PART_ENV; + } else if (!strcmp(p, "System")) { + part->part_type = PART_SYSTEM; + } else if (!strcmp(p, "ESP")) { + part->part_type = PART_ESP; + } else if (!strcmp(p, "FileSystem")) { + part->part_type = PART_FILESYSTEM; + } else if (!strcmp(p, "RawImage")) { + part->part_type = RAW_IMAGE; + } else { + result = -EINVAL; + } + if (result) + stm32prog_err("Layout line %d: type parsing error : '%s'", + i, p); + + return result; +} + +static int parse_ip(struct stm32prog_data *data, + int i, char *p, struct stm32prog_part_t *part) +{ + int result = 0; + unsigned int len = 0; + + part->dev_id = 0; + if (!strcmp(p, "none")) { + part->target = STM32PROG_NONE; + } else if (!strncmp(p, "mmc", 3)) { + part->target = STM32PROG_MMC; + len = 3; + } else if (!strncmp(p, "nor", 3)) { + part->target = STM32PROG_NOR; + len = 3; + } else if (!strncmp(p, "nand", 4)) { + part->target = STM32PROG_NAND; + len = 4; + } else if (!strncmp(p, "spi-nand", 8)) { + part->target = STM32PROG_SPI_NAND; + len = 8; + } else if (!strncmp(p, "ram", 3)) { + part->target = STM32PROG_RAM; + len = 0; + } else { + result = -EINVAL; + } + if (len) { + /* only one digit allowed for device id */ + if (strlen(p) != len + 1) { + result = -EINVAL; + } else { + part->dev_id = p[len] - '0'; + if (part->dev_id > 9) + result = -EINVAL; + } + } + if (result) + stm32prog_err("Layout line %d: ip parsing error: '%s'", i, p); + + return result; +} + +static int parse_offset(struct stm32prog_data *data, + int i, char *p, struct stm32prog_part_t *part) +{ + int result = 0; + char *tail; + + part->part_id = 0; + part->addr = 0; + part->size = 0; + /* eMMC boot parttion */ + if (!strncmp(p, "boot", 4)) { + if (strlen(p) != 5) { + result = -EINVAL; + } else { + if (p[4] == '1') + part->part_id = -1; + else if (p[4] == '2') + part->part_id = -2; + else + result = -EINVAL; + } + if (result) + stm32prog_err("Layout line %d: invalid part '%s'", + i, p); + } else { + part->addr = simple_strtoull(p, &tail, 10); + if (tail == p || *tail != '\0') { + stm32prog_err("Layout line %d: invalid offset '%s'", + i, p); + result = -EINVAL; + } + } + + return result; +} + +static +int (* const parse[COL_NB_STM32])(struct stm32prog_data *data, int i, char *p, + struct stm32prog_part_t *part) = { + [COL_OPTION] = parse_option, + [COL_ID] = parse_id, + [COL_NAME] = parse_name, + [COL_TYPE] = parse_type, + [COL_IP] = parse_ip, + [COL_OFFSET] = parse_offset, +}; + +static int parse_flash_layout(struct stm32prog_data *data, + uintptr_t addr, + ulong size) +{ + int column = 0, part_nb = 0, ret; + bool end_of_line, eof; + char *p, *start, *last, *col; + struct stm32prog_part_t *part; + struct image_header_s header; + int part_list_size; + int i; + + data->part_nb = 0; + + /* check if STM32image is detected */ + stm32prog_header_check(addr, &header); + if (header.type == HEADER_STM32IMAGE) { + u32 checksum; + + addr = addr + header.length; + size = header.image_length; + + checksum = stm32prog_header_checksum(addr, &header); + if (checksum != header.image_checksum) { + stm32prog_err("Layout: invalid checksum : 0x%x expected 0x%x", + checksum, header.image_checksum); + return -EIO; + } + } + if (!size) + return -EINVAL; + + start = (char *)addr; + last = start + size; + + *last = 0x0; /* force null terminated string */ + log_debug("flash layout =\n%s\n", start); + + /* calculate expected number of partitions */ + part_list_size = 1; + p = start; + while (*p && (p < last)) { + if (*p++ == '\n') { + part_list_size++; + if (p < last && *p == '#') + part_list_size--; + } + } + if (part_list_size > PHASE_LAST_USER) { + stm32prog_err("Layout: too many partition (%d)", + part_list_size); + return -1; + } + part = calloc(sizeof(struct stm32prog_part_t), part_list_size); + if (!part) { + stm32prog_err("Layout: alloc failed"); + return -ENOMEM; + } + data->part_array = part; + + /* main parsing loop */ + i = 1; + eof = false; + p = start; + col = start; /* 1st column */ + end_of_line = false; + while (!eof) { + switch (*p) { + /* CR is ignored and replaced by NULL character */ + case '\r': + *p = '\0'; + p++; + continue; + case '\0': + end_of_line = true; + eof = true; + break; + case '\n': + end_of_line = true; + break; + case '\t': + break; + case '#': + /* comment line is skipped */ + if (column == 0 && p == col) { + while ((p < last) && *p) + if (*p++ == '\n') + break; + col = p; + i++; + if (p >= last || !*p) { + eof = true; + end_of_line = true; + } + continue; + } + /* fall through */ + /* by default continue with the next character */ + default: + p++; + continue; + } + + /* replace by \0: allow string parsing for each column */ + *p = '\0'; + p++; + if (p >= last) { + eof = true; + end_of_line = true; + } + + /* skip empty line and multiple TAB in tsv file */ + if (strlen(col) == 0) { + col = p; + /* skip empty line */ + if (column == 0 && end_of_line) { + end_of_line = false; + i++; + } + continue; + } + + if (column < COL_NB_STM32) { + ret = parse[column](data, i, col, part); + if (ret) + return ret; + } + + /* save the beginning of the next column */ + column++; + col = p; + + if (!end_of_line) + continue; + + /* end of the line detected */ + end_of_line = false; + + if (column < COL_NB_STM32) { + stm32prog_err("Layout line %d: no enought column", i); + return -EINVAL; + } + column = 0; + part_nb++; + part++; + i++; + if (part_nb >= part_list_size) { + part = NULL; + if (!eof) { + stm32prog_err("Layout: no enought memory for %d part", + part_nb); + return -EINVAL; + } + } + } + data->part_nb = part_nb; + if (data->part_nb == 0) { + stm32prog_err("Layout: no partition found"); + return -ENODEV; + } + + return 0; +} + +static int __init part_cmp(void *priv, struct list_head *a, struct list_head *b) +{ + struct stm32prog_part_t *parta, *partb; + + parta = container_of(a, struct stm32prog_part_t, list); + partb = container_of(b, struct stm32prog_part_t, list); + + if (parta->part_id != partb->part_id) + return parta->part_id - partb->part_id; + else + return parta->addr > partb->addr ? 1 : -1; +} + +static void get_mtd_by_target(char *string, enum stm32prog_target target, + int dev_id) +{ + const char *dev_str; + + switch (target) { + case STM32PROG_NOR: + dev_str = "nor"; + break; + case STM32PROG_NAND: + dev_str = "nand"; + break; + case STM32PROG_SPI_NAND: + dev_str = "spi-nand"; + break; + default: + dev_str = "invalid"; + break; + } + sprintf(string, "%s%d", dev_str, dev_id); +} + +static int init_device(struct stm32prog_data *data, + struct stm32prog_dev_t *dev) +{ + struct mmc *mmc = NULL; + struct blk_desc *block_dev = NULL; + struct mtd_info *mtd = NULL; + struct mtd_info *partition; + char mtd_id[16]; + int part_id; + int ret; + u64 first_addr = 0, last_addr = 0; + struct stm32prog_part_t *part, *next_part; + u64 part_addr, part_size; + bool part_found; + const char *part_name; + u8 i; + + switch (dev->target) { + case STM32PROG_MMC: + if (!IS_ENABLED(CONFIG_MMC)) { + stm32prog_err("unknown device type = %d", dev->target); + return -ENODEV; + } + mmc = find_mmc_device(dev->dev_id); + if (!mmc || mmc_init(mmc)) { + stm32prog_err("mmc device %d not found", dev->dev_id); + return -ENODEV; + } + block_dev = mmc_get_blk_desc(mmc); + if (!block_dev) { + stm32prog_err("mmc device %d not probed", dev->dev_id); + return -ENODEV; + } + dev->erase_size = mmc->erase_grp_size * block_dev->blksz; + dev->mmc = mmc; + + /* reserve a full erase group for each GTP headers */ + if (mmc->erase_grp_size > GPT_HEADER_SZ) { + first_addr = dev->erase_size; + last_addr = (u64)(block_dev->lba - + mmc->erase_grp_size) * + block_dev->blksz; + } else { + first_addr = (u64)GPT_HEADER_SZ * block_dev->blksz; + last_addr = (u64)(block_dev->lba - GPT_HEADER_SZ - 1) * + block_dev->blksz; + } + log_debug("MMC %d: lba=%lld blksz=%ld\n", dev->dev_id, + (u64)block_dev->lba, block_dev->blksz); + log_debug(" available address = 0x%llx..0x%llx\n", + first_addr, last_addr); + log_debug(" full_update = %d\n", dev->full_update); + break; + case STM32PROG_NOR: + case STM32PROG_NAND: + case STM32PROG_SPI_NAND: + if (!IS_ENABLED(CONFIG_MTD)) { + stm32prog_err("unknown device type = %d", dev->target); + return -ENODEV; + } + /* register partitions with MTDIDS/MTDPARTS or OF fallback */ + mtd_probe_devices(); + get_mtd_by_target(mtd_id, dev->target, dev->dev_id); + log_debug("%s\n", mtd_id); + + mtd = get_mtd_device_nm(mtd_id); + if (IS_ERR(mtd)) { + stm32prog_err("MTD device %s not found", mtd_id); + return -ENODEV; + } + first_addr = 0; + last_addr = mtd->size; + dev->erase_size = mtd->erasesize; + log_debug("MTD device %s: size=%lld erasesize=%d\n", + mtd_id, mtd->size, mtd->erasesize); + log_debug(" available address = 0x%llx..0x%llx\n", + first_addr, last_addr); + dev->mtd = mtd; + break; + case STM32PROG_RAM: + first_addr = gd->bd->bi_dram[0].start; + last_addr = first_addr + gd->bd->bi_dram[0].size; + dev->erase_size = 1; + break; + default: + stm32prog_err("unknown device type = %d", dev->target); + return -ENODEV; + } + log_debug(" erase size = 0x%x\n", dev->erase_size); + log_debug(" full_update = %d\n", dev->full_update); + + /* order partition list in offset order */ + list_sort(NULL, &dev->part_list, &part_cmp); + part_id = 1; + log_debug("id : Opt Phase Name target.n dev.n addr size part_off part_size\n"); + list_for_each_entry(part, &dev->part_list, list) { + if (part->bin_nb > 1) { + if ((dev->target != STM32PROG_NAND && + dev->target != STM32PROG_SPI_NAND) || + part->id >= PHASE_FIRST_USER || + strncmp(part->name, "fsbl", 4)) { + stm32prog_err("%s (0x%x): multiple binary %d not supported", + part->name, part->id, + part->bin_nb); + return -EINVAL; + } + } + if (part->part_type == RAW_IMAGE) { + part->part_id = 0x0; + part->addr = 0x0; + if (block_dev) + part->size = block_dev->lba * block_dev->blksz; + else + part->size = last_addr; + log_debug("-- : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx\n", + part->option, part->id, part->name, + part->part_type, part->bin_nb, part->target, + part->dev_id, part->addr, part->size); + continue; + } + if (part->part_id < 0) { /* boot hw partition for eMMC */ + if (mmc) { + part->size = mmc->capacity_boot; + } else { + stm32prog_err("%s (0x%x): hw partition not expected : %d", + part->name, part->id, + part->part_id); + return -ENODEV; + } + } else { + part->part_id = part_id++; + + /* last partition : size to the end of the device */ + if (part->list.next != &dev->part_list) { + next_part = + container_of(part->list.next, + struct stm32prog_part_t, + list); + if (part->addr < next_part->addr) { + part->size = next_part->addr - + part->addr; + } else { + stm32prog_err("%s (0x%x): same address : 0x%llx == %s (0x%x): 0x%llx", + part->name, part->id, + part->addr, + next_part->name, + next_part->id, + next_part->addr); + return -EINVAL; + } + } else { + if (part->addr <= last_addr) { + part->size = last_addr - part->addr; + } else { + stm32prog_err("%s (0x%x): invalid address 0x%llx (max=0x%llx)", + part->name, part->id, + part->addr, last_addr); + return -EINVAL; + } + } + if (part->addr < first_addr) { + stm32prog_err("%s (0x%x): invalid address 0x%llx (min=0x%llx)", + part->name, part->id, + part->addr, first_addr); + return -EINVAL; + } + } + if ((part->addr & ((u64)part->dev->erase_size - 1)) != 0) { + stm32prog_err("%s (0x%x): not aligned address : 0x%llx on erase size 0x%x", + part->name, part->id, part->addr, + part->dev->erase_size); + return -EINVAL; + } + log_debug("%02d : %1d %02x %14s %02d.%d %02d.%02d %08llx %08llx", + part->part_id, part->option, part->id, part->name, + part->part_type, part->bin_nb, part->target, + part->dev_id, part->addr, part->size); + + part_addr = 0; + part_size = 0; + part_found = false; + + /* check coherency with existing partition */ + if (block_dev) { + /* + * block devices with GPT: check user partition size + * only for partial update, the GPT partions are be + * created for full update + */ + if (dev->full_update || part->part_id < 0) { + log_debug("\n"); + continue; + } + struct disk_partition partinfo; + + ret = part_get_info(block_dev, part->part_id, + &partinfo); + + if (ret) { + stm32prog_err("%s (0x%x):Couldn't find part %d on device mmc %d", + part->name, part->id, + part_id, part->dev_id); + return -ENODEV; + } + part_addr = (u64)partinfo.start * partinfo.blksz; + part_size = (u64)partinfo.size * partinfo.blksz; + part_name = (char *)partinfo.name; + part_found = true; + } + + if (IS_ENABLED(CONFIG_MTD) && mtd) { + i = 0; + list_for_each_entry(partition, &mtd->partitions, node) { + if ((part->part_id - 1) == i) { + part_found = true; + break; + } + i++; + } + if (part_found) { + part_addr = partition->offset; + part_size = partition->size; + part_name = partition->name; + } else { + stm32prog_err("%s (0x%x):Couldn't find part %d on device mtd %s", + part->name, part->id, part->part_id, mtd_id); + return -ENODEV; + } + } + + /* no partition for this device */ + if (!part_found) { + log_debug("\n"); + continue; + } + + log_debug(" %08llx %08llx\n", part_addr, part_size); + + if (part->addr != part_addr) { + stm32prog_err("%s (0x%x): Bad address for partition %d (%s) = 0x%llx <> 0x%llx expected", + part->name, part->id, part->part_id, + part_name, part->addr, part_addr); + return -ENODEV; + } + if (part->size != part_size) { + stm32prog_err("%s (0x%x): Bad size for partition %d (%s) at 0x%llx = 0x%llx <> 0x%llx expected", + part->name, part->id, part->part_id, + part_name, part->addr, part->size, + part_size); + return -ENODEV; + } + } + return 0; +} + +static int treat_partition_list(struct stm32prog_data *data) +{ + int i, j; + struct stm32prog_part_t *part; + + for (j = 0; j < STM32PROG_MAX_DEV; j++) { + data->dev[j].target = STM32PROG_NONE; + INIT_LIST_HEAD(&data->dev[j].part_list); + } + + data->fsbl_nor_detected = false; + for (i = 0; i < data->part_nb; i++) { + part = &data->part_array[i]; + part->alt_id = -1; + + /* skip partition with IP="none" */ + if (part->target == STM32PROG_NONE) { + if (IS_SELECT(part)) { + stm32prog_err("Layout: selected none phase = 0x%x for part %s", + part->id, part->name); + return -EINVAL; + } + continue; + } + + if (part->id == PHASE_FLASHLAYOUT || + part->id > PHASE_LAST_USER) { + stm32prog_err("Layout: invalid phase = 0x%x for part %s", + part->id, part->name); + return -EINVAL; + } + for (j = i + 1; j < data->part_nb; j++) { + if (part->id == data->part_array[j].id) { + stm32prog_err("Layout: duplicated phase 0x%x for part %s and %s", + part->id, part->name, data->part_array[j].name); + return -EINVAL; + } + } + for (j = 0; j < STM32PROG_MAX_DEV; j++) { + if (data->dev[j].target == STM32PROG_NONE) { + /* new device found */ + data->dev[j].target = part->target; + data->dev[j].dev_id = part->dev_id; + data->dev[j].full_update = true; + data->dev_nb++; + break; + } else if ((part->target == data->dev[j].target) && + (part->dev_id == data->dev[j].dev_id)) { + break; + } + } + if (j == STM32PROG_MAX_DEV) { + stm32prog_err("Layout: too many device"); + return -EINVAL; + } + switch (part->target) { + case STM32PROG_NOR: + if (!data->fsbl_nor_detected && + !strncmp(part->name, "fsbl", 4)) + data->fsbl_nor_detected = true; + /* fallthrough */ + default: + break; + } + part->dev = &data->dev[j]; + if (!IS_SELECT(part)) + part->dev->full_update = false; + list_add_tail(&part->list, &data->dev[j].part_list); + } + + return 0; +} + +static int create_gpt_partitions(struct stm32prog_data *data) +{ + int offset = 0; + const int buflen = SZ_8K; + char *buf; + char uuid[UUID_STR_LEN + 1]; + unsigned char *uuid_bin; + unsigned int mmc_id; + int i, j; + bool rootfs_found; + struct stm32prog_part_t *part; + const char *type_str; + + buf = malloc(buflen); + if (!buf) + return -ENOMEM; + + /* initialize the selected device */ + for (i = 0; i < data->dev_nb; i++) { + /* create gpt partition support only for full update on MMC */ + if (data->dev[i].target != STM32PROG_MMC || + !data->dev[i].full_update) + continue; + + printf("partitions on mmc%d: ", data->dev[i].dev_id); + offset = 0; + rootfs_found = false; + memset(buf, 0, buflen); + + list_for_each_entry(part, &data->dev[i].part_list, list) { + /* skip eMMC boot partitions */ + if (part->part_id < 0) + continue; + /* skip Raw Image */ + if (part->part_type == RAW_IMAGE) + continue; + + if (offset + 100 > buflen) { + log_debug("\n%s: buffer too small, %s skippped", + __func__, part->name); + continue; + } + + if (!offset) + offset += sprintf(buf, "gpt write mmc %d \"", + data->dev[i].dev_id); + + offset += snprintf(buf + offset, buflen - offset, + "name=%s,start=0x%llx,size=0x%llx", + part->name, + part->addr, + part->size); + + switch (part->part_type) { + case PART_BINARY: + type_str = LINUX_RESERVED_UUID; + break; + case PART_ENV: + type_str = "u-boot-env"; + break; + case PART_FIP: + type_str = FIP_TYPE_UUID; + break; + case PART_FWU_MDATA: + type_str = FWU_MDATA_UUID; + break; + case PART_ESP: + /* EFI System Partition */ + type_str = "system"; + break; + default: /* PART_FILESYSTEM or PART_SYSTEM for distro */ + type_str = "linux"; + break; + } + offset += snprintf(buf + offset, + buflen - offset, + ",type=%s", type_str); + + if (part->part_type == PART_SYSTEM) + offset += snprintf(buf + offset, + buflen - offset, + ",bootable"); + + /* partition UUID */ + uuid_bin = NULL; + if (!rootfs_found && !strcmp(part->name, "rootfs")) { + mmc_id = part->dev_id; + rootfs_found = true; + if (mmc_id < ARRAY_SIZE(uuid_mmc)) + uuid_bin = (unsigned char *)uuid_mmc[mmc_id].b; + } + if (part->part_type == PART_FIP) { + for (j = 0; j < ARRAY_SIZE(fip_part_name); j++) + if (!strcmp(part->name, fip_part_name[j])) { + uuid_bin = (unsigned char *)fip_part_uuid[j].b; + break; + } + } + if (uuid_bin) { + uuid_bin_to_str(uuid_bin, uuid, UUID_STR_FORMAT_GUID); + offset += snprintf(buf + offset, + buflen - offset, + ",uuid=%s", uuid); + } + + offset += snprintf(buf + offset, buflen - offset, ";"); + } + + if (offset) { + offset += snprintf(buf + offset, buflen - offset, "\""); + log_debug("\ncmd: %s\n", buf); + if (run_command(buf, 0)) { + stm32prog_err("GPT partitionning fail: %s", + buf); + free(buf); + + return -1; + } + } + + if (data->dev[i].mmc) + part_init(mmc_get_blk_desc(data->dev[i].mmc)); + +#ifdef DEBUG + sprintf(buf, "gpt verify mmc %d", data->dev[i].dev_id); + log_debug("\ncmd: %s", buf); + if (run_command(buf, 0)) + printf("fail !\n"); + else + printf("OK\n"); + + sprintf(buf, "part list mmc %d", data->dev[i].dev_id); + run_command(buf, 0); +#endif + puts("done\n"); + } + +#ifdef DEBUG + run_command("mtd list", 0); +#endif + free(buf); + + return 0; +} + +static int stm32prog_alt_add(struct stm32prog_data *data, + struct dfu_entity *dfu, + struct stm32prog_part_t *part) +{ + int ret = 0; + int offset = 0; + char devstr[10]; + char dfustr[10]; + char buf[ALT_BUF_LEN]; + u32 size; + char multiplier, type; + + /* max 3 digit for sector size */ + if (part->size > SZ_1G) { + size = (u32)(part->size / SZ_1G); + multiplier = 'G'; + } else if (part->size > SZ_1M) { + size = (u32)(part->size / SZ_1M); + multiplier = 'M'; + } else if (part->size > SZ_1K) { + size = (u32)(part->size / SZ_1K); + multiplier = 'K'; + } else { + size = (u32)part->size; + multiplier = 'B'; + } + if (IS_SELECT(part) && !IS_EMPTY(part)) + type = 'e'; /*Readable and Writeable*/ + else + type = 'a';/*Readable*/ + + memset(buf, 0, sizeof(buf)); + offset = snprintf(buf, ALT_BUF_LEN - offset, + "@%s/0x%02x/1*%d%c%c ", + part->name, part->id, + size, multiplier, type); + + if (part->target == STM32PROG_RAM) { + offset += snprintf(buf + offset, ALT_BUF_LEN - offset, + "ram 0x%llx 0x%llx", + part->addr, part->size); + } else if (part->part_type == RAW_IMAGE) { + u64 dfu_size; + + if (part->dev->target == STM32PROG_MMC) + dfu_size = part->size / part->dev->mmc->read_bl_len; + else + dfu_size = part->size; + offset += snprintf(buf + offset, ALT_BUF_LEN - offset, + "raw 0x0 0x%llx", dfu_size); + } else if (part->part_id < 0) { + u64 nb_blk = part->size / part->dev->mmc->read_bl_len; + + offset += snprintf(buf + offset, ALT_BUF_LEN - offset, + "raw 0x%llx 0x%llx", + part->addr, nb_blk); + offset += snprintf(buf + offset, ALT_BUF_LEN - offset, + " mmcpart %d", -(part->part_id)); + } else { + if (part->part_type == PART_SYSTEM && + (part->target == STM32PROG_NAND || + part->target == STM32PROG_NOR || + part->target == STM32PROG_SPI_NAND)) + offset += snprintf(buf + offset, + ALT_BUF_LEN - offset, + "partubi"); + else + offset += snprintf(buf + offset, + ALT_BUF_LEN - offset, + "part"); + /* dev_id requested by DFU MMC */ + if (part->target == STM32PROG_MMC) + offset += snprintf(buf + offset, ALT_BUF_LEN - offset, + " %d", part->dev_id); + offset += snprintf(buf + offset, ALT_BUF_LEN - offset, + " %d", part->part_id); + } + ret = -ENODEV; + switch (part->target) { + case STM32PROG_MMC: + if (IS_ENABLED(CONFIG_MMC)) { + ret = 0; + sprintf(dfustr, "mmc"); + sprintf(devstr, "%d", part->dev_id); + } + break; + case STM32PROG_NAND: + case STM32PROG_NOR: + case STM32PROG_SPI_NAND: + if (IS_ENABLED(CONFIG_MTD)) { + ret = 0; + sprintf(dfustr, "mtd"); + get_mtd_by_target(devstr, part->target, part->dev_id); + } + break; + case STM32PROG_RAM: + ret = 0; + sprintf(dfustr, "ram"); + sprintf(devstr, "0"); + break; + default: + break; + } + if (ret) { + stm32prog_err("invalid target: %d", part->target); + return ret; + } + log_debug("dfu_alt_add(%s,%s,%s)\n", dfustr, devstr, buf); + ret = dfu_alt_add(dfu, dfustr, devstr, buf); + log_debug("dfu_alt_add(%s,%s,%s) result %d\n", + dfustr, devstr, buf, ret); + + return ret; +} + +static int stm32prog_alt_add_virt(struct dfu_entity *dfu, + char *name, int phase, int size) +{ + int ret = 0; + char devstr[4]; + char buf[ALT_BUF_LEN]; + + sprintf(devstr, "%d", phase); + sprintf(buf, "@%s/0x%02x/1*%dBe", name, phase, size); + ret = dfu_alt_add(dfu, "virt", devstr, buf); + log_debug("dfu_alt_add(virt,%s,%s) result %d\n", devstr, buf, ret); + + return ret; +} + +static int dfu_init_entities(struct stm32prog_data *data) +{ + int ret = 0; + int phase, i, alt_id; + struct stm32prog_part_t *part; + struct dfu_entity *dfu; + int alt_nb; + u32 otp_size = 0; + + alt_nb = 1; /* number of virtual = CMD*/ + + if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { + /* OTP_SIZE_SMC = 0 if SMC is not supported */ + otp_size = OTP_SIZE_SMC; + /* check if PTA BSEC is supported */ + ret = optee_ta_open(data); + log_debug("optee_ta_open(PTA_NVMEM) result %d\n", ret); + if (!ret && data->tee) + otp_size = OTP_SIZE_TA; + if (otp_size) + alt_nb++; /* OTP*/ + } + + if (CONFIG_IS_ENABLED(DM_PMIC)) + alt_nb++; /* PMIC NVMEM*/ + + if (data->part_nb == 0) + alt_nb++; /* +1 for FlashLayout */ + else + for (i = 0; i < data->part_nb; i++) { + if (data->part_array[i].target != STM32PROG_NONE) + alt_nb++; + } + + if (dfu_alt_init(alt_nb, &dfu)) + return -ENODEV; + + puts("DFU alt info setting: "); + if (data->part_nb) { + alt_id = 0; + ret = 0; + for (phase = 1; + (phase <= PHASE_LAST_USER) && + (alt_id < alt_nb) && !ret; + phase++) { + /* ordering alt setting by phase id */ + part = NULL; + for (i = 0; i < data->part_nb; i++) { + if (phase == data->part_array[i].id) { + part = &data->part_array[i]; + break; + } + } + if (!part) + continue; + if (part->target == STM32PROG_NONE) + continue; + part->alt_id = alt_id; + alt_id++; + + ret = stm32prog_alt_add(data, dfu, part); + } + } else { + char buf[ALT_BUF_LEN]; + + sprintf(buf, "@FlashLayout/0x%02x/1*256Ke ram %x 40000", + PHASE_FLASHLAYOUT, CONFIG_SYS_LOAD_ADDR); + ret = dfu_alt_add(dfu, "ram", NULL, buf); + log_debug("dfu_alt_add(ram, NULL,%s) result %d\n", buf, ret); + } + + if (!ret) + ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE); + + if (!ret && IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && otp_size) + ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, otp_size); + + if (!ret && CONFIG_IS_ENABLED(DM_PMIC)) + ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE); + + if (ret) + stm32prog_err("dfu init failed: %d", ret); + puts("done\n"); + +#ifdef DEBUG + dfu_show_entities(); +#endif + return ret; +} + +int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, + long *size) +{ + u32 otp_size = data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC; + log_debug("%s: %x %lx\n", __func__, offset, *size); + + if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { + stm32prog_err("OTP update not supported"); + + return -EOPNOTSUPP; + } + + if (!data->otp_part) { + data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size); + if (!data->otp_part) { + stm32prog_err("OTP write issue %d", -ENOMEM); + + return -ENOMEM; + } + } + + if (!offset) + memset(data->otp_part, 0, otp_size); + + if (offset + *size > otp_size) + *size = otp_size - offset; + + memcpy((void *)((uintptr_t)data->otp_part + offset), buffer, *size); + + return 0; +} + +int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, + long *size) +{ + u32 otp_size = data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC; + int result = 0; + + if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { + stm32prog_err("OTP update not supported"); + + return -EOPNOTSUPP; + } + + log_debug("%s: %x %lx\n", __func__, offset, *size); + /* alway read for first packet */ + if (!offset) { + if (!data->otp_part) + data->otp_part = + memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size); + + if (!data->otp_part) { + result = -ENOMEM; + goto end_otp_read; + } + + /* init struct with 0 */ + memset(data->otp_part, 0, otp_size); + + /* call the service */ + result = -EOPNOTSUPP; + if (data->tee && CONFIG_IS_ENABLED(OPTEE)) + result = optee_ta_invoke(data, TA_NVMEM_READ, NVMEM_OTP, + data->otp_part, OTP_SIZE_TA); + else if (IS_ENABLED(CONFIG_ARM_SMCCC)) + result = stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_READ_ALL, + (unsigned long)data->otp_part, 0); + if (result) + goto end_otp_read; + } + + if (!data->otp_part) { + result = -ENOMEM; + goto end_otp_read; + } + + if (offset + *size > otp_size) + *size = otp_size - offset; + memcpy(buffer, (void *)((uintptr_t)data->otp_part + offset), *size); + +end_otp_read: + if (result) + stm32prog_err("OTP read issue %d", result); + log_debug("%s: result %i\n", __func__, result); + + return result; +} + +int stm32prog_otp_start(struct stm32prog_data *data) +{ + int result = 0; + struct arm_smccc_res res; + + if (!IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) { + stm32prog_err("OTP update not supported"); + + return -EOPNOTSUPP; + } + + if (!data->otp_part) { + stm32prog_err("start OTP without data"); + return -1; + } + + result = -EOPNOTSUPP; + if (data->tee && CONFIG_IS_ENABLED(OPTEE)) { + result = optee_ta_invoke(data, TA_NVMEM_WRITE, NVMEM_OTP, + data->otp_part, OTP_SIZE_TA); + } else if (IS_ENABLED(CONFIG_ARM_SMCCC)) { + arm_smccc_smc(STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, + (uintptr_t)data->otp_part, 0, 0, 0, 0, 0, &res); + + if (!res.a0) { + switch (res.a1) { + case 0: + result = 0; + break; + case 1: + stm32prog_err("Provisioning"); + result = 0; + break; + default: + log_err("%s: OTP incorrect value (err = %ld)\n", + __func__, res.a1); + result = -EINVAL; + break; + } + } else { + log_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n", + __func__, STM32_SMC_BSEC, STM32_SMC_WRITE_ALL, res.a0); + result = -EINVAL; + } + } + + free(data->otp_part); + data->otp_part = NULL; + if (result) + stm32prog_err("OTP write issue %d", result); + log_debug("%s: result %i\n", __func__, result); + + return result; +} + +int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, u8 *buffer, + long *size) +{ + log_debug("%s: %x %lx\n", __func__, offset, *size); + + if (!offset) + memset(data->pmic_part, 0, PMIC_SIZE); + + if (offset + *size > PMIC_SIZE) + *size = PMIC_SIZE - offset; + + memcpy(&data->pmic_part[offset], buffer, *size); + + return 0; +} + +int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer, + long *size) +{ + int result = 0, ret; + struct udevice *dev; + + if (!IS_ENABLED(CONFIG_PMIC_STPMIC1)) { + stm32prog_err("PMIC update not supported"); + + return -EOPNOTSUPP; + } + + log_debug("%s: %x %lx\n", __func__, offset, *size); + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stpmic1_nvm), + &dev); + if (ret) + return ret; + + /* alway request PMIC for first packet */ + if (!offset) { + /* init struct with 0 */ + memset(data->pmic_part, 0, PMIC_SIZE); + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stpmic1_nvm), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, 0xF8, data->pmic_part, PMIC_SIZE); + if (ret < 0) { + result = ret; + goto end_pmic_read; + } + if (ret != PMIC_SIZE) { + result = -EACCES; + goto end_pmic_read; + } + } + + if (offset + *size > PMIC_SIZE) + *size = PMIC_SIZE - offset; + + memcpy(buffer, &data->pmic_part[offset], *size); + +end_pmic_read: + log_debug("%s: result %i\n", __func__, result); + return result; +} + +int stm32prog_pmic_start(struct stm32prog_data *data) +{ + int ret; + struct udevice *dev; + + if (!IS_ENABLED(CONFIG_PMIC_STPMIC1)) { + stm32prog_err("PMIC update not supported"); + + return -EOPNOTSUPP; + } + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stpmic1_nvm), + &dev); + if (ret) + return ret; + + return misc_write(dev, 0xF8, data->pmic_part, PMIC_SIZE); +} + +/* copy FSBL on NAND to improve reliability on NAND */ +static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) +{ + int ret, i; + void *fsbl; + struct image_header_s header; + struct stm32_header_v2 raw_header; /* V2 size > v1 size */ + struct dfu_entity *dfu; + long size, offset; + + if (part->target != STM32PROG_NAND && + part->target != STM32PROG_SPI_NAND) + return -EINVAL; + + dfu = dfu_get_entity(part->alt_id); + + /* read header */ + dfu_transaction_cleanup(dfu); + size = sizeof(raw_header); + ret = dfu->read_medium(dfu, 0, (void *)&raw_header, &size); + if (ret) + return ret; + + stm32prog_header_check((ulong)&raw_header, &header); + if (header.type != HEADER_STM32IMAGE && + header.type != HEADER_STM32IMAGE_V2) + return -ENOENT; + + /* read header + payload */ + size = header.image_length + header.length; + size = round_up(size, part->dev->mtd->erasesize); + fsbl = calloc(1, size); + if (!fsbl) + return -ENOMEM; + ret = dfu->read_medium(dfu, 0, fsbl, &size); + log_debug("%s read size=%lx ret=%d\n", __func__, size, ret); + if (ret) + goto error; + + dfu_transaction_cleanup(dfu); + offset = 0; + for (i = part->bin_nb - 1; i > 0; i--) { + offset += size; + /* write to the next erase block */ + ret = dfu->write_medium(dfu, offset, fsbl, &size); + log_debug("%s copy at ofset=%lx size=%lx ret=%d", + __func__, offset, size, ret); + if (ret) + goto error; + } + +error: + free(fsbl); + return ret; +} + +static void stm32prog_end_phase(struct stm32prog_data *data, u64 offset) +{ + if (data->phase == PHASE_FLASHLAYOUT) { +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) + if (genimg_get_format((void *)CONFIG_SYS_LOAD_ADDR) == IMAGE_FORMAT_LEGACY) { + data->script = CONFIG_SYS_LOAD_ADDR; + data->phase = PHASE_END; + log_notice("U-Boot script received\n"); + return; + } +#endif + log_notice("\nFlashLayout received, size = %lld\n", offset); + if (parse_flash_layout(data, CONFIG_SYS_LOAD_ADDR, offset)) + stm32prog_err("Layout: invalid FlashLayout"); + return; + } + + if (!data->cur_part) + return; + + if (data->cur_part->target == STM32PROG_RAM) { + if (data->cur_part->part_type == PART_SYSTEM) + data->uimage = data->cur_part->addr; + if (data->cur_part->part_type == PART_FILESYSTEM) + data->dtb = data->cur_part->addr; + if (data->cur_part->part_type == PART_BINARY) { + data->initrd = data->cur_part->addr; + data->initrd_size = offset; + } + } + + if (CONFIG_IS_ENABLED(MMC) && + data->cur_part->part_id < 0) { + char cmdbuf[60]; + + sprintf(cmdbuf, "mmc bootbus %d 0 0 0; mmc partconf %d 1 %d 0", + data->cur_part->dev_id, data->cur_part->dev_id, + -(data->cur_part->part_id)); + if (run_command(cmdbuf, 0)) { + stm32prog_err("commands '%s' failed", cmdbuf); + return; + } + } + + if (IS_ENABLED(CONFIG_MTD) && + data->cur_part->bin_nb > 1) { + if (stm32prog_copy_fsbl(data->cur_part)) { + stm32prog_err("%s (0x%x): copy of fsbl failed", + data->cur_part->name, data->cur_part->id); + return; + } + } +} + +void stm32prog_do_reset(struct stm32prog_data *data) +{ + if (data->phase == PHASE_RESET) { + data->phase = PHASE_DO_RESET; + puts("Reset requested\n"); + } +} + +void stm32prog_next_phase(struct stm32prog_data *data) +{ + int phase, i; + struct stm32prog_part_t *part; + bool found; + + phase = data->phase; + switch (phase) { + case PHASE_RESET: + case PHASE_END: + case PHASE_DO_RESET: + return; + } + + /* found next selected partition */ + data->dfu_seq = 0; + data->cur_part = NULL; + data->phase = PHASE_END; + found = false; + do { + phase++; + if (phase > PHASE_LAST_USER) + break; + for (i = 0; i < data->part_nb; i++) { + part = &data->part_array[i]; + if (part->id == phase) { + if (IS_SELECT(part) && !IS_EMPTY(part)) { + data->cur_part = part; + data->phase = phase; + found = true; + } + break; + } + } + } while (!found); + + if (data->phase == PHASE_END) + puts("Phase=END\n"); +} + +static int part_delete(struct stm32prog_data *data, + struct stm32prog_part_t *part) +{ + int ret = 0; + unsigned long blks, blks_offset, blks_size; + struct blk_desc *block_dev = NULL; + char cmdbuf[40]; + char devstr[10]; + + printf("Erasing %s ", part->name); + switch (part->target) { + case STM32PROG_MMC: + if (!IS_ENABLED(CONFIG_MMC)) { + ret = -1; + stm32prog_err("%s (0x%x): erase invalid", + part->name, part->id); + break; + } + printf("on mmc %d: ", part->dev->dev_id); + block_dev = mmc_get_blk_desc(part->dev->mmc); + blks_offset = lldiv(part->addr, part->dev->mmc->read_bl_len); + blks_size = lldiv(part->size, part->dev->mmc->read_bl_len); + /* -1 or -2 : delete boot partition of MMC + * need to switch to associated hwpart 1 or 2 + */ + if (part->part_id < 0) + if (blk_select_hwpart_devnum(UCLASS_MMC, + part->dev->dev_id, + -part->part_id)) + return -1; + + blks = blk_derase(block_dev, blks_offset, blks_size); + + /* return to user partition */ + if (part->part_id < 0) + blk_select_hwpart_devnum(UCLASS_MMC, + part->dev->dev_id, 0); + if (blks != blks_size) { + ret = -1; + stm32prog_err("%s (0x%x): MMC erase failed", + part->name, part->id); + } + break; + case STM32PROG_NOR: + case STM32PROG_NAND: + case STM32PROG_SPI_NAND: + if (!IS_ENABLED(CONFIG_MTD)) { + ret = -1; + stm32prog_err("%s (0x%x): erase invalid", + part->name, part->id); + break; + } + get_mtd_by_target(devstr, part->target, part->dev->dev_id); + printf("on %s: ", devstr); + sprintf(cmdbuf, "mtd erase %s 0x%llx 0x%llx", + devstr, part->addr, part->size); + if (run_command(cmdbuf, 0)) { + ret = -1; + stm32prog_err("%s (0x%x): MTD erase commands failed (%s)", + part->name, part->id, cmdbuf); + } + break; + case STM32PROG_RAM: + printf("on ram: "); + memset((void *)(uintptr_t)part->addr, 0, (size_t)part->size); + break; + default: + ret = -1; + stm32prog_err("%s (0x%x): erase invalid", part->name, part->id); + break; + } + if (!ret) + printf("done\n"); + + return ret; +} + +static void stm32prog_devices_init(struct stm32prog_data *data) +{ + int i; + int ret; + struct stm32prog_part_t *part; + + ret = treat_partition_list(data); + if (ret) + goto error; + + /* empty flashlayout */ + if (!data->dev_nb) + return; + + /* initialize the selected device */ + for (i = 0; i < data->dev_nb; i++) { + ret = init_device(data, &data->dev[i]); + if (ret) + goto error; + } + + /* delete RAW partition before create partition */ + for (i = 0; i < data->part_nb; i++) { + part = &data->part_array[i]; + + if (part->part_type != RAW_IMAGE) + continue; + + if (!IS_SELECT(part) || !IS_DELETE(part)) + continue; + + ret = part_delete(data, part); + if (ret) + goto error; + } + + if (IS_ENABLED(CONFIG_MMC)) { + ret = create_gpt_partitions(data); + if (ret) + goto error; + } + + /* delete partition GPT or MTD */ + for (i = 0; i < data->part_nb; i++) { + part = &data->part_array[i]; + + if (part->part_type == RAW_IMAGE) + continue; + + if (!IS_SELECT(part) || !IS_DELETE(part)) + continue; + + ret = part_delete(data, part); + if (ret) + goto error; + } + + return; + +error: + data->part_nb = 0; +} + +int stm32prog_dfu_init(struct stm32prog_data *data) +{ + /* init device if no error */ + if (data->part_nb) + stm32prog_devices_init(data); + + if (data->part_nb) + stm32prog_next_phase(data); + + /* prepare DFU for device read/write */ + dfu_free_entities(); + return dfu_init_entities(data); +} + +int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size) +{ + memset(data, 0x0, sizeof(*data)); + data->read_phase = PHASE_RESET; + data->phase = PHASE_FLASHLAYOUT; + + return parse_flash_layout(data, addr, size); +} + +void stm32prog_clean(struct stm32prog_data *data) +{ + /* clean */ + dfu_free_entities(); + free(data->part_array); + free(data->otp_part); + free(data->buffer); + + if (CONFIG_IS_ENABLED(OPTEE) && data->tee) { + tee_close_session(data->tee, data->tee_session); + data->tee = NULL; + data->tee_session = 0x0; + } +} + +/* DFU callback: used after serial and direct DFU USB access */ +void dfu_flush_callback(struct dfu_entity *dfu) +{ + if (!stm32prog_data) + return; + + if (dfu->dev_type == DFU_DEV_VIRT) { + if (dfu->data.virt.dev_num == PHASE_OTP) + stm32prog_otp_start(stm32prog_data); + else if (dfu->data.virt.dev_num == PHASE_PMIC) + stm32prog_pmic_start(stm32prog_data); + return; + } + + if (dfu->dev_type == DFU_DEV_RAM) { + if (dfu->alt == 0 && + stm32prog_data->phase == PHASE_FLASHLAYOUT) { + stm32prog_end_phase(stm32prog_data, dfu->offset); + /* waiting DFU DETACH for reenumeration */ + } + } + + if (!stm32prog_data->cur_part) + return; + + if (dfu->alt == stm32prog_data->cur_part->alt_id) { + stm32prog_end_phase(stm32prog_data, dfu->offset); + stm32prog_next_phase(stm32prog_data); + } +} + +void dfu_initiated_callback(struct dfu_entity *dfu) +{ + if (!stm32prog_data) + return; + + if (!stm32prog_data->cur_part) + return; + + /* force the saved offset for the current partition */ + if (dfu->alt == stm32prog_data->cur_part->alt_id) { + dfu->offset = stm32prog_data->offset; + stm32prog_data->dfu_seq = 0; + log_debug("dfu offset = 0x%llx\n", dfu->offset); + } +} + +void dfu_error_callback(struct dfu_entity *dfu, const char *msg) +{ + struct stm32prog_data *data = stm32prog_data; + + if (!stm32prog_data) + return; + + if (!stm32prog_data->cur_part) + return; + + if (dfu->alt == stm32prog_data->cur_part->alt_id) + stm32prog_err(msg); +} diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h new file mode 100644 index 00000000000..bf184c8a884 --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +#ifndef _STM32PROG_H_ +#define _STM32PROG_H_ + +#include <linux/printk.h> + +/* - phase defines ------------------------------------------------*/ +#define PHASE_FLASHLAYOUT 0x00 +#define PHASE_FIRST_USER 0x10 +#define PHASE_LAST_USER 0xF0 +#define PHASE_CMD 0xF1 +#define PHASE_OTP 0xF2 +#define PHASE_PMIC 0xF4 +#define PHASE_END 0xFE +#define PHASE_RESET 0xFF +#define PHASE_DO_RESET 0x1FF + +#define DEFAULT_ADDRESS 0xFFFFFFFF + +#define CMD_SIZE 512 +/* SMC is only supported in SPMIN for STM32MP15x */ +#ifdef CONFIG_STM32MP15X +#define OTP_SIZE_SMC 1024 +#else +#define OTP_SIZE_SMC 0 +#endif +/* size of the OTP struct in NVMEM PTA */ +#define _OTP_SIZE_TA(otp) (((otp) * 2 + 2) * 4) +#if defined(CONFIG_STM32MP13X) || defined(CONFIG_STM32MP15X) +/* STM32MP1 with BSEC2 */ +#define OTP_SIZE_TA _OTP_SIZE_TA(96) +#else +/* STM32MP2 with BSEC3 */ +#define OTP_SIZE_TA _OTP_SIZE_TA(368) +#endif +#define PMIC_SIZE 8 + +enum stm32prog_target { + STM32PROG_NONE, + STM32PROG_MMC, + STM32PROG_NAND, + STM32PROG_NOR, + STM32PROG_SPI_NAND, + STM32PROG_RAM +}; + +enum stm32prog_link_t { + LINK_SERIAL, + LINK_USB, + LINK_UNDEFINED, +}; + +enum stm32prog_header_t { + HEADER_NONE, + HEADER_STM32IMAGE, + HEADER_STM32IMAGE_V2, + HEADER_FIP, +}; + +struct image_header_s { + enum stm32prog_header_t type; + u32 image_checksum; + u32 image_length; + u32 length; +}; + +struct stm32_header_v1 { + u32 magic_number; + u8 image_signature[64]; + u32 image_checksum; + u32 header_version; + u32 image_length; + u32 image_entry_point; + u32 reserved1; + u32 load_address; + u32 reserved2; + u32 version_number; + u32 option_flags; + u32 ecdsa_algorithm; + u8 ecdsa_public_key[64]; + u8 padding[83]; + u8 binary_type; +}; + +struct stm32_header_v2 { + u32 magic_number; + u8 image_signature[64]; + u32 image_checksum; + u32 header_version; + u32 image_length; + u32 image_entry_point; + u32 reserved1; + u32 load_address; + u32 reserved2; + u32 version_number; + u32 extension_flags; + u32 extension_headers_length; + u32 binary_type; + u8 padding[16]; + u32 extension_header_type; + u32 extension_header_length; + u8 extension_padding[376]; +}; + +/* + * partition type in flashlayout file + * SYSTEM = linux partition, bootable + * FILESYSTEM = linux partition + * ESP = EFI system partition + */ +enum stm32prog_part_type { + PART_BINARY, + PART_FIP, + PART_FWU_MDATA, + PART_ENV, + PART_SYSTEM, + PART_FILESYSTEM, + PART_ESP, + RAW_IMAGE, +}; + +/* device information */ +struct stm32prog_dev_t { + enum stm32prog_target target; + char dev_id; + u32 erase_size; + struct mmc *mmc; + struct mtd_info *mtd; + /* list of partition for this device / ordered in offset */ + struct list_head part_list; + bool full_update; +}; + +/* partition information build from FlashLayout and device */ +struct stm32prog_part_t { + /* FlashLayout information */ + int option; + int id; + enum stm32prog_part_type part_type; + enum stm32prog_target target; + char dev_id; + + /* partition name + * (16 char in gpt, + 1 for null terminated string + */ + char name[16 + 1]; + u64 addr; + u64 size; + enum stm32prog_part_type bin_nb; /* SSBL repeatition */ + + /* information on associated device */ + struct stm32prog_dev_t *dev; /* pointer to device */ + s16 part_id; /* partition id in device */ + int alt_id; /* alt id in usb/dfu */ + + struct list_head list; +}; + +#define STM32PROG_MAX_DEV 5 +struct stm32prog_data { + /* Layout information */ + int dev_nb; /* device number*/ + struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */ + int part_nb; /* nb of partition */ + struct stm32prog_part_t *part_array; /* array of partition */ + bool fsbl_nor_detected; + + /* command internal information */ + unsigned int phase; + u32 offset; + char error[255]; + struct stm32prog_part_t *cur_part; + void *otp_part; + u8 pmic_part[PMIC_SIZE]; + + /* SERIAL information */ + u32 cursor; + u32 packet_number; + u8 *buffer; /* size = USART_RAM_BUFFER_SIZE*/ + int dfu_seq; + u8 read_phase; + + /* bootm information */ + uintptr_t uimage; + uintptr_t dtb; + uintptr_t initrd; + size_t initrd_size; + + uintptr_t script; + + /* OPTEE PTA NVMEM */ + struct udevice *tee; + u32 tee_session; +}; + +extern struct stm32prog_data *stm32prog_data; + +/* OTP access */ +int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, + u8 *buffer, long *size); +int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, + u8 *buffer, long *size); +int stm32prog_otp_start(struct stm32prog_data *data); + +/* PMIC access */ +int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, + u8 *buffer, long *size); +int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, + u8 *buffer, long *size); +int stm32prog_pmic_start(struct stm32prog_data *data); + +/* generic part*/ +void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header); +int stm32prog_dfu_init(struct stm32prog_data *data); +void stm32prog_next_phase(struct stm32prog_data *data); +void stm32prog_do_reset(struct stm32prog_data *data); + +char *stm32prog_get_error(struct stm32prog_data *data); + +#define stm32prog_err(args...) {\ + if (data->phase != PHASE_RESET) { \ + sprintf(data->error, args); \ + data->phase = PHASE_RESET; \ + log_err("Error: %s\n", data->error); } \ + } + +/* Main function */ +int stm32prog_init(struct stm32prog_data *data, uintptr_t addr, ulong size); +void stm32prog_clean(struct stm32prog_data *data); + +#ifdef CONFIG_CMD_STM32PROG_SERIAL +int stm32prog_serial_init(struct stm32prog_data *data, int link_dev); +bool stm32prog_serial_loop(struct stm32prog_data *data); +#else +static inline int stm32prog_serial_init(struct stm32prog_data *data, int link_dev) +{ + return -ENOSYS; +} + +static inline bool stm32prog_serial_loop(struct stm32prog_data *data) +{ + return false; +} +#endif + +#ifdef CONFIG_CMD_STM32PROG_USB +bool stm32prog_usb_loop(struct stm32prog_data *data, int dev); +#else +static inline bool stm32prog_usb_loop(struct stm32prog_data *data, int dev) +{ + return false; +} +#endif + +#endif diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c new file mode 100644 index 00000000000..07c5e0456f8 --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -0,0 +1,866 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +#include <console.h> +#include <dm.h> +#include <dfu.h> +#include <malloc.h> +#include <serial.h> +#include <time.h> +#include <watchdog.h> +#include <asm/arch/sys_proto.h> +#include <dm/lists.h> +#include <dm/device-internal.h> +#include <linux/delay.h> +#include <linux/printk.h> +#include <asm/global_data.h> +#include "stm32prog.h" + +/* - configuration part -----------------------------*/ +#define USART_BL_VERSION 0x40 /* USART bootloader version V4.0*/ +#define UBOOT_BL_VERSION 0x03 /* bootloader version V0.3*/ + +#define USART_RAM_BUFFER_SIZE 256 /* Size of USART_RAM_Buf buffer*/ + +/* - Commands -----------------------------*/ +#define GET_CMD_COMMAND 0x00 /* Get CMD command*/ +#define GET_VER_COMMAND 0x01 /* Get Version command*/ +#define GET_ID_COMMAND 0x02 /* Get ID command*/ +#define GET_PHASE_COMMAND 0x03 /* Get Phase command*/ +#define RM_COMMAND 0x11 /* Read Memory command*/ +#define READ_PART_COMMAND 0x12 /* Read Partition command*/ +#define START_COMMAND 0x21 /* START command (Go)*/ +#define DOWNLOAD_COMMAND 0x31 /* Download command*/ +/* existing command for other STM32 but not used */ +/* ERASE 0x43 */ +/* EXTENDED_ERASE 0x44 */ +/* WRITE_UNPROTECTED 0x73 */ +/* READOUT_PROTECT 0x82 */ +/* READOUT_UNPROTECT 0x92 */ + +/* - miscellaneous defines ----------------------------------------*/ +#define INIT_BYTE 0x7F /*Init Byte ID*/ +#define ACK_BYTE 0x79 /*Acknowlede Byte ID*/ +#define NACK_BYTE 0x1F /*No Acknowlede Byte ID*/ +#define ABORT_BYTE 0x5F /*ABORT*/ + +struct udevice *down_serial_dev; + +const u8 cmd_id[] = { + GET_CMD_COMMAND, + GET_VER_COMMAND, + GET_ID_COMMAND, + GET_PHASE_COMMAND, + RM_COMMAND, + READ_PART_COMMAND, + START_COMMAND, + DOWNLOAD_COMMAND +}; + +#define NB_CMD sizeof(cmd_id) + +/* with 115200 bauds, 20 ms allow to receive the 256 bytes buffer */ +#define TIMEOUT_SERIAL_BUFFER 30 + +/* DFU support for serial *********************************************/ +static struct dfu_entity *stm32prog_get_entity(struct stm32prog_data *data) +{ + int alt_id; + + if (!data->cur_part) + if (data->phase == PHASE_FLASHLAYOUT) + alt_id = 0; + else + return NULL; + else + alt_id = data->cur_part->alt_id; + + return dfu_get_entity(alt_id); +} + +static int stm32prog_write(struct stm32prog_data *data, u8 *buffer, + u32 buffer_size) +{ + struct dfu_entity *dfu_entity; + u8 ret = 0; + + dfu_entity = stm32prog_get_entity(data); + if (!dfu_entity) + return -ENODEV; + + ret = dfu_write(dfu_entity, + buffer, + buffer_size, + data->dfu_seq); + + if (ret) { + stm32prog_err("DFU write failed [%d] cnt: %d", + ret, data->dfu_seq); + } + data->dfu_seq++; + /* handle rollover as in driver/dfu/dfu.c */ + data->dfu_seq &= 0xffff; + if (buffer_size == 0) + data->dfu_seq = 0; /* flush done */ + + return ret; +} + +static int stm32prog_read(struct stm32prog_data *data, u8 phase, u32 offset, + u8 *buffer, u32 buffer_size) +{ + struct dfu_entity *dfu_entity; + struct stm32prog_part_t *part; + u32 size; + int ret, i; + + if (data->dfu_seq) { + stm32prog_err("DFU write pending for phase %d, seq %d", + data->phase, data->dfu_seq); + return -EINVAL; + } + if (phase == PHASE_FLASHLAYOUT || phase > PHASE_LAST_USER) { + stm32prog_err("read failed : phase %d is invalid", phase); + return -EINVAL; + } + if (data->read_phase <= PHASE_LAST_USER && + phase != data->read_phase) { + /* clear previous read session */ + dfu_entity = dfu_get_entity(data->read_phase - 1); + if (dfu_entity) + dfu_transaction_cleanup(dfu_entity); + } + + dfu_entity = NULL; + /* found partition for the expected phase */ + for (i = 0; i < data->part_nb; i++) { + part = &data->part_array[i]; + if (part->id == phase) + dfu_entity = dfu_get_entity(part->alt_id); + } + if (!dfu_entity) { + stm32prog_err("read failed : phase %d is unknown", phase); + return -ENODEV; + } + + /* clear pending read before to force offset */ + if (dfu_entity->inited && + (data->read_phase != phase || data->offset != offset)) + dfu_transaction_cleanup(dfu_entity); + + /* initiate before to force offset */ + if (!dfu_entity->inited) { + ret = dfu_transaction_initiate(dfu_entity, true); + if (ret < 0) { + stm32prog_err("DFU read init failed [%d] phase = %d offset = 0x%08x", + ret, phase, offset); + return ret; + } + } + /* force new offset */ + if (dfu_entity->offset != offset) + dfu_entity->offset = offset; + data->offset = offset; + data->read_phase = phase; + log_debug("\nSTM32 download read %s offset=0x%x\n", + dfu_entity->name, offset); + ret = dfu_read(dfu_entity, buffer, buffer_size, + dfu_entity->i_blk_seq_num); + if (ret < 0) { + stm32prog_err("DFU read failed [%d] phase = %d offset = 0x%08x", + ret, phase, offset); + return ret; + } + + size = ret; + + if (size < buffer_size) { + data->offset = 0; + data->read_phase = PHASE_END; + memset(buffer + size, 0, buffer_size - size); + } else { + data->offset += size; + } + + return ret; +} + +/* UART access ***************************************************/ +int stm32prog_serial_init(struct stm32prog_data *data, int link_dev) +{ + struct udevice *dev = NULL; + struct dm_serial_ops *ops; + /* no parity, 8 bits, 1 stop */ + u32 serial_config = SERIAL_DEFAULT_CONFIG; + + down_serial_dev = NULL; + + if (uclass_get_device_by_seq(UCLASS_SERIAL, link_dev, &dev)) { + log_err("serial %d device not found\n", link_dev); + return -ENODEV; + } + + down_serial_dev = dev; + + /* force silent console on uart only when used */ + if (gd->cur_serial_dev == down_serial_dev) + gd->flags |= GD_FLG_DISABLE_CONSOLE | GD_FLG_SILENT; + else + gd->flags &= ~(GD_FLG_DISABLE_CONSOLE | GD_FLG_SILENT); + + ops = serial_get_ops(down_serial_dev); + + if (!ops) { + log_err("serial %d = %s missing ops\n", link_dev, dev->name); + return -ENODEV; + } + if (!ops->setconfig) { + log_err("serial %d = %s missing setconfig\n", link_dev, dev->name); + return -ENODEV; + } + + clrsetbits_le32(&serial_config, SERIAL_PAR_MASK, SERIAL_PAR_EVEN); + + data->buffer = memalign(CONFIG_SYS_CACHELINE_SIZE, + USART_RAM_BUFFER_SIZE); + + return ops->setconfig(down_serial_dev, serial_config); +} + +static void stm32prog_serial_flush(void) +{ + struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); + int err; + + do { + err = ops->getc(down_serial_dev); + } while (err != -EAGAIN); +} + +static int stm32prog_serial_getc_err(void) +{ + struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); + int err; + + do { + err = ops->getc(down_serial_dev); + if (err == -EAGAIN) { + ctrlc(); + schedule(); + } + } while ((err == -EAGAIN) && (!had_ctrlc())); + + return err; +} + +static u8 stm32prog_serial_getc(void) +{ + int err; + + err = stm32prog_serial_getc_err(); + + return err >= 0 ? err : 0; +} + +static bool stm32prog_serial_get_buffer(u8 *buffer, u32 *count) +{ + struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); + int err; + ulong start = get_timer(0); + + do { + err = ops->getc(down_serial_dev); + if (err >= 0) { + *buffer++ = err; + *count -= 1; + } else if (err == -EAGAIN) { + ctrlc(); + schedule(); + if (get_timer(start) > TIMEOUT_SERIAL_BUFFER) { + err = -ETIMEDOUT; + break; + } + } else { + break; + } + } while (*count && !had_ctrlc()); + + return !!(err < 0); +} + +static void stm32prog_serial_putc(u8 w_byte) +{ + struct dm_serial_ops *ops = serial_get_ops(down_serial_dev); + int err; + + do { + err = ops->putc(down_serial_dev, w_byte); + } while (err == -EAGAIN); +} + +/* Helper function ************************************************/ +static u8 stm32prog_start(struct stm32prog_data *data, uintptr_t address) +{ + u8 ret = 0; + struct dfu_entity *dfu_entity; + + if (address < 0x100) { + if (address == PHASE_OTP) + return stm32prog_otp_start(data); + + if (address == PHASE_PMIC) + return stm32prog_pmic_start(data); + + if (address == PHASE_RESET || address == PHASE_END) { + data->cur_part = NULL; + data->dfu_seq = 0; + data->phase = address; + return 0; + } + if (address != data->phase) { + stm32prog_err("invalid received phase id %d, current phase is %d", + (u8)address, (u8)data->phase); + return -EINVAL; + } + } + /* check the last loaded partition */ + if (address == DEFAULT_ADDRESS || address == data->phase) { + switch (data->phase) { + case PHASE_END: + case PHASE_RESET: + case PHASE_DO_RESET: + data->cur_part = NULL; + data->phase = PHASE_DO_RESET; + return 0; + } + dfu_entity = stm32prog_get_entity(data); + if (!dfu_entity) + return -ENODEV; + + ret = dfu_flush(dfu_entity, NULL, 0, data->dfu_seq); + if (ret) { + stm32prog_err("DFU flush failed [%d]", ret); + return ret; + } + data->dfu_seq = 0; + + printf("\n received length = 0x%x\n", data->cursor); + + /* update DFU with received flashlayout */ + if (data->phase == PHASE_FLASHLAYOUT) + stm32prog_dfu_init(data); + } else { + void (*entry)(void) = (void *)address; + + printf("## Starting application at 0x%p ...\n", (void *)address); + (*entry)(); + printf("## Application terminated\n"); + ret = -ENOEXEC; + } + + return ret; +} + +/** + * get_address() - Get address if it is valid + * + * @tmp_xor: Current xor value to update + * Return: The address area + */ +static uintptr_t get_address(u8 *tmp_xor) +{ + uintptr_t address = 0x0; + u8 data; + + data = stm32prog_serial_getc(); + *tmp_xor ^= data; + address |= ((u32)data) << 24; + + data = stm32prog_serial_getc(); + address |= ((u32)data) << 16; + *tmp_xor ^= data; + + data = stm32prog_serial_getc(); + address |= ((u32)data) << 8; + *tmp_xor ^= data; + + data = stm32prog_serial_getc(); + address |= ((u32)data); + *tmp_xor ^= data; + + return address; +} + +static void stm32prog_serial_result(u8 result) +{ + /* always flush fifo before to send result */ + stm32prog_serial_flush(); + stm32prog_serial_putc(result); +} + +/* Command -----------------------------------------------*/ +/** + * get_cmd_command() - Respond to Get command + * + * @data: Current command context + */ +static void get_cmd_command(struct stm32prog_data *data) +{ + u32 counter = 0x0; + + stm32prog_serial_putc(NB_CMD); + stm32prog_serial_putc(USART_BL_VERSION); + + for (counter = 0; counter < NB_CMD; counter++) + stm32prog_serial_putc(cmd_id[counter]); + + stm32prog_serial_result(ACK_BYTE); +} + +/** + * get_version_command() - Respond to Get Version command + * + * @data: Current command context + */ +static void get_version_command(struct stm32prog_data *data) +{ + stm32prog_serial_putc(UBOOT_BL_VERSION); + stm32prog_serial_result(ACK_BYTE); +} + +/** + * get_id_command() - Respond to Get ID command + * + * @data: Current command context + */ +static void get_id_command(struct stm32prog_data *data) +{ + u32 cpu = get_cpu_dev(); + + /* Send Device IDCode */ + stm32prog_serial_putc(0x1); + stm32prog_serial_putc((cpu >> 8) & 0xFF); + stm32prog_serial_putc(cpu & 0xFF); + stm32prog_serial_result(ACK_BYTE); +} + +/** + * get_phase_command() - Respond to Get phase + * + * @data: Current command context + */ +static void get_phase_command(struct stm32prog_data *data) +{ + char *err_msg = NULL; + u8 i, length = 0; + u32 destination = DEFAULT_ADDRESS; /* destination address */ + int phase = data->phase; + + if (phase == PHASE_RESET || phase == PHASE_DO_RESET) { + err_msg = stm32prog_get_error(data); + length = strlen(err_msg); + } + if (phase == PHASE_FLASHLAYOUT) + destination = CONFIG_SYS_LOAD_ADDR; + + stm32prog_serial_putc(length + 5); /* Total length */ + stm32prog_serial_putc(phase & 0xFF); /* partition ID */ + stm32prog_serial_putc(destination); /* byte 1 of address */ + stm32prog_serial_putc(destination >> 8); /* byte 2 of address */ + stm32prog_serial_putc(destination >> 16); /* byte 3 of address */ + stm32prog_serial_putc(destination >> 24); /* byte 4 of address */ + + stm32prog_serial_putc(length); /* Information length */ + for (i = 0; i < length; i++) + stm32prog_serial_putc(err_msg[i]); + stm32prog_serial_result(ACK_BYTE); + + if (phase == PHASE_RESET) + stm32prog_do_reset(data); +} + +/** + * read_memory_command() - Read data from memory + * + * @data: Current command context + */ +static void read_memory_command(struct stm32prog_data *data) +{ + uintptr_t address = 0x0; + u8 rcv_data = 0x0, tmp_xor = 0x0; + u32 counter = 0x0; + + /* Read memory address */ + address = get_address(&tmp_xor); + + /* If address memory is not received correctly */ + rcv_data = stm32prog_serial_getc(); + if (rcv_data != tmp_xor) { + stm32prog_serial_result(NACK_BYTE); + return; + } + + stm32prog_serial_result(ACK_BYTE); + + /* Read the number of bytes to be received: + * Max NbrOfData = Data + 1 = 256 + */ + rcv_data = stm32prog_serial_getc(); + tmp_xor = ~rcv_data; + if (stm32prog_serial_getc() != tmp_xor) { + stm32prog_serial_result(NACK_BYTE); + return; + } + + /* If checksum is correct send ACK */ + stm32prog_serial_result(ACK_BYTE); + + /* Send data to the host: + * Number of data to read = data + 1 + */ + for (counter = (rcv_data + 1); counter != 0; counter--) + stm32prog_serial_putc(*(u8 *)(address++)); +} + +/** + * start_command() - Respond to start command + * + * Jump to user application in RAM or partition check + * + * @data: Current command context + */ +static void start_command(struct stm32prog_data *data) +{ + uintptr_t address = 0; + u8 tmp_xor = 0x0; + u8 ret, rcv_data; + + /* Read memory address */ + address = get_address(&tmp_xor); + + /* If address memory is not received correctly */ + rcv_data = stm32prog_serial_getc(); + if (rcv_data != tmp_xor) { + stm32prog_serial_result(NACK_BYTE); + return; + } + /* validate partition */ + ret = stm32prog_start(data, address); + + if (ret) + stm32prog_serial_result(ABORT_BYTE); + else + stm32prog_serial_result(ACK_BYTE); +} + +/** + * download_command() - Respond to download command + * + * Write data to not volatile memory, Flash + * + * @data: Current command context + */ +static void download_command(struct stm32prog_data *data) +{ + u32 address = 0x0; + u8 my_xor = 0x0; + u8 rcv_xor; + u32 counter = 0x0, codesize = 0x0; + u8 *ramaddress = 0; + u8 rcv_data = 0x0; + u32 cursor = data->cursor; + long size = 0; + u8 operation; + u32 packet_number; + u32 result = ACK_BYTE; + u8 ret; + bool error; + int rcv; + + address = get_address(&my_xor); + + /* If address memory is not received correctly */ + rcv_xor = stm32prog_serial_getc(); + if (rcv_xor != my_xor) { + result = NACK_BYTE; + goto end; + } + + /* If address valid send ACK */ + stm32prog_serial_result(ACK_BYTE); + + /* get packet number and operation type */ + operation = (u8)((u32)address >> 24); + packet_number = ((u32)(((u32)address << 8))) >> 8; + + switch (operation) { + /* supported operation */ + case PHASE_FLASHLAYOUT: + case PHASE_OTP: + case PHASE_PMIC: + break; + default: + result = NACK_BYTE; + goto end; + } + /* check the packet number */ + if (packet_number == 0) { + /* erase: re-initialize the image_header struct */ + data->packet_number = 0; + cursor = 0; + data->cursor = 0; + /*idx = cursor;*/ + } else { + data->packet_number++; + } + + /* Check with the number of current packet if the device receive + * the true packet + */ + if (packet_number != data->packet_number) { + data->packet_number--; + result = NACK_BYTE; + goto end; + } + + /*-- Read number of bytes to be written and data -----------*/ + + /* Read the number of bytes to be written: + * Max NbrOfData = data + 1 <= 256 + */ + rcv_data = stm32prog_serial_getc(); + + /* NbrOfData to write = data + 1 */ + codesize = rcv_data + 0x01; + + if (codesize > USART_RAM_BUFFER_SIZE) { + result = NACK_BYTE; + goto end; + } + + /* Checksum Initialization */ + my_xor = rcv_data; + + /* UART receive data and send to Buffer */ + counter = codesize; + error = stm32prog_serial_get_buffer(data->buffer, &counter); + + /* read checksum */ + if (!error) { + rcv = stm32prog_serial_getc_err(); + error = !!(rcv < 0); + rcv_xor = rcv; + } + + if (error) { + printf("transmission error on packet %d, byte %d\n", + packet_number, codesize - counter); + /* waiting end of packet before flush & NACK */ + mdelay(TIMEOUT_SERIAL_BUFFER); + data->packet_number--; + result = NACK_BYTE; + goto end; + } + + /* Compute Checksum */ + ramaddress = data->buffer; + for (counter = codesize; counter != 0; counter--) + my_xor ^= *(ramaddress++); + + /* If Checksum is incorrect */ + if (rcv_xor != my_xor) { + printf("checksum error on packet %d\n", + packet_number); + /* wait to be sure that all data are received + * in the FIFO before flush + */ + mdelay(TIMEOUT_SERIAL_BUFFER); + data->packet_number--; + result = NACK_BYTE; + goto end; + } + + switch (operation) { + case PHASE_OTP: + size = codesize; + ret = stm32prog_otp_write(data, cursor, data->buffer, &size); + break; + + case PHASE_PMIC: + size = codesize; + ret = stm32prog_pmic_write(data, cursor, data->buffer, &size); + break; + + default: + ret = stm32prog_write(data, data->buffer, codesize); + break; + } + + if (ret) + result = ABORT_BYTE; + else + /* Update current position in buffer */ + data->cursor += codesize; + +end: + stm32prog_serial_result(result); +} + +/** + * read_partition() - Respond to read command + * + * Read data from not volatile memory, Flash + * + * @data: Current command context + */ +static void read_partition_command(struct stm32prog_data *data) +{ + u32 i, part_id, codesize, offset = 0, rcv_data; + long size; + u8 tmp_xor; + int res; + u8 buffer[256]; + + part_id = stm32prog_serial_getc(); + tmp_xor = part_id; + + offset = get_address(&tmp_xor); + + rcv_data = stm32prog_serial_getc(); + if (rcv_data != tmp_xor) { + log_debug("1st checksum received = %x, computed %x\n", + rcv_data, tmp_xor); + goto error; + } + stm32prog_serial_putc(ACK_BYTE); + + /* NbrOfData to read = data + 1 */ + rcv_data = stm32prog_serial_getc(); + codesize = rcv_data + 0x01; + tmp_xor = rcv_data; + + rcv_data = stm32prog_serial_getc(); + if ((rcv_data ^ tmp_xor) != 0xFF) { + log_debug("2nd checksum received = %x, computed %x\n", + rcv_data, tmp_xor); + goto error; + } + + log_debug("%s : %x\n", __func__, part_id); + rcv_data = 0; + switch (part_id) { + case PHASE_OTP: + size = codesize; + if (!stm32prog_otp_read(data, offset, buffer, &size)) + rcv_data = size; + break; + case PHASE_PMIC: + size = codesize; + if (!stm32prog_pmic_read(data, offset, buffer, &size)) + rcv_data = size; + break; + default: + res = stm32prog_read(data, part_id, offset, + buffer, codesize); + if (res > 0) + rcv_data = res; + break; + } + if (rcv_data > 0) { + stm32prog_serial_putc(ACK_BYTE); + /*----------- Send data to the host -----------*/ + for (i = 0; i < rcv_data; i++) + stm32prog_serial_putc(buffer[i]); + /*----------- Send filler to the host -----------*/ + for (; i < codesize; i++) + stm32prog_serial_putc(0x0); + return; + } + stm32prog_serial_result(ABORT_BYTE); + return; + +error: + stm32prog_serial_result(NACK_BYTE); +} + +/* MAIN function = SERIAL LOOP ***********************************************/ + +/** + * stm32prog_serial_loop() - USART bootloader Loop routine + * + * @data: Current command context + * Return: true if reset is needed after loop + */ +bool stm32prog_serial_loop(struct stm32prog_data *data) +{ + u32 counter = 0x0; + u8 command = 0x0; + u8 found; + int phase = data->phase; + + /* element of cmd_func need to aligned with cmd_id[]*/ + void (*cmd_func[NB_CMD])(struct stm32prog_data *) = { + /* GET_CMD_COMMAND */ get_cmd_command, + /* GET_VER_COMMAND */ get_version_command, + /* GET_ID_COMMAND */ get_id_command, + /* GET_PHASE_COMMAND */ get_phase_command, + /* RM_COMMAND */ read_memory_command, + /* READ_PART_COMMAND */ read_partition_command, + /* START_COMMAND */ start_command, + /* DOWNLOAD_COMMAND */ download_command + }; + + /* flush and NACK pending command received during u-boot init + * request command reemit + */ + stm32prog_serial_result(NACK_BYTE); + + clear_ctrlc(); /* forget any previous Control C */ + while (!had_ctrlc()) { + phase = data->phase; + + if (phase == PHASE_DO_RESET) + return true; + + /* Get the user command: read first byte */ + command = stm32prog_serial_getc(); + + if (command == INIT_BYTE) { + puts("\nConnected\n"); + stm32prog_serial_result(ACK_BYTE); + continue; + } + + found = 0; + for (counter = 0; counter < NB_CMD; counter++) + if (cmd_id[counter] == command) { + found = 1; + break; + } + if (found) + if ((command ^ stm32prog_serial_getc()) != 0xFF) + found = 0; + if (!found) { + /* wait to be sure that all data are received + * in the FIFO before flush (CMD and XOR) + */ + mdelay(3); + stm32prog_serial_result(NACK_BYTE); + } else { + stm32prog_serial_result(ACK_BYTE); + cmd_func[counter](data); + } + schedule(); + } + + /* clean device */ + if (gd->cur_serial_dev == down_serial_dev) { + /* restore console on uart */ + gd->flags &= ~(GD_FLG_DISABLE_CONSOLE | GD_FLG_SILENT); + } + down_serial_dev = NULL; + + return false; /* no reset after ctrlc */ +} diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c new file mode 100644 index 00000000000..4b1ed50e9fe --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +#include <dfu.h> +#include <g_dnl.h> +#include <usb.h> +#include <asm/arch/stm32prog.h> +#include <asm/arch/sys_proto.h> +#include <linux/printk.h> +#include "stm32prog.h" + +static int stm32prog_set_phase(struct stm32prog_data *data, u8 phase, + u32 offset) +{ + struct stm32prog_part_t *part; + int i; + + if (phase == data->phase) { + data->offset = offset; + data->dfu_seq = 0; + return 0; + } + + /* found partition for phase */ + for (i = 0; i < data->part_nb; i++) { + part = &data->part_array[i]; + if (part->id == phase) { + data->cur_part = part; + data->phase = phase; + data->offset = offset; + data->dfu_seq = 0; + return 0; + } + } + + return -EINVAL; +} + +static int stm32prog_cmd_write(u64 offset, void *buf, long *len) +{ + u8 phase; + uintptr_t address; + u8 *pt = buf; + void (*entry)(void); + int ret; + + if (*len < 5) { + log_err("size not allowed\n"); + return -EINVAL; + } + if (offset) { + log_err("invalid offset\n"); + return -EINVAL; + } + phase = pt[0]; + address = (pt[1] << 24) | (pt[2] << 16) | (pt[3] << 8) | pt[4]; + if (phase == PHASE_RESET) { + entry = (void *)address; + printf("## Starting application at 0x%p ...\n", entry); + (*entry)(); + printf("## Application terminated\n"); + return 0; + } + /* set phase and offset */ + ret = stm32prog_set_phase(stm32prog_data, phase, address); + if (ret) + log_err("failed: %d\n", ret); + return ret; +} + +#define PHASE_MIN_SIZE 9 +static int stm32prog_cmd_read(u64 offset, void *buf, long *len) +{ + u32 destination = DEFAULT_ADDRESS; /* destination address */ + u32 dfu_offset; + u8 *pt_buf = buf; + int phase; + char *err_msg; + int length; + + if (*len < PHASE_MIN_SIZE) { + log_err("request exceeds allowed area\n"); + return -EINVAL; + } + if (offset) { + *len = 0; /* EOF for second request */ + return 0; + } + phase = stm32prog_data->phase; + if (phase == PHASE_FLASHLAYOUT) + destination = CONFIG_SYS_LOAD_ADDR; + dfu_offset = stm32prog_data->offset; + + /* mandatory header, size = PHASE_MIN_SIZE */ + *pt_buf++ = (u8)(phase & 0xFF); + *pt_buf++ = (u8)(destination); + *pt_buf++ = (u8)(destination >> 8); + *pt_buf++ = (u8)(destination >> 16); + *pt_buf++ = (u8)(destination >> 24); + *pt_buf++ = (u8)(dfu_offset); + *pt_buf++ = (u8)(dfu_offset >> 8); + *pt_buf++ = (u8)(dfu_offset >> 16); + *pt_buf++ = (u8)(dfu_offset >> 24); + + if (phase == PHASE_RESET || phase == PHASE_DO_RESET) { + err_msg = stm32prog_get_error(stm32prog_data); + length = strlen(err_msg); + if (length + PHASE_MIN_SIZE > *len) + length = *len - PHASE_MIN_SIZE; + + memcpy(pt_buf, err_msg, length); + *len = PHASE_MIN_SIZE + length; + stm32prog_do_reset(stm32prog_data); + } else if (phase == PHASE_FLASHLAYOUT) { + *pt_buf++ = stm32prog_data->part_nb ? 1 : 0; + *len = PHASE_MIN_SIZE + 1; + } else { + *len = PHASE_MIN_SIZE; + } + + return 0; +} + +int stm32prog_write_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len) +{ + if (dfu->dev_type != DFU_DEV_VIRT) + return -EINVAL; + + switch (dfu->data.virt.dev_num) { + case PHASE_CMD: + return stm32prog_cmd_write(offset, buf, len); + + case PHASE_OTP: + return stm32prog_otp_write(stm32prog_data, (u32)offset, + buf, len); + + case PHASE_PMIC: + return stm32prog_pmic_write(stm32prog_data, (u32)offset, + buf, len); + } + *len = 0; + return 0; +} + +int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len) +{ + if (dfu->dev_type != DFU_DEV_VIRT) + return -EINVAL; + + switch (dfu->data.virt.dev_num) { + case PHASE_CMD: + return stm32prog_cmd_read(offset, buf, len); + + case PHASE_OTP: + return stm32prog_otp_read(stm32prog_data, (u32)offset, + buf, len); + + case PHASE_PMIC: + return stm32prog_pmic_read(stm32prog_data, (u32)offset, + buf, len); + } + *len = 0; + return 0; +} + +int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size) +{ + if (dfu->dev_type != DFU_DEV_VIRT) { + *size = 0; + log_debug("%s, invalid dev_type = %d\n", + __func__, dfu->dev_type); + return -EINVAL; + } + + switch (dfu->data.virt.dev_num) { + case PHASE_CMD: + *size = CMD_SIZE; + break; + case PHASE_OTP: + *size = stm32prog_data->tee ? OTP_SIZE_TA : OTP_SIZE_SMC; + break; + case PHASE_PMIC: + *size = PMIC_SIZE; + break; + } + + return 0; +} + +bool stm32prog_usb_loop(struct stm32prog_data *data, int dev) +{ + int ret; + bool result; + /* USB download gadget for STM32 Programmer */ + char product[128]; + char name[SOC_NAME_SIZE]; + + get_soc_name(name); + snprintf(product, sizeof(product), + "USB download gadget@Device ID /0x%03X, @Revision ID /0x%04X, @Name /%s,", + get_cpu_dev(), get_cpu_rev(), name); + g_dnl_set_product(product); + + if (stm32prog_data->phase == PHASE_FLASHLAYOUT) { + /* forget any previous Control C */ + clear_ctrlc(); + ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu"); + /* DFU reset received, no error or CtrlC */ + if (ret || stm32prog_data->phase != PHASE_FLASHLAYOUT || had_ctrlc()) + return ret; /* true = reset on DFU error */ + /* prepare the second enumeration with the FlashLayout */ + stm32prog_dfu_init(data); + } + + ret = run_usb_dnl_gadget(dev, "usb_dnl_dfu"); + + result = !!(ret) || (stm32prog_data->phase == PHASE_DO_RESET); + + g_dnl_set_product(NULL); + + return result; +} + +int g_dnl_get_board_bcd_device_number(int gcnum) +{ + log_debug("%s\n", __func__); + return 0x200; +} diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c new file mode 100644 index 00000000000..34b958d7afd --- /dev/null +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <dm.h> +#include <efi_loader.h> +#include <image.h> +#include <init.h> +#include <lmb.h> +#include <log.h> +#include <ram.h> +#include <asm/global_data.h> +#include <asm/system.h> +#include <mach/stm32mp.h> + +DECLARE_GLOBAL_DATA_PTR; + +int optee_get_reserved_memory(u32 *start, u32 *size) +{ + fdt_addr_t fdt_mem_size; + fdt_addr_t fdt_start; + ofnode node; + + node = ofnode_path("/reserved-memory/optee"); + if (!ofnode_valid(node)) { + node = ofnode_path("/reserved-memory/optee_core"); + if (!ofnode_valid(node)) + return -ENOENT; + } + + fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); + *start = fdt_start; + *size = fdt_mem_size; + return (fdt_start < 0) ? fdt_start : 0; +} + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + /* in case there is no RAM driver, retrieve DDR size from DT */ + if (ret == -ENODEV) { + return fdtdec_setup_mem_size_base(); + } else if (ret) { + log_err("RAM init failed: %d\n", ret); + return ret; + } + ret = ram_get_info(dev, &ram); + if (ret) { + log_debug("Cannot get RAM size: %d\n", ret); + return ret; + } + log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size); + + gd->ram_size = ram.size; + + return 0; +} + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + phys_size_t size; + phys_addr_t reg; + u32 optee_start, optee_size; + + if (!total_size) + return gd->ram_top; + + /* + * make sure U-Boot uses address space below 4GB boundaries even + * if the effective available memory is bigger + */ + gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + + /* add 8M for U-Boot reserved memory: display, fdt, gd,... */ + size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); + + reg = ALIGN(gd->ram_top - size, MMU_SECTION_SIZE); + + /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */ + if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) { + if (!optee_get_reserved_memory(&optee_start, &optee_size)) + reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); + } + + /* before relocation, mark the U-Boot memory as cacheable by default */ + if (!(gd->flags & GD_FLG_RELOC)) + mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); + + return reg + size; +} diff --git a/arch/arm/mach-stm32mp/ecdsa_romapi.c b/arch/arm/mach-stm32mp/ecdsa_romapi.c new file mode 100644 index 00000000000..93c561c69b1 --- /dev/null +++ b/arch/arm/mach-stm32mp/ecdsa_romapi.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * STM32MP ECDSA verification via the ROM API + * + * Implements ECDSA signature verification via the STM32MP ROM. + */ +#include <asm/system.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <linux/types.h> +#include <u-boot/ecdsa.h> +#include <crypto/ecdsa-uclass.h> +#include <linux/libfdt.h> +#include <dm/platdata.h> + +#define ROM_API_SUCCESS 0x77 +#define ROM_API_ECDSA_ALGO_PRIME_256V1 1 +#define ROM_API_ECDSA_ALGO_BRAINPOOL_256 2 + +#define ROM_API_OFFSET_ECDSA_VERIFY 0x60 + +struct ecdsa_rom_api { + uint32_t (*ecdsa_verify_signature)(const void *hash, const void *pubkey, + const void *signature, + uint32_t ecc_algo); +}; + +static void stm32mp_rom_get_ecdsa_functions(struct ecdsa_rom_api *rom) +{ + uintptr_t verify_ptr = get_stm32mp_rom_api_table() + + ROM_API_OFFSET_ECDSA_VERIFY; + + rom->ecdsa_verify_signature = *(void **)verify_ptr; +} + +static int ecdsa_key_algo(const char *curve_name) +{ + if (!strcmp(curve_name, "prime256v1")) + return ROM_API_ECDSA_ALGO_PRIME_256V1; + else if (!strcmp(curve_name, "brainpool256")) + return ROM_API_ECDSA_ALGO_BRAINPOOL_256; + else + return -ENOPROTOOPT; +} + +static int romapi_ecdsa_verify(struct udevice *dev, + const struct ecdsa_public_key *pubkey, + const void *hash, size_t hash_len, + const void *signature, size_t sig_len) +{ + struct ecdsa_rom_api rom; + uint8_t raw_key[64]; + uint32_t rom_ret; + int algo; + + /* The ROM API can only handle 256-bit ECDSA keys. */ + if (sig_len != 64 || hash_len != 32 || pubkey->size_bits != 256) + return -EINVAL; + + algo = ecdsa_key_algo(pubkey->curve_name); + if (algo < 0) + return algo; + + /* The ROM API wants the (X, Y) coordinates concatenated. */ + memcpy(raw_key, pubkey->x, 32); + memcpy(raw_key + 32, pubkey->y, 32); + + stm32mp_rom_get_ecdsa_functions(&rom); + + /* Mark BootROM region as executable. */ + mmu_set_region_dcache_behaviour(0, SZ_2M, DCACHE_DEFAULT_OPTION); + + rom_ret = rom.ecdsa_verify_signature(hash, raw_key, signature, algo); + + return rom_ret == ROM_API_SUCCESS ? 0 : -EPERM; +} + +static const struct ecdsa_ops rom_api_ops = { + .verify = romapi_ecdsa_verify, +}; + +U_BOOT_DRIVER(stm32mp_rom_api_ecdsa) = { + .name = "stm32mp_rom_api_ecdsa", + .id = UCLASS_ECDSA, + .ops = &rom_api_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRVINFO(stm32mp_rom_api_ecdsa) = { + .name = "stm32mp_rom_api_ecdsa", +}; diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h new file mode 100644 index 00000000000..10ebc535c4b --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/bsec.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +/* check self hosted debug status = BSEC_DENABLE.DBGSWENABLE */ +bool bsec_dbgswenable(void); + +/* Bitfield definition for LOCK status */ +#define BSEC_LOCK_PERM BIT(30) +#define BSEC_LOCK_SHADOW_R BIT(29) +#define BSEC_LOCK_SHADOW_W BIT(28) +#define BSEC_LOCK_SHADOW_P BIT(27) +#define BSEC_LOCK_ERROR BIT(26) diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h new file mode 100644 index 00000000000..bfc42a7c489 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/ddr.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef __MACH_STM32MP_DDR_H_ +#define __MACH_STM32MP_DDR_H_ + +/* DDR power initializations */ +enum ddr_type { + STM32MP_DDR3, + STM32MP_LPDDR2_16, + STM32MP_LPDDR2_32, + STM32MP_LPDDR3_16, + STM32MP_LPDDR3_32, +}; + +int board_ddr_power_init(enum ddr_type ddr_type); + +#endif diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h new file mode 100644 index 00000000000..6eb85ba7233 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#ifndef _MACH_STM32_H_ +#define _MACH_STM32_H_ + +#include <linux/sizes.h> +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> + +enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, + + BOOT_FLASH_SPINAND = 0x70, + BOOT_FLASH_SPINAND_1 = 0x71, +}; + +#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) +#define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16) +#define TAMP_BOOT_AUTH_SHIFT 16 +#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) +#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) +#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4) +#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0) +#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) + +enum forced_boot_mode { + BOOT_NORMAL = 0x00, + BOOT_FASTBOOT = 0x01, + BOOT_RECOVERY = 0x02, + BOOT_STM32PROG = 0x03, + BOOT_UMS_MMC0 = 0x10, + BOOT_UMS_MMC1 = 0x11, + BOOT_UMS_MMC2 = 0x12, +}; + +#endif + +/* + * Peripheral memory map + * only address used before device tree parsing + */ + +#if defined(CONFIG_STM32MP15X) || defined(CONFIG_STM32MP13X) +#define STM32_RCC_BASE 0x50000000 +#define STM32_PWR_BASE 0x50001000 +#define STM32_SYSCFG_BASE 0x50020000 +#ifdef CONFIG_STM32MP15X +#define STM32_DBGMCU_BASE 0x50081000 +#endif +#define STM32_FMC2_BASE 0x58002000 +#define STM32_IWDG2_BASE 0x5A002000 +#define STM32_DDRCTRL_BASE 0x5A003000 +#define STM32_DDRPHYC_BASE 0x5A004000 +#define STM32_IWDG1_BASE 0x5C003000 +#define STM32_TZC_BASE 0x5C006000 +#define STM32_ETZPC_BASE 0x5C007000 +#define STM32_STGEN_BASE 0x5C008000 +#define STM32_TAMP_BASE 0x5C00A000 + +#ifdef CONFIG_STM32MP15X +#define STM32_USART1_BASE 0x5C000000 +#define STM32_USART2_BASE 0x4000E000 +#endif +#ifdef CONFIG_STM32MP13X +#define STM32_USART1_BASE 0x4c000000 +#define STM32_USART2_BASE 0x4c001000 +#endif +#define STM32_USART3_BASE 0x4000F000 +#define STM32_UART4_BASE 0x40010000 +#define STM32_UART5_BASE 0x40011000 +#define STM32_USART6_BASE 0x44003000 +#define STM32_UART7_BASE 0x40018000 +#define STM32_UART8_BASE 0x40019000 + +#define STM32_SDMMC1_BASE 0x58005000 +#define STM32_SDMMC2_BASE 0x58007000 +#define STM32_SDMMC3_BASE 0x48004000 + +#ifdef CONFIG_STM32MP15X +#define STM32_SYSRAM_BASE 0x2FFC0000 +#define STM32_SYSRAM_SIZE SZ_256K +#endif + +#define STM32_DDR_BASE 0xC0000000 +#define STM32_DDR_SIZE SZ_1G + +#ifndef __ASSEMBLY__ +/* + * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT + * - boot device = bit 8:4 + * - boot instance = bit 3:0 + */ +#define BOOT_TYPE_MASK 0xF0 +#define BOOT_TYPE_SHIFT 4 +#define BOOT_INSTANCE_MASK 0x0F +#define BOOT_INSTANCE_SHIFT 0 + +/* TAMP registers */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) + +#ifdef CONFIG_STM32MP15X +#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) +#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) +#define TAMP_FWU_BOOT_INFO_REG TAMP_BACKUP_REGISTER(10) +#define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) +#define TAMP_COPRO_STATE TAMP_BACKUP_REGISTER(18) +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) +#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) + +#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) + +#define TAMP_FWU_BOOT_IDX_OFFSET 0 +#define TAMP_COPRO_STATE_OFF 0 +#define TAMP_COPRO_STATE_INIT 1 +#define TAMP_COPRO_STATE_CRUN 2 +#define TAMP_COPRO_STATE_CSTOP 3 +#define TAMP_COPRO_STATE_STANDBY 4 +#define TAMP_COPRO_STATE_CRASH 5 +#endif + +#ifdef CONFIG_STM32MP13X +#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ + +#ifdef CONFIG_STM32MP25X +#define STM32_RCC_BASE 0x44200000 +#define STM32_TAMP_BASE 0x46010000 + +#define STM32_DDR_BASE 0x80000000 + +#define STM32_DDR_SIZE SZ_4G + +/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x)) + +/* TAMP registers zone 3 RIF 1 (RW) at 96*/ +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) +#endif /* STM32MP25X */ + +/* offset used for BSEC driver: misc_read and misc_write */ +#define STM32_BSEC_SHADOW_OFFSET 0x0 +#define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4) +#define STM32_BSEC_OTP_OFFSET 0x80000000 +#define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4) +#define STM32_BSEC_LOCK_OFFSET 0xC0000000 +#define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4) + +/* BSEC OTP index */ +#ifdef CONFIG_STM32MP15X +#define BSEC_OTP_RPN 1 +#define BSEC_OTP_SERIAL 13 +#define BSEC_OTP_PKG 16 +#define BSEC_OTP_MAC 57 +#define BSEC_OTP_BOARD 59 +#endif +#ifdef CONFIG_STM32MP13X +#define BSEC_OTP_RPN 1 +#define BSEC_OTP_SERIAL 13 +#define BSEC_OTP_MAC 57 +#define BSEC_OTP_BOARD 60 +#endif +#ifdef CONFIG_STM32MP25X +#define BSEC_OTP_SERIAL 5 +#define BSEC_OTP_RPN 9 +#define BSEC_OTP_PKG 122 +#define BSEC_OTP_BOARD 246 +#define BSEC_OTP_MAC 247 +#endif + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* enumerated used to identify the SYSCON driver instance */ +enum { + STM32MP_SYSCON_UNKNOWN, + STM32MP_SYSCON_SYSCFG, +}; +#endif /* __ASSEMBLY__*/ + +#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp.h b/arch/arm/mach-stm32mp/include/mach/stm32mp.h new file mode 100644 index 00000000000..506a42559b8 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/stm32mp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2024, STMicroelectronics - All Rights Reserved + */ + +#ifndef __MACH_STM32MP_H_ +#define __MACH_STM32MP_H_ + +int optee_get_reserved_memory(u32 *start, u32 *size); + +#endif diff --git a/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h new file mode 100644 index 00000000000..1b2bba3d34c --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/stm32mp1_smc.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#ifndef __STM32MP1_SMC_H__ +#define __STM32MP1_SMC_H__ + +#include <linux/arm-smccc.h> +#include <linux/printk.h> + +/* + * SMC function IDs for STM32 Service queries + * STM32 SMC services use the space between 0x82000000 and 0x8200FFFF + * like this is defined in SMC calling Convention by ARM + * for SiP (silicon Partner) + * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + */ +#define STM32_SMC_VERSION 0x82000000 + +/* Secure Service access from Non-secure */ +#define STM32_SMC_BSEC 0x82001003 + +/* Service for BSEC */ +#define STM32_SMC_READ_SHADOW 0x01 +#define STM32_SMC_PROG_OTP 0x02 +#define STM32_SMC_WRITE_SHADOW 0x03 +#define STM32_SMC_READ_OTP 0x04 +#define STM32_SMC_READ_ALL 0x05 +#define STM32_SMC_WRITE_ALL 0x06 +#define STM32_SMC_WRLOCK_OTP 0x07 + +/* SMC error codes */ +#define STM32_SMC_OK 0x0 +#define STM32_SMC_NOT_SUPPORTED -1 +#define STM32_SMC_FAILED -2 +#define STM32_SMC_INVALID_PARAMS -3 + +#define stm32_smc_exec(svc, op, data1, data2) \ + stm32_smc(svc, op, data1, data2, NULL) + +#ifdef CONFIG_ARM_SMCCC +static inline u32 stm32_smc(u32 svc, u8 op, u32 data1, u32 data2, u32 *result) +{ + struct arm_smccc_res res; + + arm_smccc_smc(svc, op, data1, data2, 0, 0, 0, 0, &res); + + if (res.a0) { + pr_err("%s: Failed to exec svc=%x op=%x in secure mode (err = %ld)\n", + __func__, svc, op, res.a0); + return -EINVAL; + } + if (result) + *result = (u32)res.a1; + + return 0; +} +#else +static inline u32 stm32_smc(u32 svc, u8 op, u32 data1, u32 data2, u32 *result) +{ + return 0; +} +#endif + +#endif /* __STM32MP1_SMC_H__ */ diff --git a/arch/arm/mach-stm32mp/include/mach/stm32prog.h b/arch/arm/mach-stm32mp/include/mach/stm32prog.h new file mode 100644 index 00000000000..23d1adfbad9 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/stm32prog.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +#define STM32PROG_VIRT_FIRST_DEV_NUM 0xF1 + +int stm32prog_write_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len); +int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset, + void *buf, long *len); +int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size); + +bool stm32prog_get_fsbl_nor(void); diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h new file mode 100644 index 00000000000..2a65efc0a50 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved + */ + +/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */ +#define CPU_STM32MP157Cxx 0x05000000 +#define CPU_STM32MP157Axx 0x05000001 +#define CPU_STM32MP153Cxx 0x05000024 +#define CPU_STM32MP153Axx 0x05000025 +#define CPU_STM32MP151Cxx 0x0500002E +#define CPU_STM32MP151Axx 0x0500002F +#define CPU_STM32MP157Fxx 0x05000080 +#define CPU_STM32MP157Dxx 0x05000081 +#define CPU_STM32MP153Fxx 0x050000A4 +#define CPU_STM32MP153Dxx 0x050000A5 +#define CPU_STM32MP151Fxx 0x050000AE +#define CPU_STM32MP151Dxx 0x050000AF + +#define CPU_STM32MP135Cxx 0x05010000 +#define CPU_STM32MP135Axx 0x05010001 +#define CPU_STM32MP133Cxx 0x050100C0 +#define CPU_STM32MP133Axx 0x050100C1 +#define CPU_STM32MP131Cxx 0x050106C8 +#define CPU_STM32MP131Axx 0x050106C9 +#define CPU_STM32MP135Fxx 0x05010800 +#define CPU_STM32MP135Dxx 0x05010801 +#define CPU_STM32MP133Fxx 0x050108C0 +#define CPU_STM32MP133Dxx 0x050108C1 +#define CPU_STM32MP131Fxx 0x05010EC8 +#define CPU_STM32MP131Dxx 0x05010EC9 + +/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ +#define CPU_STM32MP257Cxx 0x00002000 +#define CPU_STM32MP255Cxx 0x00082000 +#define CPU_STM32MP253Cxx 0x000B2004 +#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP257Axx 0x40002E00 +#define CPU_STM32MP255Axx 0x40082E00 +#define CPU_STM32MP253Axx 0x400B2E04 +#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP257Fxx 0x80002000 +#define CPU_STM32MP255Fxx 0x80082000 +#define CPU_STM32MP253Fxx 0x800B2004 +#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP257Dxx 0xC0002E00 +#define CPU_STM32MP255Dxx 0xC0082E00 +#define CPU_STM32MP253Dxx 0xC00B2E04 +#define CPU_STM32MP251Dxx 0xC00B3E65 + +/* return CPU_STMP32MP...Xxx constants */ +u32 get_cpu_type(void); + +#define CPU_DEV_STM32MP15 0x500 +#define CPU_DEV_STM32MP13 0x501 +#define CPU_DEV_STM32MP25 0x505 + +/* return CPU_DEV constants */ +u32 get_cpu_dev(void); + +#define CPU_REV1 0x1000 +#define CPU_REV1_1 0x1001 +#define CPU_REV1_2 0x1003 +#define CPU_REV2 0x2000 +#define CPU_REV2_1 0x2001 +#define CPU_REV2_2 0x2003 + +/* return Silicon revision = REV_ID[15:0] of Device Version */ +u32 get_cpu_rev(void); + +/* Get Package options from OTP */ +u32 get_cpu_package(void); + +/* package used for STM32MP15x */ +#define STM32MP15_PKG_AA_LBGA448 4 +#define STM32MP15_PKG_AB_LBGA354 3 +#define STM32MP15_PKG_AC_TFBGA361 2 +#define STM32MP15_PKG_AD_TFBGA257 1 +#define STM32MP15_PKG_UNKNOWN 0 + +/* package used for STM32MP25x */ +#define STM32MP25_PKG_CUSTOM 0 +#define STM32MP25_PKG_AL_TBGA361 3 +#define STM32MP25_PKG_AK_TBGA424 4 +#define STM32MP25_PKG_AI_TBGA436 5 +#define STM32MP25_PKG_UNKNOWN 7 + +/* Get SOC name */ +#define SOC_NAME_SIZE 20 +void get_soc_name(char name[SOC_NAME_SIZE]); + +/* return boot mode */ +u32 get_bootmode(void); + +/* return auth status and partition */ +u32 get_bootauth(void); + +int get_eth_nb(void); +int setup_mac_address(void); +int setup_serial_number(void); + +/* board power management : configure vddcore according OPP */ +void board_vddcore_init(u32 voltage_mv); + +/* weak function */ +void stm32mp_cpu_init(void); +void stm32mp_misc_init(void); + +/* helper function: read data from OTP */ +u32 get_otp(int index, int shift, int mask); + +uintptr_t get_stm32mp_rom_api_table(void); +uintptr_t get_stm32mp_bl2_dtb(void); diff --git a/arch/arm/mach-stm32mp/include/mach/timers.h b/arch/arm/mach-stm32mp/include/mach/timers.h new file mode 100644 index 00000000000..a84465bb28e --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/timers.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * Author: Cheick Traore <cheick.traore@foss.st.com> + * + * Originally based on the Linux kernel v6.1 include/linux/mfd/stm32-timers.h. + */ + +#ifndef __STM32_TIMERS_H +#define __STM32_TIMERS_H + +#include <clk.h> + +#define TIM_CR1 0x00 /* Control Register 1 */ +#define TIM_CR2 0x04 /* Control Register 2 */ +#define TIM_SMCR 0x08 /* Slave mode control reg */ +#define TIM_DIER 0x0C /* DMA/interrupt register */ +#define TIM_SR 0x10 /* Status register */ +#define TIM_EGR 0x14 /* Event Generation Reg */ +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ +#define TIM_CNT 0x24 /* Counter */ +#define TIM_PSC 0x28 /* Prescaler */ +#define TIM_ARR 0x2c /* Auto-Reload Register */ +#define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */ +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ +#define TIM_DCR 0x48 /* DMA control register */ +#define TIM_DMAR 0x4C /* DMA register for transfer */ +#define TIM_TISEL 0x68 /* Input Selection */ + +#define TIM_CR1_CEN BIT(0) /* Counter Enable */ +#define TIM_CR1_ARPE BIT(7) +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) +#define TIM_CCER_CC1E BIT(0) +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ +#define TIM_EGR_UG BIT(0) /* Update Generation */ + +#define MAX_TIM_PSC 0xFFFF + +struct stm32_timers_plat { + void __iomem *base; +}; + +struct stm32_timers_priv { + u32 max_arr; + ulong rate; +}; + +#endif diff --git a/arch/arm/mach-stm32mp/include/mach/tzc.h b/arch/arm/mach-stm32mp/include/mach/tzc.h new file mode 100644 index 00000000000..16db55c4645 --- /dev/null +++ b/arch/arm/mach-stm32mp/include/mach/tzc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Simple API for configuring TrustZone memory regions + * + * The premise is that the desired TZC layout is known beforehand, and it can + * be configured in one step. tzc_configure() provides this functionality. + */ +#ifndef MACH_TZC_H +#define MACH_TZC_H + +#include <linux/types.h> + +enum tzc_sec_mode { + TZC_ATTR_SEC_NONE = 0, + TZC_ATTR_SEC_R = 1, + TZC_ATTR_SEC_W = 2, + TZC_ATTR_SEC_RW = 3 +}; + +struct tzc_region { + uintptr_t base; + uintptr_t top; + enum tzc_sec_mode sec_mode; + uint16_t nsec_id; + uint16_t filters_mask; +}; + +int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg); +int tzc_disable_filters(uintptr_t tzc, uint16_t filters_mask); +int tzc_enable_filters(uintptr_t tzc, uint16_t filters_mask); +void tzc_dump_config(uintptr_t tzc); + +#endif /* MACH_TZC_H */ diff --git a/arch/arm/mach-stm32mp/soc.c b/arch/arm/mach-stm32mp/soc.c new file mode 100644 index 00000000000..fa56b0d2e0f --- /dev/null +++ b/arch/arm/mach-stm32mp/soc.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2024, STMicroelectronics - All Rights Reserved + */ + +#include <env.h> +#include <misc.h> +#include <net.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> + +/* max: 8 OTP for 5 mac address on stm32mp2*/ +#define MAX_NB_OTP 8 + +/* used when CONFIG_DISPLAY_CPUINFO is activated */ +int print_cpuinfo(void) +{ + char name[SOC_NAME_SIZE]; + + get_soc_name(name); + printf("CPU: %s\n", name); + + return 0; +} + +int setup_serial_number(void) +{ + char serial_string[25]; + u32 otp[3] = {0, 0, 0 }; + struct udevice *dev; + int ret; + + if (env_get("serial#")) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL), + otp, sizeof(otp)); + if (ret < 0) + return ret; + + sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]); + env_set("serial#", serial_string); + + return 0; +} + +/* + * If there is no MAC address in the environment, then it will be initialized + * (silently) from the value in the OTP. + */ +__weak int setup_mac_address(void) +{ + int ret; + int i; + u32 otp[MAX_NB_OTP]; + uchar enetaddr[ARP_HLEN]; + struct udevice *dev; + int nb_eth, nb_otp, index; + + if (!IS_ENABLED(CONFIG_NET)) + return 0; + + nb_eth = get_eth_nb(); + if (!nb_eth) + return 0; + + /* 6 bytes for each MAC addr and 4 bytes for each OTP */ + nb_otp = DIV_ROUND_UP(ARP_HLEN * nb_eth, 4); + if (nb_otp > MAX_NB_OTP) { + log_err("invalid number of OTP = %d, max = %d\n", nb_otp, MAX_NB_OTP); + return -EINVAL; + } + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp); + if (ret < 0) + return ret; + + for (index = 0; index < nb_eth; index++) { + /* MAC already in environment */ + if (eth_env_get_enetaddr_by_index("eth", index, enetaddr)) + continue; + + for (i = 0; i < ARP_HLEN; i++) + enetaddr[i] = ((uint8_t *)&otp)[i + ARP_HLEN * index]; + + /* skip FF:FF:FF:FF:FF:FF */ + if (is_broadcast_ethaddr(enetaddr)) + continue; + + if (!is_valid_ethaddr(enetaddr)) { + log_err("invalid MAC address %d in OTP %pM\n", + index, enetaddr); + return -EINVAL; + } + log_debug("OTP MAC address %d = %pM\n", index, enetaddr); + ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr); + if (ret) { + log_err("Failed to set mac address %pM from OTP: %d\n", + enetaddr, ret); + return ret; + } + } + + return 0; +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile new file mode 100644 index 00000000000..db160c24cbc --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o + +obj-$(CONFIG_STM32MP13X) += stm32mp13x.o +obj-$(CONFIG_STM32MP15X) += stm32mp15x.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-y += tzc400.o +else +obj-$(CONFIG_ARMV7_PSCI) += psci.o +endif + +obj-$(CONFIG_$(XPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c new file mode 100644 index 00000000000..18175fd12cc --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <clk.h> +#include <cpu_func.h> +#include <debug_uart.h> +#include <env.h> +#include <init.h> +#include <log.h> +#include <lmb.h> +#include <misc.h> +#include <spl.h> +#include <asm/cache.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <linux/bitops.h> +#include <linux/printk.h> + +/* + * early TLB into the .data section so that it not get cleared + * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) + */ +u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); + +u32 get_bootmode(void) +{ + /* read bootmode from TAMP backup register */ + return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> + TAMP_BOOT_MODE_SHIFT; +} + +u32 get_bootauth(void) +{ + /* read boot auth status and partition from TAMP backup register */ + return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_AUTH_MASK) >> + TAMP_BOOT_AUTH_SHIFT; +} + +/* + * weak function overidde: set the DDR/SYSRAM executable before to enable the + * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) + */ +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + int i; + phys_addr_t start; + phys_addr_t addr; + phys_size_t size; + bool use_lmb = false; + enum dcache_option option; + + if (IS_ENABLED(CONFIG_XPL_BUILD)) { +/* STM32_SYSRAM_BASE exist only when SPL is supported */ +#ifdef CONFIG_SPL + start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); + size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); +#endif + } else if (gd->flags & GD_FLG_RELOC) { + /* bd->bi_dram is available only after relocation */ + start = bd->bi_dram[bank].start; + size = bd->bi_dram[bank].size; + use_lmb = true; + } else { + /* mark cacheable and executable the beggining of the DDR */ + start = STM32_DDR_BASE; + size = CONFIG_DDR_CACHEABLE_SIZE; + } + + for (i = start >> MMU_SECTION_SHIFT; + i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); + i++) { + addr = i << MMU_SECTION_SHIFT; + option = DCACHE_DEFAULT_OPTION; + if (use_lmb && + (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) || + (gd->ram_top && addr >= gd->ram_top)) + ) + option = 0; /* INVALID ENTRY in TLB */ + set_section_dcache(i, option); + } +} +/* + * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 + */ +static void early_enable_caches(void) +{ + /* I-cache is already enabled in start.S: cpu_init_cp15 */ + + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; +#endif + + /* enable MMU (default configuration) */ + dcache_enable(); +} + +/* + * Early system init + */ +int arch_cpu_init(void) +{ + early_enable_caches(); + + /* early armv7 timer init: needed for polling */ + timer_init(); + + return 0; +} + +/* weak function for SOC specific initialization */ +__weak void stm32mp_cpu_init(void) +{ +} + +int mach_cpu_init(void) +{ + u32 boot_mode; + + stm32mp_cpu_init(); + + boot_mode = get_bootmode(); + + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && + (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + + return 0; +} + +void enable_caches(void) +{ + /* I-cache is already enabled in start.S: icache_enable() not needed */ + + /* keep D-cache configuration done before relocation, wait arch_early_init_r*/ +} + +int arch_early_init_r(void) +{ + /* deactivate the data cache, early enabled in arch_cpu_init() */ + dcache_disable(); + /* + * update MMU after relocation and enable the data cache + * warning: the TLB location udpated in board_f.c::reserve_mmu + */ + dcache_enable(); + + return 0; +} + +static void setup_boot_mode(void) +{ + const u32 serial_addr[] = { + STM32_USART1_BASE, + STM32_USART2_BASE, + STM32_USART3_BASE, + STM32_UART4_BASE, + STM32_UART5_BASE, + STM32_USART6_BASE, + STM32_UART7_BASE, + STM32_UART8_BASE + }; + const u32 sdmmc_addr[] = { + STM32_SDMMC1_BASE, + STM32_SDMMC2_BASE, + STM32_SDMMC3_BASE + }; + char cmd[60]; + u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); + u32 boot_mode = + (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; + unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; + u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); + struct udevice *dev; + + log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", + __func__, boot_ctx, boot_mode, instance, forced_mode); + switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_SERIAL_UART: + if (instance >= ARRAY_SIZE(serial_addr)) + break; + /* serial : search associated node in devicetree */ + sprintf(cmd, "serial@%x", serial_addr[instance]); + if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { + /* restore console on error */ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + log_err("uart%d = %s not found in device tree!\n", + instance + 1, cmd); + break; + } + sprintf(cmd, "%d", dev_seq(dev)); + env_set("boot_device", "serial"); + env_set("boot_instance", cmd); + + /* restore console on uart when not used */ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + log_info("serial boot with console enabled!\n"); + } + break; + case BOOT_SERIAL_USB: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + if (instance >= ARRAY_SIZE(sdmmc_addr)) + break; + /* search associated sdmmc node in devicetree */ + sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); + if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) { + printf("mmc%d = %s not found in device tree!\n", + instance, cmd); + break; + } + sprintf(cmd, "%d", dev_seq(dev)); + env_set("boot_device", "mmc"); + env_set("boot_instance", cmd); + break; + case BOOT_FLASH_NAND: + env_set("boot_device", "nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SPINAND: + env_set("boot_device", "spi-nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_NOR: + env_set("boot_device", "nor"); + env_set("boot_instance", "0"); + break; + default: + env_set("boot_device", "invalid"); + env_set("boot_instance", ""); + log_err("unexpected boot mode = %x\n", boot_mode); + break; + } + + switch (forced_mode) { + case BOOT_FASTBOOT: + log_info("Enter fastboot!\n"); + env_set("preboot", "env set preboot; fastboot 0"); + break; + case BOOT_STM32PROG: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_UMS_MMC0: + case BOOT_UMS_MMC1: + case BOOT_UMS_MMC2: + log_info("Enter UMS!\n"); + instance = forced_mode - BOOT_UMS_MMC0; + sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); + env_set("preboot", cmd); + break; + case BOOT_RECOVERY: + env_set("preboot", "env set preboot; run altbootcmd"); + break; + case BOOT_NORMAL: + break; + default: + log_debug("unexpected forced boot mode = %x\n", forced_mode); + break; + } + + /* clear TAMP for next reboot */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); +} + +__weak void stm32mp_misc_init(void) +{ +} + +static int setup_boot_auth_info(void) +{ + char buf[10]; + u32 bootauth = get_bootauth(); + + snprintf(buf, sizeof(buf), "%d", bootauth >> 4); + env_set("boot_auth", buf); + + snprintf(buf, sizeof(buf), "%d", bootauth & + (u32)TAMP_BOOT_PARTITION_MASK); + env_set("boot_part", buf); + + return 0; +} + +int arch_misc_init(void) +{ + setup_boot_auth_info(); + setup_boot_mode(); + setup_mac_address(); + setup_serial_number(); + stm32mp_misc_init(); + + return 0; +} + +/* + * Without forcing the ".data" section, this would get saved in ".bss". BSS + * will be cleared soon after, so it's not suitable. + */ +static uintptr_t rom_api_table __section(".data"); +static uintptr_t nt_fw_dtb __section(".data"); + +/* + * The ROM gives us the API location in r0 when starting. This is only available + * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save + * the FDT address provided by TF-A in r2 at boot time. This function is called + * from start.S + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY)) + rom_api_table = r0; + + if (IS_ENABLED(CONFIG_TFABOOT)) + nt_fw_dtb = r2; + + save_boot_params_ret(); +} + +uintptr_t get_stm32mp_rom_api_table(void) +{ + return rom_api_table; +} + +uintptr_t get_stm32mp_bl2_dtb(void) +{ + return nt_fw_dtb; +} + +#ifdef CONFIG_XPL_BUILD +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); + uintptr_t romapi = get_stm32mp_rom_api_table(); + + image_entry_stm32_t image_entry = + (image_entry_stm32_t)spl_image->entry_point; + + printf("image entry point: 0x%lx\n", spl_image->entry_point); + image_entry(romapi); +} +#endif diff --git a/arch/arm/mach-stm32mp/stm32mp1/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c new file mode 100644 index 00000000000..e1e4dc04e01 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c @@ -0,0 +1,514 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <fdtdec.h> +#include <fdt_support.h> +#include <log.h> +#include <tee.h> +#include <mach/stm32.h> +#include <asm/arch/sys_proto.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> +#include <linux/io.h> + +#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n)) +#define ETZPC_DECPROT_NB 6 + +#define DECPROT_MASK 0x03 +#define NB_PROT_PER_REG 0x10 +#define DECPROT_NB_BITS 2 + +#define DECPROT_SECURED 0x00 +#define DECPROT_WRITE_SECURE 0x01 +#define DECPROT_MCU_ISOLATION 0x02 +#define DECPROT_NON_SECURED 0x03 + +#define ETZPC_RESERVED 0xffffffff + +#define STM32MP13_FDCAN_BASE 0x4400F000 +#define STM32MP13_ADC1_BASE 0x48003000 +#define STM32MP13_TSC_BASE 0x5000B000 +#define STM32MP13_CRYP_BASE 0x54002000 +#define STM32MP13_ETH2_BASE 0x5800E000 +#define STM32MP13_DCMIPP_BASE 0x5A000000 +#define STM32MP13_LTDC_BASE 0x5A010000 + +#define STM32MP15_FDCAN_BASE 0x4400e000 +#define STM32MP15_CRYP2_BASE 0x4c005000 +#define STM32MP15_CRYP1_BASE 0x54001000 +#define STM32MP15_GPU_BASE 0x59000000 +#define STM32MP15_DSI_BASE 0x5a000000 + +static const u32 stm32mp13_ip_addr[] = { + 0x50025000, /* 0 VREFBUF APB3 */ + 0x50021000, /* 1 LPTIM2 APB3 */ + 0x50022000, /* 2 LPTIM3 APB3 */ + STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */ + STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */ + 0x5A006000, /* 5 USBPHYCTRL APB4 */ + 0x5A003000, /* 6 DDRCTRLPHY APB4 */ + ETZPC_RESERVED, /* 7 Reserved*/ + ETZPC_RESERVED, /* 8 Reserved*/ + ETZPC_RESERVED, /* 9 Reserved*/ + 0x5C006000, /* 10 TZC APB5 */ + 0x58001000, /* 11 MCE APB5 */ + 0x5C000000, /* 12 IWDG1 APB5 */ + 0x5C008000, /* 13 STGENC APB5 */ + ETZPC_RESERVED, /* 14 Reserved*/ + ETZPC_RESERVED, /* 15 Reserved*/ + 0x4C000000, /* 16 USART1 APB6 */ + 0x4C001000, /* 17 USART2 APB6 */ + 0x4C002000, /* 18 SPI4 APB6 */ + 0x4C003000, /* 19 SPI5 APB6 */ + 0x4C004000, /* 20 I2C3 APB6 */ + 0x4C005000, /* 21 I2C4 APB6 */ + 0x4C006000, /* 22 I2C5 APB6 */ + 0x4C007000, /* 23 TIM12 APB6 */ + 0x4C008000, /* 24 TIM13 APB6 */ + 0x4C009000, /* 25 TIM14 APB6 */ + 0x4C00A000, /* 26 TIM15 APB6 */ + 0x4C00B000, /* 27 TIM16 APB6 */ + 0x4C00C000, /* 28 TIM17 APB6 */ + ETZPC_RESERVED, /* 29 Reserved*/ + ETZPC_RESERVED, /* 30 Reserved*/ + ETZPC_RESERVED, /* 31 Reserved*/ + STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */ + 0x48004000, /* 33 ADC2 AHB2 */ + 0x49000000, /* 34 OTG AHB2 */ + ETZPC_RESERVED, /* 35 Reserved*/ + ETZPC_RESERVED, /* 36 Reserved*/ + STM32MP13_TSC_BASE, /* 37 TSC AHB4 */ + ETZPC_RESERVED, /* 38 Reserved*/ + ETZPC_RESERVED, /* 39 Reserved*/ + 0x54004000, /* 40 RNG AHB5 */ + 0x54003000, /* 41 HASH AHB5 */ + STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */ + 0x54005000, /* 43 SAES AHB5 */ + 0x54006000, /* 44 PKA AHB5 */ + 0x54000000, /* 45 BKPSRAM AHB5 */ + ETZPC_RESERVED, /* 46 Reserved*/ + ETZPC_RESERVED, /* 47 Reserved*/ + 0x5800A000, /* 48 ETH1 AHB6 */ + STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */ + 0x58005000, /* 50 SDMMC1 AHB6 */ + 0x58007000, /* 51 SDMMC2 AHB6 */ + ETZPC_RESERVED, /* 52 Reserved*/ + ETZPC_RESERVED, /* 53 Reserved*/ + 0x58002000, /* 54 FMC AHB6 */ + 0x58003000, /* 55 QSPI AHB6 */ + ETZPC_RESERVED, /* 56 Reserved*/ + ETZPC_RESERVED, /* 57 Reserved*/ + ETZPC_RESERVED, /* 58 Reserved*/ + ETZPC_RESERVED, /* 59 Reserved*/ + 0x30000000, /* 60 SRAM1 MLAHB */ + 0x30004000, /* 61 SRAM2 MLAHB */ + 0x30006000, /* 62 SRAM3 MLAHB */ + ETZPC_RESERVED, /* 63 Reserved*/ + ETZPC_RESERVED, /* 64 Reserved*/ + ETZPC_RESERVED, /* 65 Reserved*/ + ETZPC_RESERVED, /* 66 Reserved*/ + ETZPC_RESERVED, /* 67 Reserved*/ + ETZPC_RESERVED, /* 68 Reserved*/ + ETZPC_RESERVED, /* 69 Reserved*/ + ETZPC_RESERVED, /* 70 Reserved*/ + ETZPC_RESERVED, /* 71 Reserved*/ + ETZPC_RESERVED, /* 72 Reserved*/ + ETZPC_RESERVED, /* 73 Reserved*/ + ETZPC_RESERVED, /* 74 Reserved*/ + ETZPC_RESERVED, /* 75 Reserved*/ + ETZPC_RESERVED, /* 76 Reserved*/ + ETZPC_RESERVED, /* 77 Reserved*/ + ETZPC_RESERVED, /* 78 Reserved*/ + ETZPC_RESERVED, /* 79 Reserved*/ + ETZPC_RESERVED, /* 80 Reserved*/ + ETZPC_RESERVED, /* 81 Reserved*/ + ETZPC_RESERVED, /* 82 Reserved*/ + ETZPC_RESERVED, /* 83 Reserved*/ + ETZPC_RESERVED, /* 84 Reserved*/ + ETZPC_RESERVED, /* 85 Reserved*/ + ETZPC_RESERVED, /* 86 Reserved*/ + ETZPC_RESERVED, /* 87 Reserved*/ + ETZPC_RESERVED, /* 88 Reserved*/ + ETZPC_RESERVED, /* 89 Reserved*/ + ETZPC_RESERVED, /* 90 Reserved*/ + ETZPC_RESERVED, /* 91 Reserved*/ + ETZPC_RESERVED, /* 92 Reserved*/ + ETZPC_RESERVED, /* 93 Reserved*/ + ETZPC_RESERVED, /* 94 Reserved*/ + ETZPC_RESERVED, /* 95 Reserved*/ +}; + +static const u32 stm32mp15_ip_addr[] = { + 0x5c008000, /* 00 stgenc */ + 0x54000000, /* 01 bkpsram */ + 0x5c003000, /* 02 iwdg1 */ + 0x5c000000, /* 03 usart1 */ + 0x5c001000, /* 04 spi6 */ + 0x5c002000, /* 05 i2c4 */ + ETZPC_RESERVED, /* 06 reserved */ + 0x54003000, /* 07 rng1 */ + 0x54002000, /* 08 hash1 */ + STM32MP15_CRYP1_BASE, /* 09 cryp1 */ + 0x5a003000, /* 0A ddrctrl */ + 0x5a004000, /* 0B ddrphyc */ + 0x5c009000, /* 0C i2c6 */ + ETZPC_RESERVED, /* 0D reserved */ + ETZPC_RESERVED, /* 0E reserved */ + ETZPC_RESERVED, /* 0F reserved */ + 0x40000000, /* 10 tim2 */ + 0x40001000, /* 11 tim3 */ + 0x40002000, /* 12 tim4 */ + 0x40003000, /* 13 tim5 */ + 0x40004000, /* 14 tim6 */ + 0x40005000, /* 15 tim7 */ + 0x40006000, /* 16 tim12 */ + 0x40007000, /* 17 tim13 */ + 0x40008000, /* 18 tim14 */ + 0x40009000, /* 19 lptim1 */ + 0x4000a000, /* 1A wwdg1 */ + 0x4000b000, /* 1B spi2 */ + 0x4000c000, /* 1C spi3 */ + 0x4000d000, /* 1D spdifrx */ + 0x4000e000, /* 1E usart2 */ + 0x4000f000, /* 1F usart3 */ + 0x40010000, /* 20 uart4 */ + 0x40011000, /* 21 uart5 */ + 0x40012000, /* 22 i2c1 */ + 0x40013000, /* 23 i2c2 */ + 0x40014000, /* 24 i2c3 */ + 0x40015000, /* 25 i2c5 */ + 0x40016000, /* 26 cec */ + 0x40017000, /* 27 dac */ + 0x40018000, /* 28 uart7 */ + 0x40019000, /* 29 uart8 */ + ETZPC_RESERVED, /* 2A reserved */ + ETZPC_RESERVED, /* 2B reserved */ + 0x4001c000, /* 2C mdios */ + ETZPC_RESERVED, /* 2D reserved */ + ETZPC_RESERVED, /* 2E reserved */ + ETZPC_RESERVED, /* 2F reserved */ + 0x44000000, /* 30 tim1 */ + 0x44001000, /* 31 tim8 */ + ETZPC_RESERVED, /* 32 reserved */ + 0x44003000, /* 33 usart6 */ + 0x44004000, /* 34 spi1 */ + 0x44005000, /* 35 spi4 */ + 0x44006000, /* 36 tim15 */ + 0x44007000, /* 37 tim16 */ + 0x44008000, /* 38 tim17 */ + 0x44009000, /* 39 spi5 */ + 0x4400a000, /* 3A sai1 */ + 0x4400b000, /* 3B sai2 */ + 0x4400c000, /* 3C sai3 */ + 0x4400d000, /* 3D dfsdm */ + STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ + ETZPC_RESERVED, /* 3F reserved */ + 0x50021000, /* 40 lptim2 */ + 0x50022000, /* 41 lptim3 */ + 0x50023000, /* 42 lptim4 */ + 0x50024000, /* 43 lptim5 */ + 0x50027000, /* 44 sai4 */ + 0x50025000, /* 45 vrefbuf */ + 0x4c006000, /* 46 dcmi */ + 0x4c004000, /* 47 crc2 */ + 0x48003000, /* 48 adc */ + 0x4c002000, /* 49 hash2 */ + 0x4c003000, /* 4A rng2 */ + STM32MP15_CRYP2_BASE, /* 4B cryp2 */ + ETZPC_RESERVED, /* 4C reserved */ + ETZPC_RESERVED, /* 4D reserved */ + ETZPC_RESERVED, /* 4E reserved */ + ETZPC_RESERVED, /* 4F reserved */ + ETZPC_RESERVED, /* 50 sram1 */ + ETZPC_RESERVED, /* 51 sram2 */ + ETZPC_RESERVED, /* 52 sram3 */ + ETZPC_RESERVED, /* 53 sram4 */ + ETZPC_RESERVED, /* 54 retram */ + 0x49000000, /* 55 otg */ + 0x48004000, /* 56 sdmmc3 */ + 0x48005000, /* 57 dlybsd3 */ + 0x48000000, /* 58 dma1 */ + 0x48001000, /* 59 dma2 */ + 0x48002000, /* 5A dmamux */ + 0x58002000, /* 5B fmc */ + 0x58003000, /* 5C qspi */ + 0x58004000, /* 5D dlybq */ + 0x5800a000, /* 5E eth */ + ETZPC_RESERVED, /* 5F reserved */ +}; + +/* fdt helper */ +static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) +{ + int node; + fdt_addr_t regs; + + for (node = fdt_first_subnode(fdt, offset); + node >= 0; + node = fdt_next_subnode(fdt, node)) { + regs = fdtdec_get_addr(fdt, node, "reg"); + if (addr == regs) { + if (fdtdec_get_is_enabled(fdt, node)) { + fdt_status_disabled(fdt, node); + + return true; + } + return false; + } + } + + return false; +} + +static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) +{ + const u32 *array; + int array_size, i; + int offset, shift; + u32 addr, status, decprot[ETZPC_DECPROT_NB]; + + if (IS_ENABLED(CONFIG_STM32MP13X)) { + array = stm32mp13_ip_addr; + array_size = ARRAY_SIZE(stm32mp13_ip_addr); + } + + if (IS_ENABLED(CONFIG_STM32MP15X)) { + array = stm32mp15_ip_addr; + array_size = ARRAY_SIZE(stm32mp15_ip_addr); + } + + for (i = 0; i < ETZPC_DECPROT_NB; i++) + decprot[i] = readl(ETZPC_DECPROT(i)); + + for (i = 0; i < array_size; i++) { + offset = i / NB_PROT_PER_REG; + shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS; + status = (decprot[offset] >> shift) & DECPROT_MASK; + addr = array[i]; + + log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status); + + if (addr == ETZPC_RESERVED || + status == DECPROT_NON_SECURED) + continue; + + if (fdt_disable_subnode_by_address(fdt, soc_node, addr)) + log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n", + addr, i, status); + } + + return 0; +} + +/* deactivate all the cpu except core 0 */ +static void stm32_fdt_fixup_cpu(void *blob, char *name) +{ + int off; + u32 reg; + + off = fdt_path_offset(blob, "/cpus"); + if (off < 0) { + log_warning("%s: couldn't find /cpus node\n", __func__); + return; + } + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + reg = fdtdec_get_addr(blob, off, "reg"); + if (reg != 0) { + fdt_del_node(blob, off); + log_notice("FDT: cpu %d node remove for %s\n", + reg, name); + /* after delete we can't trust the offsets anymore */ + off = -1; + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } +} + +static void stm32_fdt_disable(void *fdt, int offset, u32 addr, + const char *string, const char *name) +{ + if (fdt_disable_subnode_by_address(fdt, offset, addr)) + log_notice("FDT: %s@%08x node disabled for %s\n", + string, addr, name); +} + +static void stm32_fdt_disable_optee(void *blob) +{ + int off, node; + + /* Delete "optee" firmware node */ + off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz"); + if (off >= 0 && fdtdec_get_is_enabled(blob, off)) + fdt_del_node(blob, off); + + /* Delete "optee@..." reserved-memory node */ + off = fdt_path_offset(blob, "/reserved-memory/"); + if (off < 0) + return; + for (node = fdt_first_subnode(blob, off); + node >= 0; + node = fdt_next_subnode(blob, node)) { + if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6)) + continue; + + if (fdt_del_node(blob, node)) + printf("Failed to remove optee reserved-memory node\n"); + } +} + +static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name) +{ + switch (cpu) { + case CPU_STM32MP131Fxx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Cxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name); + stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name); + fallthrough; + case CPU_STM32MP133Fxx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Cxx: + case CPU_STM32MP133Axx: + stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name); + stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp", + name); + stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name); + break; + default: + break; + } + + switch (cpu) { + case CPU_STM32MP135Dxx: + case CPU_STM32MP135Axx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Axx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name); + break; + default: + break; + } +} + +static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) +{ + u32 pkg; + + switch (cpu) { + case CPU_STM32MP151Fxx: + case CPU_STM32MP151Dxx: + case CPU_STM32MP151Cxx: + case CPU_STM32MP151Axx: + stm32_fdt_fixup_cpu(blob, name); + /* after cpu delete we can't trust the soc offsets anymore */ + soc = fdt_path_offset(blob, "/soc"); + stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name); + fallthrough; + case CPU_STM32MP153Fxx: + case CPU_STM32MP153Dxx: + case CPU_STM32MP153Cxx: + case CPU_STM32MP153Axx: + stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name); + stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name); + break; + default: + break; + } + switch (cpu) { + case CPU_STM32MP157Dxx: + case CPU_STM32MP157Axx: + case CPU_STM32MP153Dxx: + case CPU_STM32MP153Axx: + case CPU_STM32MP151Dxx: + case CPU_STM32MP151Axx: + stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp", + name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp", + name); + break; + default: + break; + } + switch (get_cpu_package()) { + case STM32MP15_PKG_AA_LBGA448: + pkg = STM32MP_PKG_AA; + break; + case STM32MP15_PKG_AB_LBGA354: + pkg = STM32MP_PKG_AB; + break; + case STM32MP15_PKG_AC_TFBGA361: + pkg = STM32MP_PKG_AC; + break; + case STM32MP15_PKG_AD_TFBGA257: + pkg = STM32MP_PKG_AD; + break; + default: + pkg = 0; + break; + } + if (pkg) { + do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl", + "st,package", pkg, false); + do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", + "st,package", pkg, false); + } +} + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + int ret = 0; + int soc; + u32 cpu; + char name[SOC_NAME_SIZE]; + + soc = fdt_path_offset(blob, "/soc"); + /* when absent, nothing to do */ + if (soc == -FDT_ERR_NOTFOUND) + return 0; + if (soc < 0) + return soc; + + if (CONFIG_IS_ENABLED(STM32_ETZPC)) { + ret = stm32_fdt_fixup_etzpc(blob, soc); + if (ret) + return ret; + } + + /* MPUs Part Numbers and name*/ + cpu = get_cpu_type(); + get_soc_name(name); + + if (IS_ENABLED(CONFIG_STM32MP13X)) + stm32mp13_fdt_fixup(blob, soc, cpu, name); + + if (IS_ENABLED(CONFIG_STM32MP15X)) { + stm32mp15_fdt_fixup(blob, soc, cpu, name); + + /* + * TEMP: remove OP-TEE nodes in kernel device tree + * copied from U-Boot device tree by optee_copy_fdt_nodes + * when OP-TEE is not detected (probe failed) + * these OP-TEE nodes are present in <board>-u-boot.dtsi + * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility + * when FIP is not used by TF-A + */ + if (IS_ENABLED(CONFIG_STM32MP15X_STM32IMAGE) && + !tee_find_device(NULL, NULL, NULL, NULL)) + stm32_fdt_disable_optee(blob); + } + + return ret; +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c new file mode 100644 index 00000000000..a02a8988a68 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -0,0 +1,842 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include <config.h> +#include <asm/armv7.h> +#include <asm/cache.h> +#include <asm/gic.h> +#include <asm/io.h> +#include <asm/psci.h> +#include <asm/secure.h> +#include <hang.h> +#include <linux/bitops.h> +#include <linux/errno.h> + +/* PWR */ +#define PWR_CR3 0x0c +#define PWR_MPUCR 0x10 + +#define PWR_CR3_DDRSREN BIT(10) +#define PWR_CR3_DDRRETEN BIT(12) + +#define PWR_MPUCR_PDDS BIT(0) +#define PWR_MPUCR_CSTDBYDIS BIT(3) +#define PWR_MPUCR_CSSF BIT(9) + +/* RCC */ +#define RCC_MSSCKSELR 0x48 +#define RCC_DDRITFCR 0xd8 + +#define RCC_DDRITFCR_DDRC1EN BIT(0) +#define RCC_DDRITFCR_DDRC1LPEN BIT(1) +#define RCC_DDRITFCR_DDRC2EN BIT(2) +#define RCC_DDRITFCR_DDRC2LPEN BIT(3) +#define RCC_DDRITFCR_DDRPHYCEN BIT(4) +#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) +#define RCC_DDRITFCR_DDRCAPBEN BIT(6) +#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) +#define RCC_DDRITFCR_AXIDCGEN BIT(8) +#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_GSKPCTRL BIT(24) + +#define RCC_MP_SREQSETR 0x104 +#define RCC_MP_SREQCLRR 0x108 + +#define RCC_MP_CIER 0x414 +#define RCC_MP_CIFR 0x418 +#define RCC_MP_CIFR_WKUPF BIT(20) + +#define RCC_MCUDIVR 0x830 +#define RCC_PLL3CR 0x880 +#define RCC_PLL4CR 0x894 + +/* SYSCFG */ +#define SYSCFG_CMPCR 0x20 +#define SYSCFG_CMPCR_SW_CTRL BIT(2) +#define SYSCFG_CMPENSETR 0x24 +#define SYSCFG_CMPENCLRR 0x28 +#define SYSCFG_CMPENR_MPUEN BIT(0) + +/* DDR Controller registers offsets */ +#define DDRCTRL_STAT 0x004 +#define DDRCTRL_PWRCTL 0x030 +#define DDRCTRL_PWRTMG 0x034 +#define DDRCTRL_HWLPCTL 0x038 +#define DDRCTRL_DFIMISC 0x1b0 +#define DDRCTRL_SWCTL 0x320 +#define DDRCTRL_SWSTAT 0x324 +#define DDRCTRL_PSTAT 0x3fc +#define DDRCTRL_PCTRL_0 0x490 +#define DDRCTRL_PCTRL_1 0x540 + +/* DDR Controller Register fields */ +#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) +#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 0x1 +#define DDRCTRL_STAT_OPERATING_MODE_SR 0x3 +#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) +#define DDRCTRL_STAT_SELFREF_TYPE_ASR (0x3 << 4) +#define DDRCTRL_STAT_SELFREF_TYPE_SR (0x2 << 4) + +#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) +#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) + +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) + +#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) + +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) + +#define DDRCTRL_SWCTL_SW_DONE BIT(0) + +#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) + +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 BIT(0) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 BIT(1) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 BIT(16) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 BIT(17) + +#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) + +/* DDR PHY registers offsets */ +#define DDRPHYC_PIR 0x004 +#define DDRPHYC_PGSR 0x00c +#define DDRPHYC_ACDLLCR 0x014 +#define DDRPHYC_ACIOCR 0x024 +#define DDRPHYC_DXCCR 0x028 +#define DDRPHYC_DSGCR 0x02c +#define DDRPHYC_ZQ0CR0 0x180 +#define DDRPHYC_DX0DLLCR 0x1cc +#define DDRPHYC_DX1DLLCR 0x20c +#define DDRPHYC_DX2DLLCR 0x24c +#define DDRPHYC_DX3DLLCR 0x28c + +/* DDR PHY Register fields */ +#define DDRPHYC_PIR_INIT BIT(0) +#define DDRPHYC_PIR_DLLSRST BIT(1) +#define DDRPHYC_PIR_DLLLOCK BIT(2) +#define DDRPHYC_PIR_ITMSRST BIT(4) + +#define DDRPHYC_PGSR_IDONE BIT(0) + +#define DDRPHYC_ACDLLCR_DLLSRST BIT(30) +#define DDRPHYC_ACDLLCR_DLLDIS BIT(31) + +#define DDRPHYC_ACIOCR_ACOE BIT(1) +#define DDRPHYC_ACIOCR_ACPDD BIT(3) +#define DDRPHYC_ACIOCR_ACPDR BIT(4) +#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8) +#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8) +#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11) +#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11) +#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(20, 18) +#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18) + +#define DDRPHYC_DXCCR_DXPDD BIT(2) +#define DDRPHYC_DXCCR_DXPDR BIT(3) + +#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16) +#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16) +#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20) +#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20) +#define DDRPHYC_DSGCR_NL2PD BIT(24) +#define DDRPHYC_DSGCR_CKOE BIT(28) + +#define DDRPHYC_ZQ0CRN_ZQPD BIT(31) + +#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) + +#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xca7face0 +#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xca7face1 + +#define MPIDR_AFF0 GENMASK(7, 0) + +#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404) +#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) +#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) + +/* IWDG */ +#define IWDG_KR 0x00 +#define IWDG_KR_RELOAD_KEY 0xaaaa +#define IWDG_EWCR 0x14 +#define IWDG_EWCR_EWIC BIT(14) + +#define STM32MP1_PSCI_NR_CPUS 2 +#if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS +#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" +#endif + +u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = { + PSCI_AFFINITY_LEVEL_ON, + PSCI_AFFINITY_LEVEL_OFF}; + +static u32 __secure_data cntfrq; + +static u32 __secure cp15_read_cntfrq(void) +{ + u32 frq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); + + return frq; +} + +static void __secure cp15_write_cntfrq(u32 frq) +{ + asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq)); +} + +static inline void psci_set_state(int cpu, u8 state) +{ + psci_state[cpu] = state; + dsb(); + isb(); +} + +static u32 __secure stm32mp_get_gicd_base_address(void) +{ + u32 periphbase; + + /* get the GIC base address from the CBAR register */ + asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); + + return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; +} + +static void __secure stm32mp_raise_sgi0(int cpu) +{ + u32 gic_dist_addr; + + gic_dist_addr = stm32mp_get_gicd_base_address(); + + /* ask cpu with SGI0 */ + writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR); +} + +void __secure psci_arch_cpu_entry(void) +{ + u32 cpu = psci_get_cpu_id(); + + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); + + /* write the saved cntfrq */ + cp15_write_cntfrq(cntfrq); + + /* reset magic in TAMP register */ + writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); +} + +s32 __secure psci_features(u32 function_id, u32 psci_fid) +{ + switch (psci_fid) { + case ARM_PSCI_0_2_FN_PSCI_VERSION: + case ARM_PSCI_0_2_FN_CPU_OFF: + case ARM_PSCI_0_2_FN_CPU_ON: + case ARM_PSCI_0_2_FN_AFFINITY_INFO: + case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case ARM_PSCI_0_2_FN_SYSTEM_OFF: + case ARM_PSCI_0_2_FN_SYSTEM_RESET: + case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND: + return 0x0; + } + return ARM_PSCI_RET_NI; +} + +u32 __secure psci_version(void) +{ + return ARM_PSCI_VER_1_0; +} + +s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity, + u32 lowest_affinity_level) +{ + u32 cpu = target_affinity & MPIDR_AFF0; + + if (lowest_affinity_level > 0) + return ARM_PSCI_RET_INVAL; + + if (target_affinity & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (cpu >= STM32MP1_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + return psci_state[cpu]; +} + +u32 __secure psci_migrate_info_type(void) +{ + /* + * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf + * return 2 = Trusted OS is either not present or does not require + * migration, system of this type does not require the caller + * to use the MIGRATE function. + * MIGRATE function calls return NOT_SUPPORTED. + */ + return 2; +} + +s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, + u32 context_id) +{ + u32 cpu = target_cpu & MPIDR_AFF0; + + if (target_cpu & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (cpu >= STM32MP1_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) + return ARM_PSCI_RET_ALREADY_ON; + + /* read and save cntfrq of current cpu to write on target cpu */ + cntfrq = cp15_read_cntfrq(); + + /* reset magic in TAMP register */ + if (readl(TAMP_BACKUP_MAGIC_NUMBER)) + writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); + /* + * ROM code need a first SGI0 after core reset + * core is ready when magic is set to 0 in ROM code + */ + while (readl(TAMP_BACKUP_MAGIC_NUMBER)) + stm32mp_raise_sgi0(cpu); + + /* store target PC and context id*/ + psci_save(cpu, pc, context_id); + + /* write entrypoint in backup RAM register */ + writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS); + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING); + + /* write magic number in backup register */ + if (cpu == 0x01) + writel(BOOT_API_A7_CORE1_MAGIC_NUMBER, + TAMP_BACKUP_MAGIC_NUMBER); + else + writel(BOOT_API_A7_CORE0_MAGIC_NUMBER, + TAMP_BACKUP_MAGIC_NUMBER); + + /* Generate an IT to start the core */ + stm32mp_raise_sgi0(cpu); + + return ARM_PSCI_RET_SUCCESS; +} + +s32 __secure psci_cpu_off(void) +{ + u32 cpu; + + cpu = psci_get_cpu_id(); + + psci_cpu_off_common(); + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); + + /* reset core: wfi is managed by BootRom */ + if (cpu == 0x01) + writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR); + else + writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR); + + /* just waiting reset */ + while (1) + wfi(); +} + +void __secure psci_system_reset(void) +{ + /* System reset */ + writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR); + /* just waiting reset */ + while (1) + wfi(); +} + +void __secure psci_system_off(void) +{ + /* System Off is not managed, waiting user power off + * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF + */ + while (1) + wfi(); +} + +static void __secure secure_udelay(unsigned int delay) +{ + u32 freq = cp15_read_cntfrq() / 1000000; + u64 start, end; + + delay *= freq; + + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); + for (;;) { + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); + if ((end - start) > delay) + break; + } +} + +static int __secure secure_waitbits(u32 reg, u32 mask, u32 val) +{ + u32 freq = cp15_read_cntfrq() / 1000000; + u32 delay = 500 * freq; /* 500 us */ + u64 start, end; + u32 tmp; + + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); + for (;;) { + tmp = readl(reg); + if ((tmp & mask) == val) + return 0; + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); + if ((end - start) > delay) + return -ETIMEDOUT; + } +} + +static void __secure ddr_sr_mode_ssr(u32 *saved_pwrctl) +{ + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, + RCC_DDRITFCR_DDRC1LPEN | RCC_DDRITFCR_DDRC1EN | + RCC_DDRITFCR_DDRC2LPEN | RCC_DDRITFCR_DDRC2EN | + RCC_DDRITFCR_DDRCAPBLPEN | RCC_DDRITFCR_DDRPHYCAPBLPEN | + RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN | + RCC_DDRITFCR_DDRPHYCEN); + + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, + RCC_DDRITFCR_AXIDCGEN | RCC_DDRITFCR_DDRCKMOD_MASK); + + /* Disable HW LP interface of uMCTL2 */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_HWLPCTL, + DDRCTRL_HWLPCTL_HW_LP_EN); + + /* Configure Automatic LP modes of uMCTL2 */ + clrsetbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRTMG, + DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK, + DDRCTRL_PWRTMG_SELFREF_TO_X32_0); + + /* Save PWRCTL register to restart ASR after suspend (if applicable) */ + *saved_pwrctl = readl(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL); + + /* + * Disable Clock disable with LP modes + * (used in RUN mode for LPDDR2 with specific timing). + */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, + DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); + + /* Disable automatic Self-Refresh mode */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, + DDRCTRL_PWRCTL_SELFREF_EN); +} + +static void __secure ddr_sr_mode_restore(u32 saved_pwrctl) +{ + saved_pwrctl &= DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | + DDRCTRL_PWRCTL_SELFREF_EN; + + /* Restore ASR mode in case it was enabled before suspend. */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, saved_pwrctl); +} + +static int __secure ddr_sw_self_refresh_in(void) +{ + int ret; + + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); + + /* Blocks AXI ports from taking anymore transactions */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, + DDRCTRL_PCTRL_N_PORT_EN); + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, + DDRCTRL_PCTRL_N_PORT_EN); + + /* + * Waits unit all AXI ports are idle + * Poll PSTAT.rd_port_busy_n = 0 + * Poll PSTAT.wr_port_busy_n = 0 + */ + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_PSTAT, + DDRCTRL_PSTAT_RD_PORT_BUSY_0 | + DDRCTRL_PSTAT_RD_PORT_BUSY_1 | + DDRCTRL_PSTAT_WR_PORT_BUSY_0 | + DDRCTRL_PSTAT_WR_PORT_BUSY_1, 0); + if (ret) + goto pstat_failed; + + /* SW Self-Refresh entry */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW); + + /* + * Wait operating mode change in self-refresh mode + * with STAT.operating_mode[1:0]==11. + * Ensure transition to self-refresh was due to software + * by checking also that STAT.selfref_type[1:0]=2. + */ + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT, + DDRCTRL_STAT_OPERATING_MODE_MASK | + DDRCTRL_STAT_SELFREF_TYPE_MASK, + DDRCTRL_STAT_OPERATING_MODE_SR | + DDRCTRL_STAT_SELFREF_TYPE_SR); + if (ret) + goto selfref_sw_failed; + + /* IOs powering down (PUBL registers) */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD); + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDR); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, + DDRPHYC_ACIOCR_CKPDD_MASK, + DDRPHYC_ACIOCR_CKPDD_0); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, + DDRPHYC_ACIOCR_CKPDR_MASK, + DDRPHYC_ACIOCR_CKPDR_0); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, + DDRPHYC_ACIOCR_CSPDD_MASK, + DDRPHYC_ACIOCR_CSPDD_0); + + /* Disable command/address output driver */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, + DDRPHYC_DSGCR_ODTPDD_MASK, + DDRPHYC_DSGCR_ODTPDD_0); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, + DDRPHYC_DSGCR_CKEPDD_MASK, + DDRPHYC_DSGCR_CKEPDD_0); + + /* Disable PZQ cell (PUBL register) */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD); + + /* Set latch */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE); + + /* Additional delay to avoid early latch */ + secure_udelay(10); + + /* Activate sw retention in PWRCTRL */ + setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN); + + /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); + + /* Disable all DLLs: GLITCH window */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLDIS); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + /* Switch controller clocks (uMCTL2/PUBL) to DLL output clock */ + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); + + /* Deactivate all DDR clocks */ + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, + RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN | + RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN); + + return 0; + +selfref_sw_failed: + /* This bit should be cleared to restore DDR in its previous state */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, + DDRCTRL_PWRCTL_SELFREF_SW); + +pstat_failed: + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, + DDRCTRL_PCTRL_N_PORT_EN); + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, + DDRCTRL_PCTRL_N_PORT_EN); + + return -EINVAL; +}; + +static void __secure ddr_sw_self_refresh_exit(void) +{ + int ret; + + /* Enable all clocks */ + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, + RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN | + RCC_DDRITFCR_DDRPHYCEN | RCC_DDRITFCR_DDRPHYCAPBEN | + RCC_DDRITFCR_DDRCAPBEN); + + /* Handshake */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); + + /* Mask dfi_init_complete_en */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, + DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + + /* Ack */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT, + DDRCTRL_SWSTAT_SW_DONE_ACK, + DDRCTRL_SWSTAT_SW_DONE_ACK); + if (ret) + hang(); + + /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); + + /* Enable all DLLs: GLITCH window */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, + DDRPHYC_ACDLLCR_DLLDIS); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + /* Additional delay to avoid early DLL clock switch */ + secure_udelay(50); + + /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST); + + secure_udelay(10); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST); + + /* PHY partial init: (DLL lock and ITM reset) */ + writel(DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | + DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_INIT, + STM32_DDRPHYC_BASE + DDRPHYC_PIR); + + /* Need to wait at least 10 clock cycles before accessing PGSR */ + secure_udelay(1); + + /* Pool end of init */ + ret = secure_waitbits(STM32_DDRPHYC_BASE + DDRPHYC_PGSR, + DDRPHYC_PGSR_IDONE, DDRPHYC_PGSR_IDONE); + if (ret) + hang(); + + /* Handshake */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); + + /* Unmask dfi_init_complete_en to uMCTL2 */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + + /* Ack */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT, + DDRCTRL_SWSTAT_SW_DONE_ACK, + DDRCTRL_SWSTAT_SW_DONE_ACK); + if (ret) + hang(); + + /* Deactivate sw retention in PWR */ + clrbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN); + + /* Enable PZQ cell (PUBL register) */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD); + + /* Enable pad drivers */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD); + + /* Enable command/address output driver */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CKPDD_MASK); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CSPDD_MASK); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR); + + /* Release latch */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_ODTPDD_MASK); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKEPDD_MASK); + + /* Remove selfrefresh */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW); + + /* Wait operating_mode == normal */ + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT, + DDRCTRL_STAT_OPERATING_MODE_MASK, + DDRCTRL_STAT_OPERATING_MODE_NORMAL); + if (ret) + hang(); + + /* AXI ports are no longer blocked from taking transactions */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, DDRCTRL_PCTRL_N_PORT_EN); + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, DDRCTRL_PCTRL_N_PORT_EN); + + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); +} + +void __secure psci_system_suspend(u32 __always_unused function_id, + u32 ep, u32 context_id) +{ + u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; + u32 gicd_addr = stm32mp_get_gicd_base_address(); + u32 cpu = psci_get_cpu_id(); + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); + bool iwdg1_wake = false; + bool iwdg2_wake = false; + bool other_wake = false; + u32 saved_pwrctl, reg; + u32 gic_enabled[8]; + u32 irqs; + int i; + + /* Cache enable mask of all 256 SPI */ + for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) + gic_enabled[i] = readl(gicd_addr + GICD_ISENABLERn + 0x4 + 4 * i); + + /* Disable IO compensation */ + + /* Place current APSRC/ANSRC into RAPSRC/RANSRC */ + reg = readl(STM32_SYSCFG_BASE + SYSCFG_CMPCR); + reg >>= 8; + reg &= 0xff << 16; + reg |= SYSCFG_CMPCR_SW_CTRL; + writel(reg, STM32_SYSCFG_BASE + SYSCFG_CMPCR); + writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENCLRR); + + writel(RCC_MP_CIFR_WKUPF, STM32_RCC_BASE + RCC_MP_CIFR); + setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); + + setbits_le32(STM32_PWR_BASE + PWR_MPUCR, + PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS); + + saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); + saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); + saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR); + saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR); + + psci_v7_flush_dcache_all(); + ddr_sr_mode_ssr(&saved_pwrctl); + ddr_sw_self_refresh_in(); + setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN); + writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR); + + /* Ping the IWDG before entering suspend */ + iwdg1_wake = !!(gic_enabled[4] & BIT(22)); /* SPI 150 */ + iwdg2_wake = !!(gic_enabled[4] & BIT(23)); /* SPI 151 */ + + for (;;) { + /* Ping IWDG1 and ACK pretimer IRQ */ + if (iwdg1_wake) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (iwdg2_wake) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + + iwdg1_wake = false; + iwdg2_wake = false; + + /* Zzz, enter stop mode */ + asm volatile( + "isb\n" + "dsb\n" + "wfi\n"); + + /* Determine the wake up source */ + for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) { + irqs = readl(gicd_addr + GICR_IGROUPMODRn + 0x4 + 4 * i); + irqs &= gic_enabled[i]; + if (!irqs) + continue; + + /* Test whether IWDG pretimeout triggered the wake up. */ + if (i == 4) { /* SPI Num 128..159 */ + iwdg1_wake = !!(irqs & BIT(22)); /* SPI 150 */ + iwdg2_wake = !!(irqs & BIT(23)); /* SPI 151 */ + irqs &= ~(BIT(22) | BIT(23)); + } + + /* Test whether there is any other wake up trigger. */ + if (irqs) { + other_wake = true; + break; + } + } + + /* Other wake up triggers pending, let OS deal with all of it. */ + if (other_wake) + break; + } + + writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR); + ddr_sw_self_refresh_exit(); + ddr_sr_mode_restore(saved_pwrctl); + + writel(saved_mcudivr, STM32_RCC_BASE + RCC_MCUDIVR); + writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR); + writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR); + writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR); + + writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); + clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + + /* + * Make sure the OS would not get any spurious IWDG pretimeout IRQ + * right after the system wakes up. This may happen in case the SoC + * got woken up by another source than the IWDG pretimeout and the + * pretimeout IRQ arrived immediately afterward, but too late to be + * handled by the main loop above. In case either of the IWDG is + * enabled, ping it first and then return to the OS. + */ + + /* Ping IWDG1 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(22)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (gic_enabled[4] & BIT(23)) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + + /* + * The system has resumed successfully. Rewrite LR register stored + * on stack with 'ep' value, so that on return from this PSCI call, + * the code would jump to that 'ep' resume entry point code path + * instead of the previous 'lr' register content which (e.g. with + * Linux) points to resume failure code path. + * + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. + */ + writel(ep, sp - 8); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c new file mode 100644 index 00000000000..79c44188cc5 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_REGULATOR + +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <time.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <power/pmic.h> +#include <power/regulator.h> + +#define STM32MP_PWR_CR3 0xc +#define STM32MP_PWR_CR3_USB33DEN BIT(24) +#define STM32MP_PWR_CR3_USB33RDY BIT(26) +#define STM32MP_PWR_CR3_REG18DEN BIT(28) +#define STM32MP_PWR_CR3_REG18RDY BIT(29) +#define STM32MP_PWR_CR3_REG11DEN BIT(30) +#define STM32MP_PWR_CR3_REG11RDY BIT(31) + +struct stm32mp_pwr_reg_info { + u32 enable; + u32 ready; + char *name; +}; + +struct stm32mp_pwr_priv { + fdt_addr_t base; +}; + +static int stm32mp_pwr_write(struct udevice *dev, uint reg, + const uint8_t *buff, int len) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + u32 val = *(u32 *)buff; + + if (len != 4) + return -EINVAL; + + writel(val, priv->base + STM32MP_PWR_CR3); + + return 0; +} + +static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff, + int len) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + + if (len != 4) + return -EINVAL; + + *(u32 *)buff = readl(priv->base + STM32MP_PWR_CR3); + + return 0; +} + +static int stm32mp_pwr_of_to_plat(struct udevice *dev) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct pmic_child_info pwr_children_info[] = { + { .prefix = "reg", .driver = "stm32mp_pwr_regulator"}, + { .prefix = "usb", .driver = "stm32mp_pwr_regulator"}, + { }, +}; + +static int stm32mp_pwr_bind(struct udevice *dev) +{ + int children; + + children = pmic_bind_children(dev, dev_ofnode(dev), pwr_children_info); + if (!children) + dev_dbg(dev, "no child found\n"); + + return 0; +} + +static struct dm_pmic_ops stm32mp_pwr_ops = { + .read = stm32mp_pwr_read, + .write = stm32mp_pwr_write, +}; + +static const struct udevice_id stm32mp_pwr_ids[] = { + { .compatible = "st,stm32mp1,pwr-reg" }, + { } +}; + +U_BOOT_DRIVER(stm32mp_pwr_pmic) = { + .name = "stm32mp_pwr_pmic", + .id = UCLASS_PMIC, + .of_match = stm32mp_pwr_ids, + .bind = stm32mp_pwr_bind, + .ops = &stm32mp_pwr_ops, + .of_to_plat = stm32mp_pwr_of_to_plat, + .priv_auto = sizeof(struct stm32mp_pwr_priv), +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = { + .enable = STM32MP_PWR_CR3_REG11DEN, + .ready = STM32MP_PWR_CR3_REG11RDY, + .name = "reg11" +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg18 = { + .enable = STM32MP_PWR_CR3_REG18DEN, + .ready = STM32MP_PWR_CR3_REG18RDY, + .name = "reg18" +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_usb33 = { + .enable = STM32MP_PWR_CR3_USB33DEN, + .ready = STM32MP_PWR_CR3_USB33RDY, + .name = "usb33" +}; + +static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = { + &stm32mp_pwr_reg11, + &stm32mp_pwr_reg18, + &stm32mp_pwr_usb33, + NULL +}; + +static int stm32mp_pwr_regulator_probe(struct udevice *dev) +{ + const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos; + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + + while (*p) { + int rc; + + rc = dev_read_stringlist_search(dev, "regulator-name", + (*p)->name); + if (rc >= 0) { + dev_dbg(dev, "found regulator %s\n", (*p)->name); + break; + } else if (rc != -ENODATA) { + return rc; + } + p++; + } + if (!*p) { + int i = 0; + const char *s; + + dev_dbg(dev, "regulator "); + while (dev_read_string_index(dev, "regulator-name", + i++, &s) >= 0) + dev_dbg(dev, "%s'%s' ", (i > 1) ? ", " : "", s); + dev_dbg(dev, "%s not supported\n", (i > 2) ? "are" : "is"); + return -EINVAL; + } + + uc_pdata->type = REGULATOR_TYPE_FIXED; + dev_set_priv(dev, (void *)*p); + + return 0; +} + +static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + if (!uc_pdata) + return -ENXIO; + + if (uc_pdata->min_uV != uV) { + dev_dbg(dev, "Invalid uV=%d for: %s\n", uV, uc_pdata->name); + return -EINVAL; + } + + return 0; +} + +static int stm32mp_pwr_regulator_get_value(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + if (!uc_pdata) + return -ENXIO; + + if (uc_pdata->min_uV != uc_pdata->max_uV) { + dev_dbg(dev, "Invalid constraints for: %s\n", uc_pdata->name); + return -EINVAL; + } + + return uc_pdata->min_uV; +} + +static int stm32mp_pwr_regulator_get_enable(struct udevice *dev) +{ + const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev); + int rc; + u32 reg; + + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + dev_dbg(dev, "%s id %s\n", p->name, (reg & p->enable) ? "on" : "off"); + + return (reg & p->enable) != 0; +} + +static int stm32mp_pwr_regulator_set_enable(struct udevice *dev, bool enable) +{ + const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev); + int rc; + u32 reg; + u32 time_start; + + dev_dbg(dev, "Turning %s %s\n", enable ? "on" : "off", p->name); + + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + /* if regulator is already in the wanted state, nothing to do */ + if (!!(reg & p->enable) == enable) + return 0; + + reg &= ~p->enable; + if (enable) + reg |= p->enable; + + rc = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + if (!enable) + return 0; + + /* waiting ready for enable */ + time_start = get_timer(0); + while (1) { + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + if (reg & p->ready) + break; + if (get_timer(time_start) > CONFIG_SYS_HZ) { + dev_dbg(dev, "%s: timeout\n", p->name); + return -ETIMEDOUT; + } + } + return 0; +} + +static const struct dm_regulator_ops stm32mp_pwr_regulator_ops = { + .set_value = stm32mp_pwr_regulator_set_value, + .get_value = stm32mp_pwr_regulator_get_value, + .get_enable = stm32mp_pwr_regulator_get_enable, + .set_enable = stm32mp_pwr_regulator_set_enable, +}; + +U_BOOT_DRIVER(stm32mp_pwr_regulator) = { + .name = "stm32mp_pwr_regulator", + .id = UCLASS_REGULATOR, + .ops = &stm32mp_pwr_regulator_ops, + .probe = stm32mp_pwr_regulator_probe, +}; diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c new file mode 100644 index 00000000000..9c4fafbf478 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <config.h> +#include <cpu_func.h> +#include <dm.h> +#include <hang.h> +#include <init.h> +#include <log.h> +#include <ram.h> +#include <spl.h> +#include <asm/cache.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <mach/tzc.h> +#include <mach/stm32mp.h> +#include <linux/libfdt.h> + +u32 spl_boot_device(void) +{ + u32 boot_mode; + + boot_mode = get_bootmode(); + + switch (boot_mode) { + case BOOT_FLASH_SD_1: + case BOOT_FLASH_EMMC_1: + return BOOT_DEVICE_MMC1; + case BOOT_FLASH_SD_2: + case BOOT_FLASH_EMMC_2: + return BOOT_DEVICE_MMC2; + case BOOT_SERIAL_UART_1: + case BOOT_SERIAL_UART_2: + case BOOT_SERIAL_UART_3: + case BOOT_SERIAL_UART_4: + case BOOT_SERIAL_UART_5: + case BOOT_SERIAL_UART_6: + case BOOT_SERIAL_UART_7: + case BOOT_SERIAL_UART_8: + return BOOT_DEVICE_UART; + case BOOT_SERIAL_USB_OTG: + return BOOT_DEVICE_DFU; + case BOOT_FLASH_NAND_FMC: + return BOOT_DEVICE_NAND; + case BOOT_FLASH_NOR_QSPI: + return BOOT_DEVICE_SPI; + case BOOT_FLASH_SPINAND_1: + return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */ + } + + return BOOT_DEVICE_MMC1; +} + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION +int spl_mmc_boot_partition(const u32 boot_device) +{ + switch (boot_device) { + case BOOT_DEVICE_MMC1: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION; + case BOOT_DEVICE_MMC2: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2; + default: + return -EINVAL; + } +} +#endif + +#ifdef CONFIG_SPL_DISPLAY_PRINT +void spl_display_print(void) +{ + DECLARE_GLOBAL_DATA_PTR; + const char *model; + + /* same code than show_board_info() but not compiled for SPL + * see CONFIG_DISPLAY_BOARDINFO & common/board_info.c + */ + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (model) + log_info("Model: %s\n", model); +} +#endif + +__weak int board_early_init_f(void) +{ + return 0; +} + +uint32_t stm32mp_get_dram_size(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + if (uclass_get_device(UCLASS_RAM, 0, &dev)) + return 0; + + ret = ram_get_info(dev, &ram); + if (ret) + return 0; + + return ram.size; +} + +#define CFG_SHMEM_SIZE 0x200000 +#define STM32_TZC_NSID_ALL 0xffff +#define STM32_TZC_FILTER_ALL 3 + +void stm32_init_tzc_for_optee(void) +{ + const uint32_t dram_size = stm32mp_get_dram_size(); + const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1); + u32 optee_base = 0, optee_size = 0, tee_shmem_base; + const uintptr_t tzc = STM32_TZC_BASE; + int ret; + + if (dram_size == 0) + panic("Cannot determine DRAM size from devicetree\n"); + + ret = optee_get_reserved_memory(&optee_base, &optee_size); + if (ret < 0 || optee_size <= CFG_SHMEM_SIZE) + panic("Invalid OPTEE reserved memory in devicetree\n"); + + tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE; + + const struct tzc_region optee_config[] = { + { + .base = STM32_DDR_BASE, + .top = optee_base - 1, + .sec_mode = TZC_ATTR_SEC_NONE, + .nsec_id = STM32_TZC_NSID_ALL, + .filters_mask = STM32_TZC_FILTER_ALL, + }, { + .base = optee_base, + .top = tee_shmem_base - 1, + .sec_mode = TZC_ATTR_SEC_RW, + .nsec_id = 0, + .filters_mask = STM32_TZC_FILTER_ALL, + }, { + .base = tee_shmem_base, + .top = dram_top, + .sec_mode = TZC_ATTR_SEC_NONE, + .nsec_id = STM32_TZC_NSID_ALL, + .filters_mask = STM32_TZC_FILTER_ALL, + }, { + .top = 0, + } + }; + + flush_dcache_all(); + + tzc_configure(tzc, optee_config); + tzc_dump_config(tzc); + + dcache_disable(); +} + +void spl_board_prepare_for_optee(void *fdt) +{ + stm32_init_tzc_for_optee(); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + arch_cpu_init(); + mach_cpu_init(); + + ret = spl_early_init(); + if (ret) { + log_debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + log_debug("Clock init failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) { + log_debug("Reset init failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev); + if (ret) { + log_debug("%s: Cannot find pinctrl device\n", __func__); + hang(); + } + + /* enable console uart printing */ + preloader_console_init(); + + ret = board_early_init_f(); + if (ret) { + log_debug("board_early_init_f() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + log_err("DRAM init failed: %d\n", ret); + hang(); + } + + /* + * activate cache on DDR only when DDR is fully initialized + * to avoid speculative access and issue in get_ram_size() + */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, + DCACHE_DEFAULT_OPTION); +} + +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +} + +void spl_board_prepare_for_linux(void) +{ + dcache_disable(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c new file mode 100644 index 00000000000..4a811065fc3 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <config.h> +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* SYSCFG register */ +#define SYSCFG_IDC_OFFSET 0x380 +#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_IDC_DEV_ID_SHIFT 0 +#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_IDC_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(11, 0) + +static u32 read_idc(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_IDC_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +static u32 get_cpu_rpn(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +u32 get_cpu_type(void) +{ + return (get_cpu_dev() << 16) | get_cpu_rpn(); +} + +int get_eth_nb(void) +{ + int nb_eth = 2; + + switch (get_cpu_type()) { + case CPU_STM32MP131Dxx: + fallthrough; + case CPU_STM32MP131Cxx: + fallthrough; + case CPU_STM32MP131Axx: + nb_eth = 1; + break; + default: + nb_eth = 2; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r; + + /* MPUs Part Numbers */ + switch (get_cpu_type()) { + case CPU_STM32MP135Fxx: + cpu_s = "135F"; + break; + case CPU_STM32MP135Dxx: + cpu_s = "135D"; + break; + case CPU_STM32MP135Cxx: + cpu_s = "135C"; + break; + case CPU_STM32MP135Axx: + cpu_s = "135A"; + break; + case CPU_STM32MP133Fxx: + cpu_s = "133F"; + break; + case CPU_STM32MP133Dxx: + cpu_s = "133D"; + break; + case CPU_STM32MP133Cxx: + cpu_s = "133C"; + break; + case CPU_STM32MP133Axx: + cpu_s = "133A"; + break; + case CPU_STM32MP131Fxx: + cpu_s = "131F"; + break; + case CPU_STM32MP131Dxx: + cpu_s = "131D"; + break; + case CPU_STM32MP131Cxx: + cpu_s = "131C"; + break; + case CPU_STM32MP131Axx: + cpu_s = "131A"; + break; + default: + cpu_s = "????"; + break; + } + + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + case CPU_REV1_1: + cpu_r = "Z"; + break; + case CPU_REV1_2: + cpu_r = "Y"; + break; + default: + cpu_r = "?"; + break; + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c new file mode 100644 index 00000000000..4f1d783649b --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <env.h> +#include <log.h> +#include <asm/io.h> +#include <asm/arch/bsec.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <linux/bitfield.h> + +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_BDCR (STM32_RCC_BASE + 0x0140) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) +#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) + +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) + +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +/* Security register */ +#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) +#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) + +#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) +#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) +#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) + +#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) +#define TAMP_SMCR (STM32_TAMP_BASE + 0x20) +#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0) +#define TAMP_SMCR_BKPWDPROT GENMASK(23, 16) + +#define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_MCUCR (STM32_PWR_BASE + 0x14) +#define PWR_CR1_DBP BIT(8) +#define PWR_MCUCR_SBF BIT(6) + +/* GPIOZ registers */ +#define GPIOZ_SECCFGR 0x54004030 + +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 + +/* boot interface from Bootrom + * - boot instance = bit 31:16 + * - boot device = bit 15:0 + */ +#define BOOTROM_PARAM_ADDR 0x2FFC0078 +#define BOOTROM_MODE_MASK GENMASK(15, 0) +#define BOOTROM_MODE_SHIFT 0 +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_SHIFT 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(7, 0) + +/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines + * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm + * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm + * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm + * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 27 +#define PKG_MASK GENMASK(2, 0) + +static void security_init(void) +{ + /* Disable the backup domain write protection */ + /* the protection is enable at each reset by hardware */ + /* And must be disable by software */ + setbits_le32(PWR_CR1, PWR_CR1_DBP); + + while (!(readl(PWR_CR1) & PWR_CR1_DBP)) + ; + + /* If RTC clock isn't enable so this is a cold boot then we need + * to reset the backup domain + */ + if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { + setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) + ; + clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + } + + /* allow non secure access in Write/Read for all peripheral */ + writel(GENMASK(25, 0), ETZPC_DECPROT0); + + /* Open SYSRAM for no secure access */ + writel(0x0, ETZPC_TZMA1_SIZE); + + /* enable TZC1 TZC2 clock */ + writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); + + /* Region 0 set to no access by default */ + /* bit 0 / 16 => nsaid0 read/write Enable + * bit 1 / 17 => nsaid1 read/write Enable + * ... + * bit 15 / 31 => nsaid15 read/write Enable + */ + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); + /* bit 30 / 31 => Secure Global Enable : write/read */ + /* bit 0 / 1 => Region Enable for filter 0/1 */ + writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); + + /* Enable Filter 0 and 1 */ + setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); + + /* RCC trust zone deactivated */ + writel(0x0, RCC_TZCR); + + /* TAMP: deactivate the internal tamper + * Bit 23 ITAMP8E: monotonic counter overflow + * Bit 20 ITAMP5E: RTC calendar overflow + * Bit 19 ITAMP4E: HSE monitoring + * Bit 18 ITAMP3E: LSE monitoring + * Bit 16 ITAMP1E: RTC power domain supply monitoring + */ + writel(0x0, TAMP_CR1); + + /* + * TAMP: Configure non-zero secure protection settings. This is + * checked by BootROM function 35ac on OTP-CLOSED device during + * CPU core 1 release from endless loop. If secure protection + * fields are zero, the core 1 is not released from endless + * loop on second SGI0. + */ + clrsetbits_le32(TAMP_SMCR, + TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT, + FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x0A) | + FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x0F)); + + /* GPIOZ: deactivate the security */ + writel(BIT(0), RCC_MP_AHB5ENSETR); + writel(0x0, GPIOZ_SECCFGR); +} + +/* + * Debug init + */ +void dbgmcu_init(void) +{ + /* + * Freeze IWDG2 if Cortex-A7 is in debug mode + * done in TF-A for TRUSTED boot and + * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE + */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + int ret; + + dbgmcu_init(); + + /* force probe of BSEC driver to shadow the upper OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret) + log_warning("BSEC probe failed: %d\n", ret); +} + +/* get bootmode from ROM code boot context: saved in TAMP register */ +static void update_bootmode(void) +{ + u32 boot_mode; + u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); + u32 bootrom_device, bootrom_instance; + + /* enable TAMP clock = RTCAPBEN */ + writel(BIT(8), RCC_MP_APB5ENSETR); + + /* read bootrom context */ + bootrom_device = + (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; + bootrom_instance = + (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; + boot_mode = + ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | + ((bootrom_instance << BOOT_INSTANCE_SHIFT) & + BOOT_INSTANCE_MASK); + + /* save the boot mode in TAMP backup register */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); +} + +/* weak function: STM32MP15x mach init for boot without TFA */ +void stm32mp_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_XPL_BUILD)) { + security_init(); + update_bootmode(); + } + + /* reset copro state in SPL, when used, or in U-Boot */ + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_XPL_BUILD)) { + /* Reset Coprocessor state unless it wakes up from Standby power mode */ + if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { + writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); + writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); + } + } +} + +static u32 read_idc(void) +{ + /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + + return readl(DBGMCU_IDC); + } + + return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ +} + +u32 get_cpu_dev(void) +{ + return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +static u32 get_cpu_rpn(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +u32 get_cpu_type(void) +{ + return (get_cpu_dev() << 16) | get_cpu_rpn(); +} + +int get_eth_nb(void) +{ + return 1; +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +static const char * const soc_type[] = { + "????", + "151C", "151A", "151F", "151D", + "153C", "153A", "153F", "153D", + "157C", "157A", "157F", "157D" +}; + +static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; +static const char * const soc_rev[] = { "?", "A", "B", "Z", "Y"}; + +static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, + unsigned int *rev) +{ + u32 cpu_type = get_cpu_type(); + u32 ct = cpu_type & ~(BIT(7) | BIT(0)); + u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); + + /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ + switch (ct) { + case CPU_STM32MP151Cxx: + *type = cm + 1; + break; + case CPU_STM32MP153Cxx: + *type = cm + 5; + break; + case CPU_STM32MP157Cxx: + *type = cm + 9; + break; + default: + *type = 0; + break; + } + + /* Package */ + *pkg = get_cpu_package(); + if (*pkg > STM32MP15_PKG_AA_LBGA448) + *pkg = STM32MP15_PKG_UNKNOWN; + + /* Revision */ + switch (get_cpu_rev()) { + case CPU_REV1: + *rev = 1; + break; + case CPU_REV2: + *rev = 2; + break; + case CPU_REV2_1: + *rev = 3; + break; + case CPU_REV2_2: + *rev = 4; + break; + default: + *rev = 0; + break; + } +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + if (bsec_dbgswenable()) { + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); + } else { + /* + * SoC revision is only accessible via DBUMCU IDC register, + * which requires BSEC.DENABLE DBGSWENABLE bit to be set to + * make the register accessible, otherwise an access to the + * register triggers bus fault. As BSEC.DBGSWENABLE is zero + * in case of an OTP-CLOSED system, do NOT set DBGSWENABLE + * bit as this might open a brief window for timing attacks. + * Instead, report that this system is OTP-CLOSED and do not + * report any SoC revision to avoid confusing users. + */ + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C", + soc_type[type], soc_pkg[pkg]); + } +} + +static void setup_soc_type_pkg_rev(void) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + env_set("soc_type", soc_type[type]); + env_set("soc_pkg", soc_pkg[pkg]); + env_set("soc_rev", soc_rev[rev]); +} + +/* weak function called in arch_misc_init */ +void stm32mp_misc_init(void) +{ + setup_soc_type_pkg_rev(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/tzc400.c b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c new file mode 100644 index 00000000000..cdc4a40edaf --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Simple API for configuring TrustZone memory restrictions for TZC400 + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <linux/iopoll.h> +#include <mach/tzc.h> + +#define TZC_TIMEOUT_US 100 + +#define TZC_BUILD_CONFIG 0x00 +#define TZC_ACTION 0x04 +#define TZC_ACTION_NONE 0 +#define TZC_ACTION_ERR 1 +#define TZC_ACTION_INT 2 +#define TZC_ACTION_INT_ERR 3 +#define TZC_GATE_KEEPER 0x08 + +#define TZC_REGION0_OFFSET 0x100 +#define TZC_REGION_CFG_SIZE 0x20 +#define TZC_REGION1_OFFSET 0x120 +#define TZC_REGION_BASE 0x00 +#define TZC_REGION_TOP 0x08 +#define TZC_REGION_ATTRIBUTE 0x10 +#define TZC_REGION_ACCESS 0x14 + +static uint32_t tzc_read(uintptr_t tzc, size_t reg) +{ + return readl(tzc + reg); +} + +static void tzc_write(uintptr_t tzc, size_t reg, uint32_t val) +{ + writel(val, tzc + reg); +} + +static uint16_t tzc_config_get_active_filters(const struct tzc_region *cfg) +{ + uint16_t active_filters = 0; + + for ( ; cfg->top != 0; cfg++) + active_filters |= cfg->filters_mask; + + return active_filters; +} + +int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg) +{ + uintptr_t region = tzc + TZC_REGION1_OFFSET; + uint32_t nsid, attr_reg, active_filters; + int ret; + + active_filters = tzc_config_get_active_filters(cfg); + if (active_filters == 0) + return -EINVAL; + + ret = tzc_disable_filters(tzc, active_filters); + if (ret < 0) + return ret; + + for ( ; cfg->top != 0; cfg++, region += TZC_REGION_CFG_SIZE) { + attr_reg = (cfg->sec_mode & 0x03) << 30; + attr_reg |= (cfg->filters_mask & 0x03) << 0; + nsid = cfg->nsec_id & 0xffff; + nsid |= nsid << 16; + + tzc_write(region, TZC_REGION_BASE, cfg->base); + tzc_write(region, TZC_REGION_TOP, cfg->top); + tzc_write(region, TZC_REGION_ACCESS, nsid); + tzc_write(region, TZC_REGION_ATTRIBUTE, attr_reg); + } + + tzc_write(tzc, TZC_ACTION, TZC_ACTION_ERR); + return tzc_enable_filters(tzc, active_filters); +} + +int tzc_disable_filters(uintptr_t tzc, uint16_t filters_mask) +{ + uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER); + uint32_t filter_status = filters_mask << 16; + + gate &= ~filters_mask; + tzc_write(tzc, TZC_GATE_KEEPER, gate); + + return readl_poll_timeout(tzc + TZC_GATE_KEEPER, gate, + (gate & filter_status) == 0, TZC_TIMEOUT_US); +} + +int tzc_enable_filters(uintptr_t tzc, uint16_t filters_mask) +{ + uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER); + uint32_t filter_status = filters_mask << 16; + + gate |= filters_mask; + tzc_write(tzc, TZC_GATE_KEEPER, gate); + + return readl_poll_timeout(tzc + TZC_GATE_KEEPER, gate, + (gate & filter_status) == filter_status, + TZC_TIMEOUT_US); +} + +static const char *sec_access_str_from_attr(uint32_t attr) +{ + const char *const sec_mode[] = { "none", "RO ", "WO ", "RW " }; + + return sec_mode[(attr >> 30) & 0x03]; +} + +void tzc_dump_config(uintptr_t tzc) +{ + uint32_t build_config, base, top, attr, nsaid; + int num_regions, i; + uintptr_t region; + + build_config = tzc_read(tzc, TZC_BUILD_CONFIG); + num_regions = ((build_config >> 0) & 0x1f) + 1; + + for (i = 0; i < num_regions; i++) { + region = tzc + TZC_REGION0_OFFSET + i * TZC_REGION_CFG_SIZE; + + base = tzc_read(region, TZC_REGION_BASE); + top = tzc_read(region, TZC_REGION_TOP); + attr = tzc_read(region, TZC_REGION_ATTRIBUTE); + nsaid = tzc_read(region, TZC_REGION_ACCESS); + + if (attr == 0 && nsaid == 0) + continue; + + log_info("TZC region %u: %08x->%08x - filters 0x%x\n", + i, base, top, (attr >> 0) & 0xf); + log_info("\t Secure access %s NSAID %08x\n", + sec_access_str_from_attr(attr), nsaid); + } +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile new file mode 100644 index 00000000000..b579ce5a800 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +# +# Copyright (C) 2023, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o +obj-y += arm64-mmu.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c new file mode 100644 index 00000000000..36c631ef0c2 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <asm/system.h> +#include <asm/armv8/mmu.h> +#include <mach/stm32.h> + +#define MP2_MEM_MAP_MAX 10 + +#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \ + (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE)) +#error "invalid CONFIG_TEXT_BASE value" +#endif + +struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = { + { + /* PCIe */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Peripherals: alias1 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OSPI and FMC: memory-map area */ + .virt = 0x60000000UL, + .phys = 0x60000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* + * DDR = STM32_DDR_BASE / STM32_DDR_SIZE + * the beginning of DDR (before CONFIG_TEXT_BASE) is not + * mapped, protected by RIF and reserved for other firmware + * (OP-TEE / TF-M / Cube M33) + */ + .virt = CONFIG_TEXT_BASE, + .phys = CONFIG_TEXT_BASE, + .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE), + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = stm32mp2_mem_map; diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c new file mode 100644 index 00000000000..9530aa8534b --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <clk.h> +#include <cpu_func.h> +#include <debug_uart.h> +#include <env_internal.h> +#include <init.h> +#include <misc.h> +#include <wdt.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <asm/system.h> +#include <dm/device.h> +#include <dm/lists.h> +#include <dm/uclass.h> + +/* + * early TLB into the .data section so that it not get cleared + * with 16kB alignment + */ +#define EARLY_TLB_SIZE 0xA000 +u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); + +/* + * initialize the MMU and activate cache in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + */ +static void early_enable_caches(void) +{ + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { + gd->arch.tlb_size = EARLY_TLB_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + } + /* enable MMU (default configuration) */ + dcache_enable(); +} + +/* + * Early system init + */ +int arch_cpu_init(void) +{ + icache_enable(); + early_enable_caches(); + + return 0; +} + +void enable_caches(void) +{ + /* deactivate the data cache, early enabled in arch_cpu_init() */ + dcache_disable(); + /* + * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr + * to update the TLB location udpated in board_f.c::reserve_mmu + */ + gd->arch.tlb_fillptr = 0; + dcache_enable(); +} + +int arch_misc_init(void) +{ + setup_serial_number(); + setup_mac_address(); + + return 0; +} + +/* + * Force data-section, as .bss will not be valid + * when save_boot_params is invoked. + */ +static uintptr_t nt_fw_dtb __section(".data"); + +uintptr_t get_stm32mp_bl2_dtb(void) +{ + return nt_fw_dtb; +} + +/* + * Save the FDT address provided by TF-A in r2 at boot time + * This function is called from start.S + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + nt_fw_dtb = r2; + + save_boot_params_ret(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/fdt.c b/arch/arm/mach-stm32mp/stm32mp2/fdt.c new file mode 100644 index 00000000000..31b127b465a --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/fdt.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <asm/u-boot.h> + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c new file mode 100644 index 00000000000..7f896a0d65d --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* SYSCFG register */ +#define SYSCFG_DEVICEID_OFFSET 0x6400 +#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 +#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_DEVICEID_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP9 */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(31, 0) + +/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines + * - 000: Custom package + * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 0 +#define PKG_MASK GENMASK(2, 0) + +static u32 read_deviceid(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +u32 get_cpu_type(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +int get_eth_nb(void) +{ + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + fallthrough; + case CPU_STM32MP257Dxx: + fallthrough; + case CPU_STM32MP257Cxx: + fallthrough; + case CPU_STM32MP257Axx: + nb_eth = 5; /* dual ETH with TSN support */ + break; + case CPU_STM32MP253Fxx: + fallthrough; + case CPU_STM32MP253Dxx: + fallthrough; + case CPU_STM32MP253Cxx: + fallthrough; + case CPU_STM32MP253Axx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP251Fxx: + fallthrough; + case CPU_STM32MP251Dxx: + fallthrough; + case CPU_STM32MP251Cxx: + fallthrough; + case CPU_STM32MP251Axx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP25) { + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + cpu_s = "257F"; + break; + case CPU_STM32MP257Dxx: + cpu_s = "257D"; + break; + case CPU_STM32MP257Cxx: + cpu_s = "257C"; + break; + case CPU_STM32MP257Axx: + cpu_s = "257A"; + break; + case CPU_STM32MP255Fxx: + cpu_s = "255F"; + break; + case CPU_STM32MP255Dxx: + cpu_s = "255D"; + break; + case CPU_STM32MP255Cxx: + cpu_s = "255C"; + break; + case CPU_STM32MP255Axx: + cpu_s = "255A"; + break; + case CPU_STM32MP253Fxx: + cpu_s = "253F"; + break; + case CPU_STM32MP253Dxx: + cpu_s = "253D"; + break; + case CPU_STM32MP253Cxx: + cpu_s = "253C"; + break; + case CPU_STM32MP253Axx: + cpu_s = "253A"; + break; + case CPU_STM32MP251Fxx: + cpu_s = "251F"; + break; + case CPU_STM32MP251Dxx: + cpu_s = "251D"; + break; + case CPU_STM32MP251Cxx: + cpu_s = "251C"; + break; + case CPU_STM32MP251Axx: + cpu_s = "251A"; + break; + default: + cpu_s = "25??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + case CPU_REV2: + cpu_r = "B"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP25_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP25_PKG_AL_TBGA361: + package = "AL"; + break; + case STM32MP25_PKG_AK_TBGA424: + package = "AK"; + break; + case STM32MP25_PKG_AI_TBGA436: + package = "AI"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c new file mode 100644 index 00000000000..8bcbd979340 --- /dev/null +++ b/arch/arm/mach-stm32mp/syscon.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include <clk.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/stm32.h> + +static const struct udevice_id stm32mp_syscon_ids[] = { + { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG}, + { } +}; + +static int stm32mp_syscon_probe(struct udevice *dev) +{ + struct clk_bulk clk_bulk; + int ret; + + ret = clk_get_bulk(dev, &clk_bulk); + if (!ret) + clk_enable_bulk(&clk_bulk); + + return 0; +} + +U_BOOT_DRIVER(syscon_stm32mp) = { + .name = "stmp32mp_syscon", + .id = UCLASS_SYSCON, + .of_match = stm32mp_syscon_ids, + .bind = dm_scan_fdt_dev, + .probe = stm32mp_syscon_probe, +}; diff --git a/arch/arm/mach-stm32mp/timers.c b/arch/arm/mach-stm32mp/timers.c new file mode 100644 index 00000000000..a3207895f40 --- /dev/null +++ b/arch/arm/mach-stm32mp/timers.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * Author: Cheick Traore <cheick.traore@foss.st.com> + * + * Originally based on the Linux kernel v6.1 drivers/mfd/stm32-timers.c. + */ + +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/timers.h> +#include <dm/device_compat.h> + +static void stm32_timers_get_arr_size(struct udevice *dev) +{ + struct stm32_timers_plat *plat = dev_get_plat(dev); + struct stm32_timers_priv *priv = dev_get_priv(dev); + u32 arr; + + /* Backup ARR to restore it after getting the maximum value */ + arr = readl(plat->base + TIM_ARR); + + /* + * Only the available bits will be written so when readback + * we get the maximum value of auto reload register + */ + writel(~0L, plat->base + TIM_ARR); + priv->max_arr = readl(plat->base + TIM_ARR); + writel(arr, plat->base + TIM_ARR); +} + +static int stm32_timers_of_to_plat(struct udevice *dev) +{ + struct stm32_timers_plat *plat = dev_get_plat(dev); + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) { + dev_err(dev, "can't get address\n"); + return -ENOENT; + } + + return 0; +} + +static int stm32_timers_probe(struct udevice *dev) +{ + struct stm32_timers_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret = 0; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock: ret=%d\n", ret); + return ret; + } + + priv->rate = clk_get_rate(&clk); + + stm32_timers_get_arr_size(dev); + + return ret; +} + +static const struct udevice_id stm32_timers_ids[] = { + { .compatible = "st,stm32-timers" }, + {} +}; + +U_BOOT_DRIVER(stm32_timers) = { + .name = "stm32_timers", + .id = UCLASS_NOP, + .of_match = stm32_timers_ids, + .of_to_plat = stm32_timers_of_to_plat, + .plat_auto = sizeof(struct stm32_timers_plat), + .probe = stm32_timers_probe, + .priv_auto = sizeof(struct stm32_timers_priv), + .bind = dm_scan_fdt_dev, +}; |