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-rw-r--r--arch/arm/mach-tegra/Makefile2
-rw-r--r--arch/arm/mach-tegra/board.c7
-rw-r--r--arch/arm/mach-tegra/board2.c2
-rw-r--r--arch/arm/mach-tegra/clock.c6
-rw-r--r--arch/arm/mach-tegra/tegra114/Kconfig10
-rw-r--r--arch/arm/mach-tegra/tegra114/clock.c1
-rw-r--r--arch/arm/mach-tegra/tegra124/clock.c4
-rw-r--r--arch/arm/mach-tegra/tegra20/Kconfig8
-rw-r--r--arch/arm/mach-tegra/tegra20/Makefile2
-rw-r--r--arch/arm/mach-tegra/tegra210/clock.c4
-rw-r--r--arch/arm/mach-tegra/tegra30/Makefile2
11 files changed, 39 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index ebac3473a1f..2f0341bc02a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o
obj-y += board.o board2.o
obj-y += cache.o
obj-$(CONFIG_TEGRA_CLKRST) += clock.o
-obj-$(CONFIG_$(XPL_)TEGRA_CRYPTO) += crypto.o
+obj-$(CONFIG_$(PHASE_)TEGRA_CRYPTO) += crypto.o
obj-$(CONFIG_TEGRA_PMC) += powergate.o
obj-y += xusb-padctl-dummy.o
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index 7ca56a3b081..4835824f724 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -169,6 +169,8 @@ static int uart_configs[] = {
FUNCMUX_UART1_GPU,
#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
+ #elif defined(CONFIG_TEGRA_UARTA_SDB_SDD)
+ FUNCMUX_UART1_SDB_SDD,
#else
FUNCMUX_UART1_IRRX_IRTX,
#endif
@@ -236,18 +238,23 @@ void board_init_uart_f(void)
int uart_ids = 0; /* bit mask of which UART ids to enable */
#ifdef CONFIG_TEGRA_ENABLE_UARTA
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
uart_ids |= UARTA;
#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTB
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE
uart_ids |= UARTB;
#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTC
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTC_BASE
uart_ids |= UARTC;
#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTD
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
uart_ids |= UARTD;
#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTE
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTE_BASE
uart_ids |= UARTE;
#endif
setup_uarts(uart_ids);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 6e9ef68caf9..68534dcbb22 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -96,7 +96,7 @@ int checkboard(void)
{
int board_id = tegra_board_id();
- printf("Board: %s", CFG_TEGRA_BOARD_STRING);
+ printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
if (board_id != -1)
printf(", ID: %d\n", board_id);
printf("\n");
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index a375693481e..4f0cc19df50 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -703,6 +703,12 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
else
writel(base_reg, &simple_pll->pll_base);
+ /* PLLD and PLLD2 are only clocks which have ENABLE bit */
+ if (clkid == CLOCK_ID_DISPLAY)
+ setbits_le32(&pll->pll_misc, BIT(PLLD_CLKENABLE));
+ if (clkid == CLOCK_ID_DISPLAY2)
+ setbits_le32(&simple_pll->pll_misc, BIT(PLLD_CLKENABLE));
+
/*
* Changing clocks was never intended in the U-Boot for Tegra.
* If a clock is changed after clock_init() the parent rate is wrong.
diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig
index 5f0f909dd3b..98f1d0e71c1 100644
--- a/arch/arm/mach-tegra/tegra114/Kconfig
+++ b/arch/arm/mach-tegra/tegra114/Kconfig
@@ -8,11 +8,21 @@ config TARGET_DALMORE
bool "NVIDIA Tegra114 Dalmore evaluation board"
select BOARD_LATE_INIT
+config TARGET_TEGRATAB
+ bool "NVIDIA Tegra114 TegraTab evaluation board"
+ select BOARD_LATE_INIT
+
+config TARGET_TRANSFORMER_T114
+ bool "ASUS Tegra114 Transformer board"
+ select BOARD_LATE_INIT
+
endchoice
config SYS_SOC
default "tegra114"
source "board/nvidia/dalmore/Kconfig"
+source "board/nvidia/tegratab/Kconfig"
+source "board/asus/transformer-t114/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index d5cc8ac44dd..d67d808b724 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -796,7 +796,6 @@ struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
- { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 0ea212f80e2..8a6735d71af 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -598,8 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
- { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
- .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
+ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
+ .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLD2 */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
.lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
};
diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig
index e2735d93e28..a79fdc25650 100644
--- a/arch/arm/mach-tegra/tegra20/Kconfig
+++ b/arch/arm/mach-tegra/tegra20/Kconfig
@@ -17,6 +17,9 @@ config TEGRA_UARTA_GPU
config TEGRA_UARTA_SDIO1
bool
+config TEGRA_UARTA_SDB_SDD
+ bool
+
choice
prompt "Tegra20 board select"
optional
@@ -29,6 +32,10 @@ config TARGET_MEDCOM_WIDE
bool "Avionic Design Medcom-Wide board"
select BOARD_LATE_INIT
+config TARGET_MOT
+ bool "Motorola Tegra20 board"
+ select BOARD_LATE_INIT
+
config TARGET_PAZ00
bool "Paz00 board"
select BOARD_LATE_INIT
@@ -76,6 +83,7 @@ config SYS_SOC
source "board/nvidia/harmony/Kconfig"
source "board/avionic-design/medcom-wide/Kconfig"
+source "board/motorola/mot/Kconfig"
source "board/compal/paz00/Kconfig"
source "board/acer/picasso/Kconfig"
source "board/avionic-design/plutux/Kconfig"
diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile
index 32c1866b099..a3ea759d764 100644
--- a/arch/arm/mach-tegra/tegra20/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2010,2011 Nvidia Corporation.
obj-$(CONFIG_XPL_BUILD) += cpu.o
-obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o
+obj-$(CONFIG_$(PHASE_)CMD_EBTUPDATE) += bct.o
# The AVP is ARMv4T architecture so we must use special compiler
# flags for any startup files it might use.
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 04708f97144..d1ede5238dd 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -668,8 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
.lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
- { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
- .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
+ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
+ .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLD2 */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
.lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
};
diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile
index b36657a432f..d6351734ec0 100644
--- a/arch/arm/mach-tegra/tegra30/Makefile
+++ b/arch/arm/mach-tegra/tegra30/Makefile
@@ -3,6 +3,6 @@
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
obj-$(CONFIG_XPL_BUILD) += cpu.o
-obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o
+obj-$(CONFIG_$(PHASE_)CMD_EBTUPDATE) += bct.o
obj-y += clock.o
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 08:53:54 +0000