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-rw-r--r--arch/arm/mach-uniphier/Kconfig1
-rw-r--r--arch/arm/mach-uniphier/board_init.c28
-rw-r--r--arch/arm/mach-uniphier/clk/pll-base-ld20.c6
-rw-r--r--arch/arm/mach-uniphier/clk/pll-ld11.c13
-rw-r--r--arch/arm/mach-uniphier/clk/pll-ld20.c21
-rw-r--r--arch/arm/mach-uniphier/clk/pll-pxs3.c55
-rw-r--r--arch/arm/mach-uniphier/sbc/sbc-pxs2.c2
-rw-r--r--arch/arm/mach-uniphier/sc64-regs.h21
8 files changed, 96 insertions, 51 deletions
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 6a7e239e0d2..ee221124123 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -9,7 +9,6 @@ config ARCH_UNIPHIER_32BIT
select CPU_V7_HAS_NONSEC
select ARMV7_NONSEC
select ARCH_SUPPORT_PSCI
- imply NAND
choice
prompt "UniPhier SoC select"
diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
index ed58d07f7e5..a6ee22e3392 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -78,7 +78,6 @@ static void uniphier_ld20_misc_init(void)
struct uniphier_initdata {
unsigned int soc_id;
- bool nand_2cs;
void (*sbc_init)(void);
void (*pll_init)(void);
void (*clk_init)(void);
@@ -89,7 +88,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD4)
{
.soc_id = UNIPHIER_LD4_ID,
- .nand_2cs = true,
.sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
@@ -98,7 +96,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
{
.soc_id = UNIPHIER_PRO4_ID,
- .nand_2cs = false,
.sbc_init = uniphier_sbc_init_savepin,
.pll_init = uniphier_pro4_pll_init,
.clk_init = uniphier_pro4_clk_init,
@@ -107,7 +104,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
{
.soc_id = UNIPHIER_SLD8_ID,
- .nand_2cs = true,
.sbc_init = uniphier_ld4_sbc_init,
.pll_init = uniphier_ld4_pll_init,
.clk_init = uniphier_ld4_clk_init,
@@ -116,7 +112,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
{
.soc_id = UNIPHIER_PRO5_ID,
- .nand_2cs = true,
.sbc_init = uniphier_sbc_init_savepin,
.clk_init = uniphier_pro5_clk_init,
},
@@ -124,7 +119,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
{
.soc_id = UNIPHIER_PXS2_ID,
- .nand_2cs = true,
.sbc_init = uniphier_pxs2_sbc_init,
.clk_init = uniphier_pxs2_clk_init,
},
@@ -132,7 +126,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
{
.soc_id = UNIPHIER_LD6B_ID,
- .nand_2cs = true,
.sbc_init = uniphier_pxs2_sbc_init,
.clk_init = uniphier_pxs2_clk_init,
},
@@ -140,7 +133,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
{
.soc_id = UNIPHIER_LD11_ID,
- .nand_2cs = false,
.sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld11_pll_init,
.clk_init = uniphier_ld11_clk_init,
@@ -150,7 +142,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{
.soc_id = UNIPHIER_LD20_ID,
- .nand_2cs = false,
.sbc_init = uniphier_ld11_sbc_init,
.pll_init = uniphier_ld20_pll_init,
.clk_init = uniphier_ld20_clk_init,
@@ -160,7 +151,6 @@ static const struct uniphier_initdata uniphier_initdata[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
{
.soc_id = UNIPHIER_PXS3_ID,
- .nand_2cs = false,
.sbc_init = uniphier_pxs2_sbc_init,
.pll_init = uniphier_pxs3_pll_init,
.clk_init = uniphier_pxs3_clk_init,
@@ -172,7 +162,6 @@ UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata)
int board_init(void)
{
const struct uniphier_initdata *initdata;
- int ret;
led_puts("U0");
@@ -188,33 +177,24 @@ int board_init(void)
led_puts("U0");
- if (IS_ENABLED(CONFIG_NAND_DENALI)) {
- ret = uniphier_pin_init(initdata->nand_2cs ?
- "nand2cs_grp" : "nand_grp");
- if (ret)
- pr_err("failed to init NAND pins\n");
- }
-
- led_puts("U1");
-
if (initdata->pll_init)
initdata->pll_init();
- led_puts("U2");
+ led_puts("U1");
if (initdata->clk_init)
initdata->clk_init();
- led_puts("U3");
+ led_puts("U2");
if (initdata->misc_init)
initdata->misc_init();
- led_puts("U4");
+ led_puts("U3");
uniphier_setup_xirq();
- led_puts("U5");
+ led_puts("U4");
support_card_late_init();
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index 697eb7aabf0..3aa42f8bfdc 100644
--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -88,7 +88,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
if (!base)
return -ENOMEM;
- tmp = readl(base + 8); /* SSCPLLCTRL */
+ tmp = readl(base + 8); /* SSCPLLCTRL3 */
tmp &= ~SC_PLLCTRL3_REGI_MASK;
tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
writel(tmp, base + 8);
@@ -133,9 +133,9 @@ int uniphier_ld20_dspll_init(unsigned long reg_base)
if (!base)
return -ENOMEM;
- tmp = readl(base + 8); /* DSPLLCTRL2 */
+ tmp = readl(base + 4); /* DSPLLCTRL2 */
tmp |= SC_DSPLLCTRL2_K_LD;
- writel(tmp, base + 8);
+ writel(tmp, base + 4);
iounmap(base);
diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index 02befa298b4..1a7ec295252 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -4,13 +4,24 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
+#include <linux/delay.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
+/* PLL type: SSC */
+#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */
+#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
+#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
void uniphier_ld11_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */
diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c
index 121a3690e83..5e072c6dff7 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -5,12 +5,31 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
+#include <linux/delay.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
+/* PLL type: SSC */
+#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
+#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */
+#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */
+#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
+#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
+#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
+#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
+#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
+
void uniphier_ld20_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c
index 201d3517a86..e84d52b80f3 100644
--- a/arch/arm/mach-uniphier/clk/pll-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c
@@ -1,9 +1,64 @@
/*
+ * Copyright (C) 2017 Socionext Inc.
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/delay.h>
+
#include "../init.h"
+#include "../sc64-regs.h"
+#include "pll.h"
+
+/* PLL type: SSC */
+#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
+#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
+#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
+#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */
+#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440)
+#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450)
+#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460)
+#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470)
+#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */
+#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */
+#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */
+#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0)
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+
+/* PLL type: DSPLL */
+#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
void uniphier_pxs3_pll_init(void)
{
+ uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ /* do nothing for SPLL */
+ uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
+ uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+
+ mdelay(1);
+
+ uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+
+ uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
+ uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
+
+ uniphier_ld20_dspll_init(SC_VPLL8KCTRL);
}
diff --git a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
index 342a086b7df..0e0ba27bd97 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c
@@ -16,4 +16,6 @@ void uniphier_pxs2_sbc_init(void)
/* necessary for ROM boot ?? */
/* system bus output enable */
writel(0x17, PC0CTRL);
+
+ uniphier_pin_init("system_bus_grp"); /* PXs3 */
}
diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index d3aa18530d9..d0a51f239c3 100644
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -12,27 +12,6 @@
#define SC_BASE_ADDR 0x61840000
-/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* LD11/20: CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* LD11/20: misc */
-#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* LD20: IPP */
-#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* LD11/20: Video codec */
-#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD11 */
-#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* LD20: VPE etc. */
-#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* LD20: GPU/Mali */
-#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* LD11: DDR memory */
-#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* LD20: DDR memory 0 */
-#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* LD20: DDR memory 1 */
-#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* LD20: DDR memory 2 */
-
-/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
-
-/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
-#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0)
-
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 19:38:45 +0000