summaryrefslogtreecommitdiff
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/arm1136/cpu.c103
-rw-r--r--arch/arm/cpu/arm926ejs/cache.c19
-rw-r--r--arch/arm/cpu/arm926ejs/mx28/mx28.c6
-rw-r--r--arch/arm/cpu/armv7/config.mk3
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c8
-rw-r--r--arch/arm/include/asm/arch-mx28/dma.h4
-rw-r--r--arch/arm/include/asm/arch-mx35/mx35_pins.h2
-rw-r--r--arch/arm/include/asm/arch-mx5/mx5x_pins.h2
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h4
9 files changed, 131 insertions, 20 deletions
diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index 2b91631735..f72bab6693 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -70,8 +70,105 @@ int cleanup_before_linux (void)
static void cache_flush(void)
{
unsigned long i = 0;
+ /* clean entire data cache */
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+ /* invalidate both caches and flush btb */
+ asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+ /* mem barrier to sync things */
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+void invalidate_dcache_all(void)
+{
+ asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static inline int bad_cache_range(unsigned long start, unsigned long stop)
+{
+ int ok = 1;
+
+ if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
- asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */
- asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+ if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (!ok)
+ debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+ start, stop);
+
+ return ok;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (bad_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (bad_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 5b23e3a71b..2740ad7e29 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -30,7 +30,7 @@
void invalidate_dcache_all(void)
{
- asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0));
+ asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
}
void flush_dcache_all(void)
@@ -40,7 +40,7 @@ void flush_dcache_all(void)
"mrc p15, 0, r15, c7, c14, 3\n"
"bne 0b\n"
"mcr p15, 0, %0, c7, c10, 4\n"
- ::"r"(0):"memory"
+ : : "r"(0) : "memory"
);
}
@@ -55,7 +55,7 @@ static int check_cache_range(unsigned long start, unsigned long stop)
ok = 0;
if (!ok)
- printf("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+ debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
start, stop);
return ok;
@@ -67,7 +67,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start));
+ asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
@@ -78,11 +78,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
- asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start));
+ asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
- asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
void flush_cache(unsigned long start, unsigned long size)
@@ -114,8 +114,7 @@ void flush_cache(unsigned long start, unsigned long size)
/*
* Stub implementations for l2 cache operations
*/
-void __l2_cache_disable(void)
-{
-}
+void __l2_cache_disable(void) {}
+
void l2_cache_disable(void)
- __attribute__((weak, alias("__l2_cache_disable")));
+ __attribute__((weak, alias("__l2_cache_disable")));
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index cf6d4e9bd4..dc0338dfb5 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -30,6 +30,7 @@
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
@@ -172,6 +173,11 @@ int arch_cpu_init(void)
*/
mxs_gpio_init();
+#ifdef CONFIG_APBH_DMA
+ /* Start APBH DMA */
+ mxs_dma_init();
+#endif
+
return 0;
}
#endif
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index 83ddf10f1f..f532d62e57 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -31,3 +31,6 @@ PLATFORM_CPPFLAGS += -march=armv5
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+ifneq ($(CONFIG_IMX_CONFIG),)
+ALL-y += $(obj)u-boot.imx
+endif
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a81e2bc01a..543b2cc6d8 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -85,6 +85,14 @@ int arch_cpu_init(void)
}
#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
diff --git a/arch/arm/include/asm/arch-mx28/dma.h b/arch/arm/include/asm/arch-mx28/dma.h
index 52747e2fbf..4a1820bdee 100644
--- a/arch/arm/include/asm/arch-mx28/dma.h
+++ b/arch/arm/include/asm/arch-mx28/dma.h
@@ -140,6 +140,8 @@ void mxs_dma_desc_free(struct mxs_dma_desc *);
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
int mxs_dma_go(int chan);
-int mxs_dma_init(void);
+void mxs_dma_init(void);
+int mxs_dma_init_channel(int chan);
+int mxs_dma_release(int chan);
#endif /* __DMA_H__ */
diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h
index 3676e330bd..8c38139118 100644
--- a/arch/arm/include/asm/arch-mx35/mx35_pins.h
+++ b/arch/arm/include/asm/arch-mx35/mx35_pins.h
@@ -84,8 +84,6 @@
GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
#define NON_GPIO_I 0x7
#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
index 4e3a31b262..122fbeef6a 100644
--- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
@@ -78,8 +78,6 @@
GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
-#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
#define NON_GPIO_PORT 0x7
#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index cad957a3b7..6d25c8d983 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -19,6 +19,8 @@
#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
#define __ASM_ARCH_MX6_IMX_REGS_H__
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
#define CAAM_ARB_BASE_ADDR 0x00100000
@@ -168,8 +170,6 @@
#define FEC_QUIRK_ENET_MAC
#define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31))
-#define GPIO_TO_PORT(number) (((number)/32)+1)
-#define GPIO_TO_INDEX(number) ((number)&31)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-30 08:38:45 +0000