diff options
Diffstat (limited to 'arch/arm')
95 files changed, 2587 insertions, 808 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fedfdb21457..79f60eb3f34 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1416,7 +1416,7 @@ config TARGET_TOTAL_COMPUTE select DM_SERIAL select DM_GPIO select MMC - imply OF_HAS_PRIOR_STAGE + imply OF_HAS_PRIOR_STAGE if !BLOBLIST imply MISC_INIT_R config TARGET_LS2080A_EMU diff --git a/arch/arm/cpu/armv7m/start.S b/arch/arm/cpu/armv7m/start.S index 0c07f2140c7..a439404a248 100644 --- a/arch/arm/cpu/armv7m/start.S +++ b/arch/arm/cpu/armv7m/start.S @@ -4,13 +4,19 @@ * Kamil Lulko, <kamil.lulko@gmail.com> */ +#include <linux/linkage.h> #include <asm/assembler.h> -.globl reset -.type reset, %function -reset: - W(b) _main +/* + * Startup code (reset vector) + */ +ENTRY(reset) + W(b) _main @ Jump to _main (C runtime crt0.S) +ENDPROC(reset) -.globl c_runtime_cpu_setup -c_runtime_cpu_setup: - mov pc, lr +/* + * Setup CPU for C runtime + */ +ENTRY(c_runtime_cpu_setup) + mov pc, lr @ Jump back to caller +ENDPROC(c_runtime_cpu_setup) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index ca6be3626fb..e8d2339f1a3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -7,6 +7,7 @@ #include <config.h> #include <clock_legacy.h> #include <efi_loader.h> +#include <env.h> #include <log.h> #include <asm/cache.h> #include <linux/libfdt.h> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 82f5c374f10..976dbda48c3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra20-asus-tf101.dtb \ tegra20-asus-tf101g.dtb \ tegra20-harmony.dtb \ + tegra20-lg-star.dtb \ tegra20-medcom-wide.dtb \ tegra20-motorola-daytona.dtb \ tegra20-motorola-olympus.dtb \ @@ -419,6 +420,7 @@ dtb-$(CONFIG_AM33XX) += \ am335x-evm.dtb \ am335x-evmsk.dtb \ am335x-bonegreen.dtb \ + am335x-bonegreen-eco.dtb \ am335x-bonegreen-wireless.dtb \ am335x-icev2.dtb \ am335x-pocketbeagle.dtb \ @@ -916,8 +918,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_IMX9) += \ - imx93-var-som-symphony.dtb \ - imx93-phyboard-segin.dtb + imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ diff --git a/arch/arm/dts/am335x-bonegreen-eco.dts b/arch/arm/dts/am335x-bonegreen-eco.dts new file mode 100644 index 00000000000..f3363d1ebcc --- /dev/null +++ b/arch/arm/dts/am335x-bonegreen-eco.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Bootlin + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-bonegreen-common.dtsi" + +/ { + model = "TI AM335x BeagleBone Green Eco"; + compatible = "ti,am335x-bone-green-eco", "ti,am335x-bone-green", + "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; + + cpus { + cpu@0 { + /delete-property/ cpu0-supply; + }; + }; +}; + +&usb0 { + interrupts-extended = <&intc 18>; + interrupt-names = "mc"; +}; + +&baseboard_eeprom { + /delete-property/ vcc-supply; +}; + +&i2c0 { + /delete-node/ tps@24; +}; diff --git a/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi b/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi index 7730bb60dd0..faf596255f1 100644 --- a/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi +++ b/arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi @@ -5,8 +5,12 @@ * Author: Michael Trimarchi <michael@amarulasolutions.com> */ -&{/soc} { - bootph-all; +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &aips2 { diff --git a/arch/arm/dts/imx93-phyboard-segin.dts b/arch/arm/dts/imx93-phyboard-segin.dts deleted file mode 100644 index 85fb188b057..00000000000 --- a/arch/arm/dts/imx93-phyboard-segin.dts +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> - * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> - * - * Product homepage: - * phyBOARD-Segin carrier board is reused for the i.MX93 design. - * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/ - */ -/dts-v1/; - -#include "imx93-phycore-som.dtsi" - -/{ - model = "PHYTEC phyBOARD-Segin-i.MX93"; - compatible = "phytec,imx93-phyboard-segin", "phytec,imx93-phycore-som", - "fsl,imx93"; - - chosen { - stdout-path = &lpuart1; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "VCC_SD"; - }; -}; - -/* Console */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* eMMC */ -&usdhc1 { - no-1-8-v; -}; - -/* SD-Card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; - bus-width = <4>; - cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - no-mmc; - no-sdio; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x30e - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e - >; - }; - - pinctrl_usdhc2_cd: usdhc2cdgrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; - - pinctrl_usdhc2_default: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; -}; diff --git a/arch/arm/dts/imx93-phycore-som.dtsi b/arch/arm/dts/imx93-phycore-som.dtsi deleted file mode 100644 index 88c2657b50e..00000000000 --- a/arch/arm/dts/imx93-phycore-som.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de> - * Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com> - * - * Product homepage: - * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ - */ - -#include <dt-bindings/leds/common.h> - -#include "imx93.dtsi" - -/{ - model = "PHYTEC phyCORE-i.MX93"; - compatible = "phytec,imx93-phycore-som", "fsl,imx93"; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - alloc-ranges = <0 0x80000000 0 0x40000000>; - size = <0 0x10000000>; - linux,cma-default; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -/* Ethernet */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - fsl,magic-packet; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <100000000>, <50000000>, <50000000>; - status = "okay"; - - mdio: mdio { - clock-frequency = <5000000>; - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -/* Watchdog */ -&wdog3 { - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e - MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386 - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; -}; diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi new file mode 100644 index 00000000000..2d1f02baa5f --- /dev/null +++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "imx95-u-boot.dtsi" + +&lpuart1 { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&wdog3 { + status = "disabled"; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi new file mode 100644 index 00000000000..5ec3b1c51d6 --- /dev/null +++ b/arch/arm/dts/imx95-u-boot.dtsi @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +/ { + binman { + multiple-images; + + m33-oei-ddrfw { + pad-byte = <0x00>; + align-size = <0x8>; + filename = "m33-oei-ddrfw.bin"; + + oei-m33-ddr { + align-size = <0x4>; + filename = "oei-m33-ddr.bin"; + type = "blob-ext"; + }; + + imx-lpddr { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem { + filename = "lpddr5_imem_v202311.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem { + filename = "lpddr5_dmem_v202311.bin"; + type = "blob-ext"; + }; + }; + + imx-lpddr-qb { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem-qb { + filename = "lpddr5_imem_qb_v202311.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem-qb { + filename = "lpddr5_dmem_qb_v202311.bin"; + type = "blob-ext"; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + align = <0x400>; + align-size = <0x400>; + type = "mkimage"; + args = "-n spl/u-boot-spl.cfgout -T imx8image"; + }; + + u-boot { + type = "mkimage"; + args = "-n u-boot-container.cfgout -T imx8image"; + }; + }; + }; +}; + +&A55_0 { + clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_1 { + clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_2 { + clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_3 { + clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_4 { + clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&A55_5 { + clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&aips1 { + bootph-all; +}; + +&aips2 { + bootph-all; +}; + +&aips3 { + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; +}; + +&elemu1 { + bootph-all; + status = "okay"; +}; + +&elemu3 { + bootph-all; + status = "okay"; +}; + +&{/firmware} { + bootph-all; +}; + +&{/firmware/scmi} { + bootph-all; +}; + +&{/firmware/scmi/protocol@11} { + bootph-all; +}; + +&{/firmware/scmi/protocol@13} { + bootph-all; +}; + +&{/firmware/scmi/protocol@14} { + bootph-all; +}; + +&{/firmware/scmi/protocol@19} { + bootph-all; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&mu2 { + bootph-all; +}; + +&osc_24m { + bootph-all; +}; + +&{/soc} { + bootph-all; +}; + +&sram0 { + bootph-all; +}; + +&scmi_buf0 { + reg = <0x0 0x400>; + bootph-all; +}; + +&scmi_buf1 { + bootph-all; +}; diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts index 0d8e7016860..354352477c7 100644 --- a/arch/arm/dts/imxrt1170-evk.dts +++ b/arch/arm/dts/imxrt1170-evk.dts @@ -234,6 +234,34 @@ (IMX_PAD_SION | 8) /* SEMC_DQS */ >; }; + + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0xa + IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0xa + IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0xa + IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0xa + IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0xa + IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0xa + IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0xa + >; + }; + }; +}; + +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <250000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; }; diff --git a/arch/arm/dts/imxrt1170.dtsi b/arch/arm/dts/imxrt1170.dtsi index 2de775f043f..08665eaf06a 100644 --- a/arch/arm/dts/imxrt1170.dtsi +++ b/arch/arm/dts/imxrt1170.dtsi @@ -246,6 +246,19 @@ #interrupt-cells = <2>; }; + flexspi1: spi@400cc000 { + compatible = "nxp,imxrt1170-fspi"; + reg = <0x400cc000 0x800>, <0x30000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <130>; + clocks = <&clks IMXRT1170_CLK_DUMMY>, + <&clks IMXRT1170_CLK_FLEXSPI1>; + clock-names = "fspi_en", "fspi"; + status = "disabled"; + }; + gpt1: gpt1@400ec000 { compatible = "fsl,imxrt-gpt"; reg = <0x400ec000 0x4000>; diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index a067b0ba354..2a4f0e45365 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -9,10 +9,6 @@ #include "k3-binman.dtsi" / { - chosen { - tick-timer = &main_timer0; - }; - /* Keep the LEDs on by default to indicate life */ leds { led-0 { @@ -37,10 +33,6 @@ }; }; -&main_timer0 { - clock-frequency = <25000000>; -}; - &sd_pins_default { /* Force to use SDCD card detect pin */ pinctrl-single,pins = < @@ -71,13 +63,6 @@ #define AM625_BEAGLEPLAY_DTB "dts/upstream/src/arm64/ti/k3-am625-beagleplay.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - }; - }; - tifsstub-gp { filename = "tifsstub.bin_gp"; ti-secure-rom { @@ -153,8 +138,8 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { - filename = "ti-dm.bin"; + ti-dm { + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi index c001e2c96e8..ee273563e83 100644 --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi @@ -13,7 +13,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - tick-timer = &main_timer0; }; aliases { @@ -96,10 +95,6 @@ bootph-all; }; -&main_timer0 { - clock-frequency = <25000000>; -}; - &main_uart0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index 4a65427e877..32d8804a395 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -36,7 +36,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -45,7 +44,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -82,7 +80,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -91,7 +88,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -125,7 +121,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -158,13 +153,6 @@ #define AM625_PHYBOARD_LYRA_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - }; - }; - tifsstub-hs { filename = "tifsstub.bin_hs"; ti-secure-rom { @@ -270,8 +258,8 @@ content = <&dm>; keyfile = "custMpk.pem"; }; - dm: blob-ext { - filename = "ti-dm.bin"; + dm: ti-dm { + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; @@ -418,8 +406,8 @@ fit { images { dm { - blob-ext { - filename = "ti-dm.bin"; + ti-dm { + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index 9e0a6ed6784..f4b2cd8904e 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -46,6 +46,14 @@ }; }; +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; + &dmsc { mboxes= <&secure_proxy_main 0>, <&secure_proxy_main 1>, @@ -103,7 +111,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts index 70154409b12..7132fae36fa 100644 --- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts @@ -54,6 +54,14 @@ }; }; +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; + &secure_proxy_sa3 { /* We require this for boot handshake */ status = "okay"; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 534eb14795b..6822a5dac89 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -34,7 +34,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -43,7 +42,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -80,7 +78,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -89,7 +86,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -123,7 +119,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -156,14 +151,6 @@ #define AM625_SK_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - tifsstub-hs { filename = "tifsstub.bin_hs"; ti-secure-rom { @@ -270,7 +257,7 @@ keyfile = "custMpk.pem"; }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; @@ -397,7 +384,7 @@ dm { ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 2b333e70f5c..39e8ab8158e 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -69,6 +69,14 @@ ti,secure-host; }; +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; + &secure_proxy_sa3 { /* We require this for boot handshake */ status = "okay"; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 0e6188907e4..bfbba28269c 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -34,7 +34,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -43,7 +42,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -80,7 +78,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -89,7 +86,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62x-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -123,7 +119,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -144,13 +139,6 @@ #define VERDIN_AM62_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - }; - }; - tifsstub-hs { filename = "tifsstub.bin_hs"; ti-secure-rom { @@ -257,7 +245,7 @@ keyfile = "custMpk.pem"; }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; @@ -380,7 +368,7 @@ dm { ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi index b3d237c8697..8487ea14800 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi @@ -12,10 +12,6 @@ eeprom2 = &eeprom_display_adapter; }; - chosen { - tick-timer = &main_timer0; - }; - memory@80000000 { bootph-all; }; @@ -25,10 +21,6 @@ }; }; -&main_timer0 { - clock-frequency = <25000000>; -}; - &main_bcdma { reg = <0x00 0x485c0100 0x00 0x100>, <0x00 0x4c000000 0x00 0x20000>, diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index 325702ed6e0..fd340101532 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -41,7 +41,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -50,7 +49,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -87,7 +85,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -96,7 +93,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -130,7 +126,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -164,14 +159,6 @@ #define AM62A7_PHYBOARD_LYRA_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - tifsstub-hs { filename = "tifsstub.bin_hs"; ti-secure-rom { @@ -276,7 +263,7 @@ keyfile = "custMpk.pem"; }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; @@ -462,7 +449,7 @@ }; dm { ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 2a8c260387b..877a513a241 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -38,7 +38,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -47,7 +46,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -84,7 +82,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -93,7 +90,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -127,7 +123,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -148,14 +143,6 @@ #define AM62A7_SK_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - tifsstub-hs { filename = "tifsstub.bin_hs"; ti-secure-rom { @@ -260,7 +247,7 @@ keyfile = "custMpk.pem"; }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; @@ -385,7 +372,7 @@ }; dm { ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi index f922f4b4781..73255a18e9b 100644 --- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi @@ -13,7 +13,6 @@ / { chosen { stdout-path = "serial2:115200n8"; - tick-timer = &main_timer0; }; aliases { @@ -157,10 +156,6 @@ bootph-all; }; -&main_timer0 { - bootph-all; -}; - &main_uart0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts index 0060c7a6934..63b7864a469 100644 --- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts @@ -88,6 +88,15 @@ ti,secure-host; }; +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; + bootph-pre-ram; +}; + &main_bcdma { ti,sci = <&dm_tifs>; }; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index 797644a7e0d..d65e5c4d4e1 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -38,7 +38,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { @@ -49,7 +48,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { @@ -87,7 +85,6 @@ ti_fs_enc_hs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-am62px-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_hs: combined-tifs-cfg.bin { @@ -98,7 +95,6 @@ sysfw_inner_cert_hs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-am62px-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_hs: combined-dm-cfg.bin { @@ -127,14 +123,6 @@ #define AM62PX_SK_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - - blob-ext { - filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; tifsstub-hs { filename = "tifsstub.bin_hs"; ti-secure-rom { @@ -210,7 +198,7 @@ }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi index 5228eed19bf..966905bd64d 100644 --- a/arch/arm/dts/k3-am642-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am642-phycore-som-binman.dtsi @@ -33,7 +33,6 @@ ti_sci_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg: combined-sysfw-cfg.bin { filename = "combined-sysfw-cfg.bin"; @@ -42,7 +41,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; }; @@ -73,7 +71,6 @@ ti_sci_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg_fs: combined-sysfw-cfg.bin { filename = "combined-sysfw-cfg.bin"; @@ -82,7 +79,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; }; @@ -109,7 +105,6 @@ ti_sci_gp: ti-sci-gp.bin { filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin { filename = "combined-sysfw-cfg.bin"; diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi index f768c4d946d..32e47a3f688 100644 --- a/arch/arm/dts/k3-am64x-binman.dtsi +++ b/arch/arm/dts/k3-am64x-binman.dtsi @@ -29,7 +29,6 @@ ti_sci_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg: combined-sysfw-cfg.bin { filename = "combined-sysfw-cfg.bin"; @@ -38,7 +37,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; }; @@ -69,7 +67,6 @@ ti_sci_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg_fs: combined-sysfw-cfg.bin { filename = "combined-sysfw-cfg.bin"; @@ -78,7 +75,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-sci-firmware-am64x_sr2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; }; @@ -105,7 +101,6 @@ ti_sci_gp: ti-sci-gp.bin { filename = "ti-sysfw/ti-sci-firmware-am64x-gp.bin"; type = "blob-ext"; - optional; }; combined_sysfw_cfg_gp: combined-sysfw-cfg-gp.bin { filename = "combined-sysfw-cfg.bin"; diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi index 350775e42c2..cc82c8b5768 100644 --- a/arch/arm/dts/k3-am65x-binman.dtsi +++ b/arch/arm/dts/k3-am65x-binman.dtsi @@ -32,12 +32,10 @@ ti_sci_cert: ti-sci-cert.bin { filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; ti-sci-firmware-am65x-hs-enc.bin { filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; }; itb { @@ -73,7 +71,6 @@ ti_sci: ti-sci.bin { filename = "ti-sysfw/ti-sci-firmware-am65x_sr2-gp.bin"; type = "blob-ext"; - optional; }; }; itb_gp { diff --git a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi index 6c52038cdca..2a0023fb7c3 100644 --- a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi +++ b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi @@ -53,6 +53,10 @@ status = "disabled"; }; +&main_gpio1 { + bootph-all; +}; + #if IS_ENABLED(CONFIG_TARGET_J722S_R5_BEAGLEY_AI) &binman { @@ -84,7 +88,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { @@ -95,7 +98,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { @@ -136,7 +138,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { @@ -147,7 +148,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { @@ -164,15 +164,6 @@ #define BEAGLEY_AI_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - - blob-ext { - filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - ti-spl { insert-template = <&ti_spl_template>; @@ -185,7 +176,7 @@ }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts index 9c6e324ba29..e8362647c5d 100644 --- a/arch/arm/dts/k3-am69-r5-sk.dts +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -10,3 +10,10 @@ #include "k3-j784s4-ddr.dtsi" #include "k3-am69-sk-u-boot.dtsi" #include "k3-j784s4-r5.dtsi" + +&tps659413 { + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; +}; diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi index 2f119508e18..fc686087023 100644 --- a/arch/arm/dts/k3-am69-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi @@ -58,17 +58,18 @@ #else // CONFIG_ARM64 &binman { - ti-dm { - filename = "ti-dm.bin"; - - blob-ext { - filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - tispl { insert-template = <&ti_spl>; + + fit { + images { + dm { + ti-dm { + filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + }; + }; }; u-boot { @@ -77,6 +78,16 @@ tispl-unsigned { insert-template = <&ti_spl_unsigned>; + + fit { + images { + dm { + ti-dm { + filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + }; + }; }; u-boot-unsigned { diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index 423badd7cb5..b74bd1657f9 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -35,7 +35,6 @@ ti_fs_enc_sr1: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_sr1: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -44,7 +43,6 @@ sysfw_inner_cert_sr1: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j7200-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_sr1: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -80,7 +78,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -89,7 +86,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -127,7 +123,6 @@ ti_fs_enc_fs_sr1: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs_sr1: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -136,7 +131,6 @@ sysfw_inner_cert_fs_sr1: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j7200-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs_sr1: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -172,7 +166,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -181,7 +174,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j7200_sr2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -216,7 +208,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-j7200-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -237,13 +228,6 @@ #define J7200_EVM_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; ti-spl { insert-template = <&ti_spl_template>; @@ -345,7 +329,7 @@ keyfile = "custMpk.pem"; }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; @@ -430,7 +414,7 @@ images { dm { ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi index 8cefa39290d..6a773c1b3d1 100644 --- a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi @@ -212,13 +212,6 @@ #define J721E_BBAI64_DTB "dts/upstream/src/arm64/ti/k3-j721e-beagleboneai64.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - }; - }; - ti-spl_unsigned { filename = "tispl.bin_unsigned"; pad-byte = <0xff>; @@ -263,8 +256,8 @@ os = "DM"; load = <0x89000000>; entry = <0x89000000>; - blob-ext { - filename = "ti-dm.bin"; + ti-dm { + filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi index 0d607296f0e..9522a956506 100644 --- a/arch/arm/dts/k3-j721e-binman.dtsi +++ b/arch/arm/dts/k3-j721e-binman.dtsi @@ -46,12 +46,10 @@ ti_fs_cert: ti-fs-cert.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-cert.bin"; type = "blob-ext"; - optional; }; ti-fs-firmware-j721e_sr1_1-hs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-enc.bin"; type = "blob-ext"; - optional; }; }; @@ -67,12 +65,10 @@ ti_fs_cert_sr2: ti-fs-cert.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-cert.bin"; type = "blob-ext"; - optional; }; ti-fs-firmware-j721e_sr2-hs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-enc.bin"; type = "blob-ext"; - optional; }; }; @@ -148,12 +144,10 @@ ti-fs-cert-fs.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; ti-fs-firmware-j721e-hs-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr1_1-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; }; itb_fs_sr1_1 { @@ -235,12 +229,10 @@ ti-fs-cert-fs.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; ti-fs-firmware-j721e-hs-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; }; itb_fs { @@ -276,7 +268,6 @@ ti_fs: ti-fs.bin { filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin"; type = "blob-ext"; - optional; }; }; itb_gp { @@ -333,13 +324,6 @@ #define J721E_EVM_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; ti-spl { insert-template = <&ti_spl_template>; @@ -467,7 +451,7 @@ keyfile = "custMpk.pem"; }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; @@ -551,7 +535,7 @@ images { dm { ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts index 586ddb6e7c8..5f0dfe9c2fa 100644 --- a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts +++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts @@ -47,7 +47,6 @@ ti_fs: ti-fs.bin { filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin"; type = "blob-ext"; - optional; }; }; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index d121d8c0c54..4f524e58ceb 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -34,7 +34,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -43,7 +42,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -79,7 +77,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { filename = "combined-tifs-cfg.bin"; @@ -88,7 +85,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j721s2-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { filename = "combined-dm-cfg.bin"; @@ -123,7 +119,6 @@ ti_fs_gp: ti-fs-gp.bin { filename = "ti-sysfw/ti-fs-firmware-j721s2-gp.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { filename = "combined-tifs-cfg.bin"; @@ -145,13 +140,6 @@ #define J721S2_EVM_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - blob-ext { - filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; ti-spl { insert-template = <&ti_spl_template>; @@ -286,7 +274,7 @@ keyfile = "custMpk.pem"; }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; @@ -371,7 +359,7 @@ images { dm { ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/j721s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi index 6b521166575..57e966ea666 100644 --- a/arch/arm/dts/k3-j722s-binman.dtsi +++ b/arch/arm/dts/k3-j722s-binman.dtsi @@ -36,7 +36,6 @@ ti_fs_enc: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { @@ -47,7 +46,6 @@ sysfw_inner_cert: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { @@ -88,7 +86,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin"; type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { @@ -99,7 +96,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin"; type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { @@ -116,15 +112,6 @@ #define J722S_EVM_DTB "u-boot.dtb" &binman { - ti-dm { - filename = "ti-dm.bin"; - - blob-ext { - filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - ti-spl { insert-template = <&ti_spl_template>; @@ -137,7 +124,7 @@ }; dm: ti-dm { - filename = "ti-dm.bin"; + filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; diff --git a/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi index ede5d6e58f5..b1d79a3f64a 100644 --- a/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi @@ -43,17 +43,18 @@ #else // CONFIG_ARM64 &binman { - ti-dm { - filename = "ti-dm.bin"; - - blob-ext { - filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - tispl { insert-template = <&ti_spl>; + + fit { + images { + dm { + ti-dm { + filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + }; + }; }; u-boot { @@ -62,6 +63,16 @@ tispl-unsigned { insert-template = <&ti_spl_unsigned>; + + fit { + images { + dm { + ti-dm { + filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + }; + }; }; u-boot-unsigned { diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index 0553825b383..a7ce1ee2b03 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -39,7 +39,6 @@ ti_fs_enc: ti-fs-enc.bin { type = "blob-ext"; - optional; }; combined_tifs_cfg: combined-tifs-cfg.bin { @@ -49,7 +48,6 @@ sysfw_inner_cert: sysfw-inner-cert { type = "blob-ext"; - optional; }; combined_dm_cfg: combined-dm-cfg.bin { @@ -88,7 +86,6 @@ ti_fs_enc_fs: ti-fs-enc.bin { type = "blob-ext"; - optional; }; combined_tifs_cfg_fs: combined-tifs-cfg.bin { @@ -98,7 +95,6 @@ sysfw_inner_cert_fs: sysfw-inner-cert { type = "blob-ext"; - optional; }; combined_dm_cfg_fs: combined-dm-cfg.bin { @@ -135,7 +131,6 @@ ti_fs_gp: ti-fs-gp.bin { type = "blob-ext"; - optional; }; combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { @@ -165,8 +160,7 @@ keyfile = "custMpk.pem"; }; - dm: blob-ext { - filename = "ti-dm.bin"; + dm: ti-dm { }; }; @@ -254,8 +248,7 @@ fit { images { dm { - blob-ext { - filename = "ti-dm.bin"; + ti-dm { }; }; diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi index 8a60d7c6107..cc0b562d27e 100644 --- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi +++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi @@ -52,17 +52,18 @@ #else // CONFIG_ARM64 &binman { - ti-dm { - filename = "ti-dm.bin"; - - blob-ext { - filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - optional; - }; - }; - tispl { insert-template = <&ti_spl>; + + fit { + images { + dm { + ti-dm { + filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + }; + }; }; u-boot { @@ -71,6 +72,16 @@ tispl-unsigned { insert-template = <&ti_spl_unsigned>; + + fit { + images { + dm { + ti-dm { + filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + }; + }; }; u-boot-unsigned { diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts index 0eeffa78740..fc20438261c 100644 --- a/arch/arm/dts/k3-j784s4-r5-evm.dts +++ b/arch/arm/dts/k3-j784s4-r5-evm.dts @@ -10,3 +10,10 @@ #include "k3-j784s4-ddr.dtsi" #include "k3-j784s4-evm-u-boot.dtsi" #include "k3-j784s4-r5.dtsi" + +&tps659413 { + esm: esm { + compatible = "ti,tps659413-esm"; + bootph-pre-ram; + }; +}; diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index 2205caabc51..bb0078588fe 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -46,30 +46,6 @@ }; }; -#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM) -&binman { - rom { - filename = "u-boot.rom"; - size = <0x400000>; - pad-byte = <0xff>; - - mkimage { - args = "-n rk3288 -T rkspi"; - u-boot-spl { - }; - }; - u-boot-img { - offset = <0x20000>; - }; - u-boot { - offset = <0x300000>; - }; - fdtmap { - }; - }; -}; -#endif - &bus_intmem { ddr_sram: ddr-sram@1000 { compatible = "rockchip,rk3288-ddr-sram"; diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi index 4f9c59c6757..89093e2311c 100644 --- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi +++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi @@ -11,6 +11,14 @@ }; }; +#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) +&binman { + simple-bin-spi { + size = <0x400000>; + }; +}; +#endif + &dmc { logic-supply = <&vdd_logic>; rockchip,odt-disable-freq = <333000000>; diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi index 5517176aa4a..dfc7be4c621 100644 --- a/arch/arm/dts/rk3399-gru-u-boot.dtsi +++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi @@ -15,11 +15,13 @@ }; }; +#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) &binman { - rom { + simple-bin-spi { size = <0x800000>; }; }; +#endif &cros_ec { ec-interrupt = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 70f35b6c197..587eef9504e 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -29,41 +29,6 @@ }; }; -#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM) -&binman { - multiple-images; - rom { - filename = "u-boot.rom"; - size = <0x400000>; - pad-byte = <0xff>; - - mkimage { - args = "-n rk3399 -T rkspi"; - multiple-data-files; -#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL - rockchip-tpl { - }; -#elif defined(CONFIG_TPL) - u-boot-tpl { - }; -#endif - u-boot-spl { - }; - }; - fit { - type = "blob"; - filename = "u-boot.itb"; - offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>; - }; - u-boot { - offset = <0x300000>; - }; - fdtmap { - }; - }; -}; -#endif /* CONFIG_ROCKCHIP_SPI_IMAGE && CONFIG_HAS_ROM */ - &cru { bootph-all; }; diff --git a/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi b/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi new file mode 100644 index 00000000000..0c8e7018f13 --- /dev/null +++ b/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + +&rgb_led_r { + default-state = "off"; +}; + +&rgb_led_b { + default-state = "off"; +}; diff --git a/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi new file mode 100644 index 00000000000..afd33dd3248 --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi index c8c928c7e50..cc2feed6464 100644 --- a/arch/arm/dts/rockchip-u-boot.dtsi +++ b/arch/arm/dts/rockchip-u-boot.dtsi @@ -5,6 +5,36 @@ #include <config.h> +#ifdef CONFIG_ARM64 +#define FIT_ARCH "arm64" +#else +#define FIT_ARCH "arm" +#endif + +#if defined(CONFIG_SPL_GZIP) +#define FIT_UBOOT_COMP "gzip" +#elif defined(CONFIG_SPL_LZMA) +#define FIT_UBOOT_COMP "lzma" +#else +#define FIT_UBOOT_COMP "none" +#endif + +/* + * SHA256 should be enabled in SPL when signature validation is involved, + * CRC32 should only be used for basic checksum validation of FIT images. + */ +#if defined(CONFIG_SPL_FIT_SIGNATURE) +#if defined(CONFIG_SPL_SHA256) +#define FIT_HASH_ALGO "sha256" +#elif defined(CONFIG_SPL_CRC32) +#define FIT_HASH_ALGO "crc32" +#endif +#endif + +#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)) +#define HAS_FIT +#endif + / { binman: binman { multiple-images; @@ -13,6 +43,126 @@ #ifdef CONFIG_SPL &binman { +#ifdef HAS_FIT + fit_template: template-1 { + type = "fit"; +#ifdef CONFIG_ARM64 + description = "FIT image for U-Boot with bl31 (TF-A)"; +#else + description = "FIT image with OP-TEE"; +#endif + #address-cells = <1>; + fit,fdt-list = "of-list"; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + fit,align = <512>; + images { + u-boot { + description = "U-Boot"; + type = "standalone"; + os = "u-boot"; + arch = FIT_ARCH; + compression = FIT_UBOOT_COMP; + load = <CONFIG_TEXT_BASE>; + entry = <CONFIG_TEXT_BASE>; + u-boot-nodtb { + compress = FIT_UBOOT_COMP; + }; +#ifdef FIT_HASH_ALGO + hash { + algo = FIT_HASH_ALGO; + }; +#endif + }; + +#ifdef CONFIG_ARM64 + @atf-SEQ { + fit,operation = "split-elf"; + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = FIT_ARCH; + os = "arm-trusted-firmware"; + compression = "none"; + fit,load; + fit,entry; + fit,data; + + atf-bl31 { + }; +#ifdef FIT_HASH_ALGO + hash { + algo = FIT_HASH_ALGO; + }; +#endif + }; + @tee-SEQ { + fit,operation = "split-elf"; + description = "TEE"; + type = "tee"; + arch = FIT_ARCH; + os = "tee"; + compression = "none"; + fit,load; + fit,entry; + fit,data; + + tee-os { + optional; + }; +#ifdef FIT_HASH_ALGO + hash { + algo = FIT_HASH_ALGO; + }; +#endif + }; +#else /* !CONFIG_ARM64 */ + op-tee { + description = "OP-TEE"; + type = "tee"; + arch = FIT_ARCH; + os = "tee"; + compression = "none"; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + + tee-os { + }; +#ifdef FIT_HASH_ALGO + hash { + algo = FIT_HASH_ALGO; + }; +#endif + }; +#endif /* CONFIG_ARM64 */ + + @fdt-SEQ { + description = "fdt-NAME"; + compression = "none"; + type = "flat_dt"; +#ifdef FIT_HASH_ALGO + hash { + algo = FIT_HASH_ALGO; + }; +#endif + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + @config-SEQ { + description = "NAME.dtb"; + fdt = "fdt-SEQ"; +#ifdef CONFIG_ARM64 + fit,firmware = "atf-1", "u-boot"; +#else + fit,firmware = "op-tee", "u-boot"; +#endif + fit,loadables; + fit,compatible; + }; + }; + }; +#endif /* HAS_FIT */ + simple-bin { filename = "u-boot-rockchip.bin"; pad-byte = <0xff>; @@ -33,143 +183,15 @@ }; }; -#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)) - fit: fit { -#ifdef CONFIG_ARM64 - description = "FIT image for U-Boot with bl31 (TF-A)"; -#else - description = "FIT image with OP-TEE"; -#endif - #address-cells = <1>; - fit,fdt-list = "of-list"; +#ifdef HAS_FIT + fit { filename = "u-boot.itb"; - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; - fit,align = <512>; - offset = <CONFIG_SPL_PAD_TO>; - images { - u-boot { - description = "U-Boot"; - type = "standalone"; - os = "U-Boot"; -#ifdef CONFIG_ARM64 - arch = "arm64"; -#else - arch = "arm"; -#endif -#if defined(CONFIG_SPL_GZIP) - compression = "gzip"; -#elif defined(CONFIG_SPL_LZMA) - compression = "lzma"; -#else - compression = "none"; -#endif - load = <CONFIG_TEXT_BASE>; - entry = <CONFIG_TEXT_BASE>; - u-boot-nodtb { -#if defined(CONFIG_SPL_GZIP) - compress = "gzip"; -#elif defined(CONFIG_SPL_LZMA) - compress = "lzma"; -#endif - }; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif - }; - -#ifdef CONFIG_ARM64 - @atf-SEQ { - fit,operation = "split-elf"; - description = "ARM Trusted Firmware"; - type = "firmware"; - arch = "arm64"; - os = "arm-trusted-firmware"; - compression = "none"; - fit,load; - fit,entry; - fit,data; - - atf-bl31 { - }; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif - }; - @tee-SEQ { - fit,operation = "split-elf"; - description = "TEE"; - type = "tee"; - arch = "arm64"; - os = "tee"; - compression = "none"; - fit,load; - fit,entry; - fit,data; - - tee-os { - optional; - }; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif - }; -#else - op-tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm"; - os = "tee"; - compression = "none"; - load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; - - tee-os { - }; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif - }; -#endif - - @fdt-SEQ { - description = "fdt-NAME"; - compression = "none"; - type = "flat_dt"; -#ifdef CONFIG_SPL_FIT_SIGNATURE - hash { - algo = "sha256"; - }; -#endif - }; - }; - - configurations { - default = "@config-DEFAULT-SEQ"; - @config-SEQ { - description = "NAME.dtb"; - fdt = "fdt-SEQ"; -#ifdef CONFIG_ARM64 - fit,firmware = "atf-1", "u-boot"; -#else - fit,firmware = "op-tee", "u-boot"; -#endif - fit,loadables; - }; - }; - }; + insert-template = <&fit_template>; #else u-boot-img { +#endif offset = <CONFIG_SPL_PAD_TO>; }; -#endif }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE @@ -193,10 +215,9 @@ }; }; -#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE) +#ifdef HAS_FIT fit { - type = "blob"; - filename = "u-boot.itb"; + insert-template = <&fit_template>; #else u-boot-img { #endif diff --git a/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi new file mode 100644 index 00000000000..43dd3b993d5 --- /dev/null +++ b/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (c) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com> +// + +#include <stm32f769-disco-u-boot.dtsi> diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 8413264a73c..f677bb9a42a 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -30,6 +30,7 @@ <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>, <&clk_hse>; clock-names = "pclk", "px_clk", "ref"; + bootph-all; }; &fmc { diff --git a/arch/arm/dts/tegra20-lg-star.dts b/arch/arm/dts/tegra20-lg-star.dts new file mode 100644 index 00000000000..3045bc3135f --- /dev/null +++ b/arch/arm/dts/tegra20-lg-star.dts @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/input.h> + +#include "tegra20.dtsi" + +/ { + model = "LG Optimus 2X (P990)"; + compatible = "lg,star", "nvidia,tegra20"; + + chosen { + stdout-path = &uartb; + }; + + aliases { + i2c0 = &pwr_i2c; + i2c5 = &dcdc_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + crt { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + displaya { + nvidia,pins = "lcsn", "ld0", "ld1", "ld10", + "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ld2", + "ld3", "ld4", "ld5", "ld6", + "ld7", "ld8", "ld9", "ldc", + "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", + "lpw0", "lpw1", "lpw2", "lsc0", + "lsc1", "lsck", "lsda", "lsdi", + "lspi", "lvp0", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + + gmi { + nvidia,pins = "ata", "atc", "atd", "ate", + "gmb", "irrx", "irtx"; + nvidia,function = "gmi"; + }; + + hdmi { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2c { + nvidia,pins = "i2cp", "rm"; + nvidia,function = "i2c"; + }; + + i2c2 { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + + i2c3 { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + kbc { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbce", + "kbcf"; + nvidia,function = "kbc"; + }; + + owr { + nvidia,pins = "owc"; + nvidia,function = "owr"; + }; + + plla-out { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + + pllp-out4 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + + pwm { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + + pwr-on { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rtck { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + sdio2 { + nvidia,pins = "kbcd"; + nvidia,function = "sdio2"; + }; + + sdio3 { + nvidia,pins = "sdb", "sdc", "sdd", "slxa", + "slxd", "slxk", "slxc"; + nvidia,function = "sdio3"; + }; + + sdio4 { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + spi1 { + nvidia,pins = "uda"; + nvidia,function = "spi1"; + }; + + spi2 { + nvidia,pins = "spia", "spib", "spic"; + nvidia,function = "spi2"; + }; + + spi2-alt { + nvidia,pins = "spid", "spie", "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + + uarta { + nvidia,pins = "uaa", "uab"; + nvidia,function = "uarta"; + }; + + uartc { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + uartd { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + vi { + nvidia,pins = "dtc", "dtd"; + nvidia,function = "vi"; + }; + + vi-sensor-clk { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + conf-lsda { + nvidia,pins = "lsda", "owc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-ata { + nvidia,pins = "ata", "dtf", "gmb", "gmc", + "i2cp", "irrx", "kbca", "kbcc", + "kbcd", "kbce", "kbcf", "lcsn", + "ldc", "pta", "rm", "sdc", + "sdd", "spie", "spif", "spig", + "spih", "uaa", "uad", "uca", + "ucb", "pmce"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-crtp { + nvidia,pins = "crtp", "gpv", "hdint", "lhs", + "lm0", "lpw0", "lpw1", "lpw2", + "lsc1", "lsck", "lspi", "lvs", + "slxa", "slxd", "spdi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-atb { + nvidia,pins = "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "csus", "dap1", + "dap2", "dap3", "dap4", "ddc", + "dta", "dtb", "dte", "gma", + "gmd", "gme", "gpu", "gpu7", + "irtx", "kbcb", "lm1", "lsc0", + "lsdi", "lvp0", "pmc", "sdb", + "sdio1", "slxc", "spdo", "spia", + "spib", "spic", "uab", "uac", + "uda", "ck32", "ddrc", "pmca", + "pmcb", "pmcc", "pmcd", "xm2c", + "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-dtc { + nvidia,pins = "dtc", "dtd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", + "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", + "ld12", "ld13", "ld14", "ld15", + "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lpp", "lvp1", + "slxk", "spid"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + drive-sdio1 { + nvidia,pins = "drive_sdio1", "drive_vi1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + drive-i2c { + nvidia,pins = "drive_dbg", "drive_ddc", "drive_at1", + "drive_vi2", "drive_ao1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive-dap { + nvidia,pins = "drive_dap2", "drive_dap3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <46>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + + uartb: serial@70006040 { + clocks = <&tegra_car 7>; + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max8907@3c { + compatible = "maxim,max8907"; + reg = <0x3c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + maxim,system-power-controller; + + regulators { + vdd_1v8_vio: sd3 { + regulator-name = "vcc_1v8_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + iovcc_1v8_lcd: ldo3 { + regulator-name = "vcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + avdd_3v3_usb: ldo4 { + regulator-name = "avdd_3v3_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vcc_2v8_emmc"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + vdd_usd: ldo12 { + regulator-name = "vcc_2v8_sdio"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + vcc_2v8_lcd: ldo14 { + regulator-name = "vcc_2v8_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + }; + }; + }; + + dcdc_i2c: i2c-5 { + compatible = "i2c-gpio"; + + sda-gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>; + + i2c-gpio,delay-us = <5>; + i2c-gpio,timeout-ms = <100>; + + #address-cells = <1>; + #size-cells = <0>; + + aat2870: led-controller@60 { + compatible = "skyworks,aat2870"; + reg = <0x60>; + + enable-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + + backlight { + current-max-microamp = <27900000>; + }; + }; + }; + + micro_usb: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&avdd_3v3_usb>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + bridge: cpu-bridge { + compatible = "nvidia,tegra-8bit-cpu"; + + dc-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio TEGRA_GPIO(B, 3) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + + data-gpios = <&gpio TEGRA_GPIO(E, 0) GPIO_ACTIVE_HIGH>, + <&gpio TEGRA_GPIO(E, 1) GPIO_ACTIVE_HIGH>, + <&gpio TEGRA_GPIO(E, 2) GPIO_ACTIVE_HIGH>, + <&gpio TEGRA_GPIO(E, 3) GPIO_ACTIVE_HIGH>, + <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>, + <&gpio TEGRA_GPIO(E, 5) GPIO_ACTIVE_HIGH>, + <&gpio TEGRA_GPIO(E, 6) GPIO_ACTIVE_HIGH>, + <&gpio TEGRA_GPIO(E, 7) GPIO_ACTIVE_HIGH>; + + nvidia,init-sequence = <0x0000002c 0x0 0x0 0x00005000>; + + panel { + /* + * There are 2 rev of P990. One has Hitachi TX10D07VM0BAA + * panel and other has LG LH400WV3-SD04 panel. We are using + * Hitachi here but it is dynamically adjusted for the + * correct compatible. + */ + compatible = "hit,tx10d07vm0baa"; + + reset-gpios = <&gpio TEGRA_GPIO(V, 7) GPIO_ACTIVE_LOW>; + + avci-supply = <&vcc_2v8_lcd>; + iovcc-supply = <&iovcc_1v8_lcd>; + + backlight = <&aat2870>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(G, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(G, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + vdd_3v3_vbat: regulator-vbat { + compatible = "regulator-fixed"; + regulator-name = "vdd_vbat"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 0d7a5734616..1f669c72d00 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -76,6 +76,8 @@ #define MXC_CPU_IMX9111 0xCD /* dummy ID */ #define MXC_CPU_IMX9101 0xCE /* dummy ID */ +#define MXC_CPU_IMX95 0x1C1 /* dummy ID */ + #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 #define MXC_SOC_IMX8M 0x80 diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index 60d48b13b11..ffaf6b5f7d8 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -255,5 +255,15 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock void enable_usboh3_clk(unsigned char enable); int set_clk_enet(enum enet_freq type); int set_clk_eqos(enum enet_freq type); + +int imx_clk_scmi_enable(u32 clock_id, bool enable); +ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate); +ulong imx_clk_scmi_get_rate(u32 clock_id); +int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id); void set_arm_clk(ulong freq); + +int imx_clk_scmi_enable(u32 clock_id, bool enable); +ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate); +ulong imx_clk_scmi_get_rate(u32 clock_id); +int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id); #endif diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index ef9538bd42e..5127fe8f286 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -13,6 +13,7 @@ #define CCM_BASE_ADDR 0x44450000UL #define CCM_CCGR_BASE_ADDR 0x44458000UL #define SYSCNT_CTRL_BASE_ADDR 0x44290000 +#define SYSCNT_CMP_BASE_ADDR (SYSCNT_CTRL_BASE_ADDR + 0x10000) #define ANATOP_BASE_ADDR 0x44480000UL @@ -20,6 +21,11 @@ #define WDG4_BASE_ADDR 0x424a0000UL #define WDG5_BASE_ADDR 0x424b0000UL +#define GPIO2_BASE_ADDR 0x43810000UL +#define GPIO3_BASE_ADDR 0x43820000UL +#define GPIO4_BASE_ADDR 0x43840000UL +#define GPIO5_BASE_ADDR 0x43850000UL + #define FSB_BASE_ADDR 0x47510000UL #define ANATOP_BASE_ADDR 0x44480000UL diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index e4bf6a63424..df2148a53c7 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -12,6 +12,7 @@ enum imx9_soc_voltage_mode { VOLT_LOW_DRIVE = 0, VOLT_NOMINAL_DRIVE, VOLT_OVER_DRIVE, + VOLT_SUPER_OVER_DRIVE, }; void soc_power_init(void); diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 894d3a40b09..0111b3a0ded 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -934,21 +934,21 @@ enum { RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT), RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT), - GMAC_SPEED_SHIFT = 0xa, - GMAC_SPEED_MASK = 1, - GMAC_SPEED_10M = 0, - GMAC_SPEED_100M, + RK3288_GMAC_SPEED_SHIFT = 0xa, + RK3288_GMAC_SPEED_MASK = (1 << RK3288_GMAC_SPEED_SHIFT), + RK3288_GMAC_SPEED_10M = (0 << RK3288_GMAC_SPEED_SHIFT), + RK3288_GMAC_SPEED_100M = (1 << RK3288_GMAC_SPEED_SHIFT), - GMAC_FLOWCTRL_SHIFT = 0x9, - GMAC_FLOWCTRL_MASK = 1, + RK3288_GMAC_FLOWCTRL_SHIFT = 0x9, + RK3288_GMAC_FLOWCTRL_MASK = (1 << RK3288_GMAC_FLOWCTRL_SHIFT), RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6, RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), - HOST_REMAP_SHIFT = 0x5, - HOST_REMAP_MASK = 1 + RK3288_HOST_REMAP_SHIFT = 0x5, + RK3288_HOST_REMAP_MASK = (1 << RK3288_HOST_REMAP_SHIFT), }; /* GRF_SOC_CON2 */ diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index 2fd07403bdf..ab12cc9c7d0 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -448,10 +448,19 @@ enum win_color_depth_id { #define LVS_OUTPUT_POLARITY_LOW BIT(28) #define LSC0_OUTPUT_POLARITY_LOW BIT(24) +/* DC_COM_PIN_OUTPUT_SELECT6 0x31a */ +#define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) /* 100b */ + /* DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 */ #define H_PULSE0_ENABLE BIT(8) #define H_PULSE1_ENABLE BIT(10) #define H_PULSE2_ENABLE BIT(12) +#define V_PULSE0_ENABLE BIT(16) +#define V_PULSE1_ENABLE BIT(18) +#define V_PULSE2_ENABLE BIT(19) +#define V_PULSE3_ENABLE BIT(20) +#define M0_ENABLE BIT(24) +#define M1_ENABLE BIT(26) /* DC_DISP_DISP_WIN_OPTIONS 0x402 */ #define CURSOR_ENABLE BIT(16) @@ -525,6 +534,28 @@ enum { BASE_COLOR_SIZE_888, }; +/* DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 */ +#define SC0_H_QUALIFIER_SHIFT 0 +#define SC1_H_QUALIFIER_SHIFT 16 +enum { + SC_H_QUALIFIER_DISABLE, + SC_H_QUALIFIER_NONE, + SC_H_QUALIFIER_HACTIVE, + SC_H_QUALIFIER_EXT_HACTIVE, + SC_H_QUALIFIER_HPULSE, + SC_H_QUALIFIER_EXT_HPULSE, +}; +#define SC0_V_QUALIFIER_SHIFT 3 +#define SC1_V_QUALIFIER_SHIFT 19 +enum { + SC_V_QUALIFIER_NONE, + SC_V_QUALIFIER_RSVD, + SC_V_QUALIFIER_VACTIVE, + SC_V_QUALIFIER_EXT_VACTIVE, + SC_V_QUALIFIER_VPULSE, + SC_V_QUALIFIER_EXT_VPULSE, +}; + /* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ #define DE_SELECT_SHIFT 0 #define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) @@ -541,6 +572,23 @@ enum { DE_CONTROL_ACTIVE_BLANK, }; +/* DC_DISP_INIT_SEQ_CONTROL 0x442 */ +#define SEND_INIT_SEQUENCE BIT(0) +#define INIT_SEQUENCE_MODE_SPI BIT(1) +#define INIT_SEQUENCE_MODE_PLCD 0x0 +#define INIT_SEQ_DC_SIGNAL_SHIFT 4 +#define INIT_SEQ_DC_SIGNAL_MASK (0x7 << INIT_SEQ_DC_SIGNAL_SHIFT) +enum { + NO_DC_SIGNAL, + DC_SIGNAL_VSYNC, + DC_SIGNAL_VPULSE0, + DC_SIGNAL_VPULSE1, + DC_SIGNAL_VPULSE2, + DC_SIGNAL_VPULSE3, +}; +#define INIT_SEQ_DC_CONTROL_SHIFT 7 +#define FRAME_INIT_SEQ_CYCLES_SHIFT 8 + /* DC_WIN_WIN_OPTIONS 0x700 */ #define H_DIRECTION BIT(0) enum { diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 109a806852a..0780f99b49a 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -97,6 +97,8 @@ struct bd_info; #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302)) #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301)) +#define is_imx95() (is_cpu_type(MXC_CPU_IMX95)) + #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121)) #define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111)) #define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101)) @@ -216,6 +218,43 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev); u32 rom_api_download_image(u8 *dest, u32 offset, u32 size); u32 rom_api_query_boot_infor(u32 info_type, u32 *info); +#if IS_ENABLED(CONFIG_SCMI_FIRMWARE) +typedef struct rom_passover { + u16 tag; // Tag + u8 len; // Fixed value of 0x80 + u8 ver; // Version + u32 boot_mode; // Boot mode + u32 card_addr_mode; // SD card address mode + u32 bad_blks_of_img_set0; // NAND bad block count skipped 1 + u32 ap_mu_id; // AP MU ID + u32 bad_blks_of_img_set1; // NAND bad block count skipped 1 + u8 boot_stage; // Boot stage + u8 img_set_sel; // Image set booted from + u8 rsv0[2]; // Reserved + u32 img_set_end; // Offset of Image End + u32 rom_version; // ROM version + u8 boot_dev_state; // Boot device state + u8 boot_dev_inst; // Boot device type + u8 boot_dev_type; // Boot device instance + u8 rsv1; // Reserved + u32 dev_page_size; // Boot device page size + u32 cnt_header_ofs; // Container header offset + u32 img_ofs; // Image offset +} __packed rom_passover_t; + +/** + * struct scmi_rom_passover_out - Response payload for ROM_PASSOVER_GET command + * @status: SCMI clock ID + * @attributes: Attributes of the targets clock state + */ +struct scmi_rom_passover_get_out { + u32 status; + u32 numPassover; + u32 passover[(sizeof(rom_passover_t) + 8) / 4]; +}; + +#endif + /* For i.MX ULP */ #define BT0CFG_LPBOOT_MASK 0x1 #define BT0CFG_DUALBOOT_MASK 0x2 diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 2644a04a622..2604c5a710e 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -6,6 +6,7 @@ #include <dm.h> #include <dm/uclass-internal.h> #include <efi_loader.h> +#include <env.h> #include <lmb.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 134e42028c3..e4014226582 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -180,7 +180,7 @@ config DDRMC_VF610_CALIBRATION config IMX8_ROMAPI def_bool y - depends on IMX8MN || IMX8MP || IMX8ULP || IMX9 + depends on IMX8MN || IMX8MP || IMX8ULP || IMX91 || IMX93 config SPL_IMX_ROMAPI_LOADADDR hex "Default load address to load image through ROM API" diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 2afe9d38a06..f84e23f4b2a 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -41,6 +41,52 @@ #define FUSE_IMG_SET_OFF_WORD 720 #endif +#define MAX_V2X_CTNR_IMG_NUM (4) +#define MIN_V2X_CTNR_IMG_NUM (2) + +#define IMG_FLAGS_IMG_TYPE_SHIFT (0u) +#define IMG_FLAGS_IMG_TYPE_MASK (0xfU) +#define IMG_FLAGS_IMG_TYPE(x) (((x) & IMG_FLAGS_IMG_TYPE_MASK) >> \ + IMG_FLAGS_IMG_TYPE_SHIFT) + +#define IMG_FLAGS_CORE_ID_SHIFT (4u) +#define IMG_FLAGS_CORE_ID_MASK (0xf0U) +#define IMG_FLAGS_CORE_ID(x) (((x) & IMG_FLAGS_CORE_ID_MASK) >> \ + IMG_FLAGS_CORE_ID_SHIFT) + +#define IMG_TYPE_V2X_PRI_FW (0x0Bu) /* Primary V2X FW */ +#define IMG_TYPE_V2X_SND_FW (0x0Cu) /* Secondary V2X FW */ + +#define CORE_V2X_PRI 9 +#define CORE_V2X_SND 10 + +static bool is_v2x_fw_container(ulong addr) +{ + struct container_hdr *phdr; + struct boot_img_t *img_entry; + + phdr = (struct container_hdr *)addr; + if (phdr->tag != 0x87 || phdr->version != 0x0) { + debug("Wrong container header\n"); + return false; + } + + if (phdr->num_images >= MIN_V2X_CTNR_IMG_NUM && phdr->num_images <= MAX_V2X_CTNR_IMG_NUM) { + img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr)); + + if (IMG_FLAGS_IMG_TYPE(img_entry->hab_flags) == IMG_TYPE_V2X_PRI_FW && + IMG_FLAGS_CORE_ID(img_entry->hab_flags) == CORE_V2X_PRI) { + img_entry++; + + if (IMG_FLAGS_IMG_TYPE(img_entry->hab_flags) == IMG_TYPE_V2X_SND_FW && + IMG_FLAGS_CORE_ID(img_entry->hab_flags) == CORE_V2X_SND) + return true; + } + } + + return false; +} + int get_container_size(ulong addr, u16 *header_length) { struct container_hdr *phdr; @@ -83,7 +129,7 @@ int get_container_size(ulong addr, u16 *header_length) return max_offset; } -static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, u16 *header_length) +static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, u16 *header_length, bool *v2x_cntr) { u8 *buf = malloc(CONTAINER_HDR_ALIGNMENT); int ret = 0; @@ -150,6 +196,9 @@ static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, ret = get_container_size((ulong)buf, header_length); + if (v2x_cntr) + *v2x_cntr = is_v2x_fw_container((ulong)buf); + free(buf); return ret; @@ -231,45 +280,67 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type) return offset; } -static int get_imageset_end(void *dev, int dev_type) +static ulong get_imageset_end(void *dev, int dev_type) { - unsigned long offset1 = 0, offset2 = 0; - int value_container[2]; + unsigned long offset[3] = {}; + int value_container[3] = {}; u16 hdr_length; + bool v2x_fw = false; - offset1 = get_boot_device_offset(dev, dev_type); - offset2 = CONTAINER_HDR_ALIGNMENT + offset1; + offset[0] = get_boot_device_offset(dev, dev_type); - value_container[0] = get_dev_container_size(dev, dev_type, offset1, &hdr_length); + value_container[0] = get_dev_container_size(dev, dev_type, offset[0], &hdr_length, NULL); if (value_container[0] < 0) { printf("Parse seco container failed %d\n", value_container[0]); - return value_container[0]; + return 0; } debug("seco container size 0x%x\n", value_container[0]); - value_container[1] = get_dev_container_size(dev, dev_type, offset2, &hdr_length); - if (value_container[1] < 0) { - debug("Parse scu container failed %d, only seco container\n", - value_container[1]); - /* return seco container total size */ - return value_container[0] + offset1; + if (is_imx95()) { + offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0]; + + value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw); + if (value_container[1] < 0) { + printf("Parse v2x container failed %d\n", value_container[1]); + return value_container[0] + offset[0]; /* return seco container total size */ + } + + if (v2x_fw) { + debug("v2x container size 0x%x\n", value_container[1]); + offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[1]; + } else { + printf("no v2x container included\n"); + offset[2] = offset[1]; + } + } else { + /* Skip offset[1] */ + offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0]; + } + + value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL); + if (value_container[2] < 0) { + debug("Parse scu container image failed %d, only seco container\n", value_container[2]); + if (is_imx95()) + return value_container[1] + offset[1]; /* return seco + v2x container total size */ + else + return value_container[0] + offset[0]; /* return seco container total size */ } - debug("scu container size 0x%x\n", value_container[1]); + debug("scu container size 0x%x\n", value_container[2]); - return value_container[1] + offset2; + return value_container[2] + offset[2]; } #ifdef CONFIG_SPL_SPI_LOAD unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) { - int end; + ulong end; end = get_imageset_end(flash, QSPI_DEV); end = ROUND(end, SZ_1K); - printf("Load image from QSPI 0x%x\n", end); + printf("Load image from QSPI 0x%lx\n", end); return end; } @@ -279,12 +350,12 @@ unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) { - int end; + ulong end; end = get_imageset_end(mmc, MMC_DEV); end = ROUND(end, SZ_1K); - printf("Load image from MMC/SD 0x%x\n", end); + printf("Load image from MMC/SD 0x%lx\n", end); return end / mmc->read_bl_len; } @@ -312,12 +383,12 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc) #ifdef CONFIG_SPL_NAND_SUPPORT uint32_t spl_nand_get_uboot_raw_page(void) { - int end; + ulong end; end = get_imageset_end((void *)NULL, NAND_DEV); end = ROUND(end, SZ_16K); - printf("Load image from NAND 0x%x\n", end); + printf("Load image from NAND 0x%lx\n", end); return end; } @@ -326,7 +397,7 @@ uint32_t spl_nand_get_uboot_raw_page(void) #ifdef CONFIG_SPL_NOR_SUPPORT unsigned long spl_nor_get_uboot_base(void) { - int end; + ulong end; /* Calculate the image set end, * if it is less than CFG_SYS_UBOOT_BASE(0x8281000), @@ -339,7 +410,7 @@ unsigned long spl_nor_get_uboot_base(void) else end = ROUND(end, SZ_1K); - printf("Load image from NOR 0x%x\n", end); + printf("Load image from NOR 0x%lx\n", end); return end; } diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 567e8e9e81a..3cdb71a2528 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_IMX_HAB) +#if IS_ENABLED(CONFIG_IMX_HAB) struct imx_fuse const imx_sec_config_fuse = { .bank = 1, .word = 3, @@ -52,7 +52,7 @@ struct imx_fuse const imx_field_return_fuse = { int timer_init(void) { -#ifdef CONFIG_XPL_BUILD +#if IS_ENABLED(CONFIG_XPL_BUILD) struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); @@ -110,7 +110,7 @@ void set_wdog_reset(struct wdog_regs *wdog) setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); } -#ifdef CONFIG_ARMV8_PSCI +#if IS_ENABLED(CONFIG_ARMV8_PSCI) #define PTE_MAP_NS PTE_BLOCK_NS #else #define PTE_MAP_NS 0 @@ -700,11 +700,11 @@ int arch_cpu_init(void) return 0; } -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) struct rom_api *g_rom_api = (struct rom_api *)0x980; #endif -#if defined(CONFIG_IMX8M) +#if IS_ENABLED(CONFIG_IMX8M) #include <spl.h> int imx8m_detect_secondary_image_boot(void) { @@ -790,8 +790,8 @@ int boot_mode_getprisec(void) } #endif -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) -#ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) #define IMG_CNTN_SET1_OFFSET GENMASK(22, 19) unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) @@ -826,7 +826,7 @@ unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, return raw_sect; } -#endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */ +#endif /* CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */ #endif bool is_usb_boot(void) @@ -834,7 +834,7 @@ bool is_usb_boot(void) return get_boot_device() == USB_BOOT; } -#ifdef CONFIG_OF_SYSTEM_SETUP +#if IS_ENABLED(CONFIG_OF_SYSTEM_SETUP) bool check_fdt_new_path(void *blob) { const char *soc_path = "/soc@0"; @@ -880,7 +880,7 @@ add_status: return 0; } -#ifdef CONFIG_IMX8MQ +#if IS_ENABLED(CONFIG_IMX8MQ) bool check_dcss_fused(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -1026,7 +1026,7 @@ int disable_vpu_nodes(void *blob) return -EPERM; } -#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +#if IS_ENABLED(CONFIG_IMX8MN_LOW_DRIVE_MODE) static int low_drive_gpu_freq(void *blob) { static const char *nodes_path_8mn[] = { @@ -1311,7 +1311,7 @@ int ft_system_setup(void *blob, struct bd_info *bd) "/cpus/cpu@3", }; -#ifdef CONFIG_IMX8MQ +#if IS_ENABLED(CONFIG_IMX8MQ) int i = 0; int rc; int nodeoff; @@ -1387,7 +1387,7 @@ usb_modify_speed: if (is_imx8md()) disable_cpu_nodes(blob, nodes_path, 2, 4); -#elif defined(CONFIG_IMX8MM) +#elif IS_ENABLED(CONFIG_IMX8MM) if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl()) disable_vpu_nodes(blob); @@ -1396,10 +1396,10 @@ usb_modify_speed: else if (is_imx8mms() || is_imx8mmsl()) disable_cpu_nodes(blob, nodes_path, 3, 4); -#elif defined(CONFIG_IMX8MN) +#elif IS_ENABLED(CONFIG_IMX8MN) if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl()) disable_gpu_nodes(blob); -#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +#if IS_ENABLED(CONFIG_IMX8MN_LOW_DRIVE_MODE) else { int ldm_gpu = low_drive_gpu_freq(blob); @@ -1415,7 +1415,7 @@ usb_modify_speed: else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) disable_cpu_nodes(blob, nodes_path, 3, 4); -#elif defined(CONFIG_IMX8MP) +#elif IS_ENABLED(CONFIG_IMX8MP) if (is_imx8mpul()) { /* Disable GPU */ disable_gpu_nodes(blob); @@ -1471,7 +1471,7 @@ void reset_cpu(void) } #endif -#if defined(CONFIG_ARCH_MISC_INIT) +#if IS_ENABLED(CONFIG_ARCH_MISC_INIT) int arch_misc_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { @@ -1487,8 +1487,8 @@ int arch_misc_init(void) } #endif -#if defined(CONFIG_XPL_BUILD) -#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) +#if IS_ENABLED(CONFIG_XPL_BUILD) +#if IS_ENABLED(CONFIG_IMX8MQ) || IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) bool serror_need_skip = true; void do_error(struct pt_regs *pt_regs) @@ -1523,7 +1523,7 @@ void do_error(struct pt_regs *pt_regs) #endif #endif -#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#if IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP) enum env_location arch_env_get_location(enum env_operation op, int prio) { enum boot_device dev = get_boot_device(); @@ -1571,7 +1571,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio) #endif -#ifdef CONFIG_IMX_BOOTAUX +#if IS_ENABLED(CONFIG_IMX_BOOTAUX) const struct rproc_att hostmap[] = { /* aux core , host core, size */ { 0x00000000, 0x007e0000, 0x00020000 }, diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 1ccdb1cf64f..e6cafdcd813 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -24,6 +24,13 @@ config IMX91 select IMX9 select ARMV8_SPL_EXCEPTION_VECTORS +config IMX95 + bool + select ARMV8_SPL_EXCEPTION_VECTORS + select IMX9 + select DM_MAILBOX + select SCMI_FIRMWARE + select SPL_IMX_CONTAINER_USE_TRAMPOLINE config SYS_SOC default "imx9" @@ -66,9 +73,17 @@ config TARGET_PHYCORE_IMX93 bool "phycore_imx93" select IMX93 select IMX9_LPDDR4X + imply OF_UPSTREAM select OF_BOARD_FIXUP select OF_BOARD_SETUP +config TARGET_IMX95_19X19_EVK + bool "imx95_19x19_evk" + select IMX95 + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM + endchoice source "board/freescale/imx91_evk/Kconfig" @@ -76,6 +91,7 @@ source "board/freescale/imx93_evk/Kconfig" source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" +source "board/freescale/imx95_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index 45a9105a75a..53cc97c6b47 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -3,8 +3,13 @@ # Copyright 2022 NXP obj-y += lowlevel_init.o + +ifeq ($(CONFIG_SCMI_FIRMWARE),y) +obj-y += scmi/ +else obj-y += soc.o clock.o clock_root.o trdc.o +endif -#ifndef CONFIG_XPL_BUILD +ifneq ($(CONFIG_SPL_BUILD),y) obj-y += imx_bootaux.o -#endif +endif
\ No newline at end of file diff --git a/arch/arm/mach-imx/imx9/scmi/Makefile b/arch/arm/mach-imx/imx9/scmi/Makefile new file mode 100644 index 00000000000..4534db08d28 --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2025 NXP + +obj-y += soc.o +obj-y += clock_scmi.o clock.o diff --git a/arch/arm/mach-imx/imx9/scmi/clock.c b/arch/arm/mach-imx/imx9/scmi/clock.c new file mode 100644 index 00000000000..6e6541eaa31 --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/clock.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include <asm/arch/clock.h> +#include <dm/uclass.h> +#include <scmi_agent.h> +#include "../../../../../dts/upstream/src/arm64/freescale/imx95-clock.h" + +u32 get_arm_core_clk(void) +{ + u32 val; + + val = imx_clk_scmi_get_rate(IMX95_CLK_SEL_A55C0); + if (val) + return val; + return imx_clk_scmi_get_rate(IMX95_CLK_A55); +} + +void init_uart_clk(u32 index) +{ + u32 clock_id; + + switch (index) { + case 0: + clock_id = IMX95_CLK_LPUART1; + break; + case 1: + clock_id = IMX95_CLK_LPUART2; + break; + case 2: + clock_id = IMX95_CLK_LPUART3; + break; + default: + return; + } + + /* 24MHz */ + imx_clk_scmi_enable(clock_id, false); + imx_clk_scmi_set_parent(clock_id, IMX95_CLK_24M); + imx_clk_scmi_set_rate(clock_id, 24000000); + imx_clk_scmi_enable(clock_id, true); +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_arm_core_clk(); + case MXC_IPG_CLK: + return imx_clk_scmi_get_rate(IMX95_CLK_BUSWAKEUP); + case MXC_CSPI_CLK: + return imx_clk_scmi_get_rate(IMX95_CLK_LPSPI1); + case MXC_ESDHC_CLK: + return imx_clk_scmi_get_rate(IMX95_CLK_USDHC1); + case MXC_ESDHC2_CLK: + return imx_clk_scmi_get_rate(IMX95_CLK_USDHC2); + case MXC_ESDHC3_CLK: + return imx_clk_scmi_get_rate(IMX95_CLK_USDHC3); + case MXC_UART_CLK: + return imx_clk_scmi_get_rate(IMX95_CLK_LPUART1); + case MXC_FLEXSPI_CLK: + return imx_clk_scmi_get_rate(IMX95_CLK_FLEXSPI1); + default: + return -1; + }; + + return -1; +}; diff --git a/arch/arm/mach-imx/imx9/scmi/clock_scmi.c b/arch/arm/mach-imx/imx9/scmi/clock_scmi.c new file mode 100644 index 00000000000..fa15b5f8df9 --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/clock_scmi.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <dm/uclass.h> +#include <scmi_agent.h> + +int imx_clk_scmi_enable(u32 clock_id, bool enable) +{ + struct scmi_clk_state_in in = { + .clock_id = clock_id, + .attributes = (enable) ? 1 : 0, + }; + struct scmi_clk_state_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, + SCMI_CLOCK_CONFIG_SET, + in, out); + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + + return scmi_to_linux_errno(out.status); +} + +ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate) +{ + struct scmi_clk_rate_set_in in = { + .clock_id = clock_id, + .flags = SCMI_CLK_RATE_ROUND_CLOSEST, + .rate_lsb = (u32)rate, + .rate_msb = (u32)((u64)rate >> 32), + }; + struct scmi_clk_rate_set_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, + SCMI_CLOCK_RATE_SET, + in, out); + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret < 0) + return ret; + + ret = scmi_to_linux_errno(out.status); + if (ret < 0) + return ret; + + struct scmi_clk_rate_get_in in_rate = { + .clock_id = clock_id, + }; + struct scmi_clk_rate_get_out out_rate; + + msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, SCMI_CLOCK_RATE_GET, in_rate, out_rate); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret < 0) + return ret; + + ret = scmi_to_linux_errno(out_rate.status); + if (ret < 0) + return ret; + + return (ulong)(((u64)out_rate.rate_msb << 32) | out_rate.rate_lsb); +} + +ulong imx_clk_scmi_get_rate(u32 clock_id) +{ + struct scmi_clk_rate_get_in in = { + .clock_id = clock_id, + }; + struct scmi_clk_rate_get_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, + SCMI_CLOCK_RATE_GET, + in, out); + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret < 0) + return ret; + + ret = scmi_to_linux_errno(out.status); + if (ret < 0) + return ret; + + return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb); +} + +int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id) +{ + struct scmi_clk_parent_set_in in = { + .clock_id = clock_id, + .parent_clk = parent_id, + }; + struct scmi_clk_parent_set_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, + SCMI_CLOCK_PARENT_SET, + in, out); + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret < 0) + return ret; + + ret = scmi_to_linux_errno(out.status); + if (ret < 0 && ret != -EACCES) + printf("%s: %d, clock_id %u\n", __func__, ret, clock_id); + + return ret; +} diff --git a/arch/arm/mach-imx/imx9/scmi/container.cfg b/arch/arm/mach-imx/imx9/scmi/container.cfg new file mode 100644 index 00000000000..441d9beedd1 --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/container.cfg @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +BOOT_FROM SD +SOC_TYPE IMX9 +CONTAINER +IMAGE A55 bl31.bin 0x8a200000 +IMAGE A55 u-boot.bin CONFIG_TEXT_BASE diff --git a/arch/arm/mach-imx/imx9/scmi/imximage.cfg b/arch/arm/mach-imx/imx9/scmi/imximage.cfg new file mode 100644 index 00000000000..6af1c4ba628 --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/imximage.cfg @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +BOOT_FROM SD +SOC_TYPE IMX9 +APPEND mx95a0-ahab-container.img +CONTAINER +IMAGE OEI m33-oei-ddrfw.bin 0x1ffc0000 +HOLD 0x10000 +IMAGE OEI oei-m33-tcm.bin 0x1ffc0000 +IMAGE M33 m33_image.bin 0x1ffc0000 +IMAGE A55 spl/u-boot-spl.bin 0x20480000 +DUMMY_V2X 0x8b000000 diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c new file mode 100644 index 00000000000..d2b0455bff9 --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -0,0 +1,749 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/sys_proto.h> +#include <asm/armv8/mmu.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/setup.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <env_internal.h> +#include <fuse.h> +#include <imx_thermal.h> +#include <linux/iopoll.h> +#include <scmi_agent.h> + +DECLARE_GLOBAL_DATA_PTR; + +static rom_passover_t rom_passover_data = {0}; + +uint32_t scmi_get_rom_data(rom_passover_t *rom_data) +{ + /* Read ROM passover data */ + struct scmi_rom_passover_get_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC, + .message_id = SCMI_MISC_ROM_PASSOVER_GET, + .in_msg = (u8 *)NULL, + .in_msg_sz = 0, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret == 0 && out.status == 0) { + memcpy(rom_data, (struct rom_passover_t *)out.passover, sizeof(rom_passover_t)); + } else { + printf("Failed to get ROM passover data, scmi_err = %d, size_of(out) = %ld\n", + out.status, sizeof(out)); + return -EINVAL; + } + + return 0; +} + +#if IS_ENABLED(CONFIG_ENV_IS_IN_MMC) +__weak int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_get_env_dev(void) +{ + int ret; + u16 boot_type; + u8 boot_instance; + + volatile gd_t *pgd = gd; + rom_passover_t *rdata; + +#if IS_ENABLED(CONFIG_XPL_BUILD) + rdata = &rom_passover_data; +#else + rom_passover_t rom_data = {0}; + + if (!pgd->reloc_off) + rdata = &rom_data; + else + rdata = &rom_passover_data; +#endif + if (rdata->tag == 0) { + ret = scmi_get_rom_data(rdata); + if (ret != 0) { + puts("SCMI: failure at rom_boot_info\n"); + return CONFIG_SYS_MMC_ENV_DEV; + } + } + boot_type = rdata->boot_dev_type; + boot_instance = rdata->boot_dev_inst; + set_gd(pgd); + + debug("boot_type %d, instance %d\n", boot_type, boot_instance); + + /* If not boot from sd/mmc, use default value */ + if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC) + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); + + return board_mmc_get_env_dev(boot_instance); +} +#endif + +u32 get_cpu_speed_grade_hz(void) +{ + u32 speed, max_speed; + int ret; + u32 val, word, offset; + + word = 17; + offset = 14; + + ret = fuse_read(word / 8, word % 8, &val); + if (ret) + val = 0; /* If read fuse failed, return as blank fuse */ + + val >>= offset; + val &= 0xf; + + max_speed = 2300000000; + speed = max_speed - val * 100000000; + + if (is_imx95()) + max_speed = 2000000000; + + /* In case the fuse of speed grade not programmed */ + if (speed > max_speed) + speed = max_speed; + + return speed; +} + +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + int ret; + u32 val, word, offset; + + word = 17; + offset = 12; + + ret = fuse_read(word / 8, word % 8, &val); + if (ret) + val = 0; /* If read fuse failed, return as blank fuse */ + + val >>= offset; + val &= 0x3; + + if (minc && maxc) { + if (val == TEMP_AUTOMOTIVE) { + *minc = -40; + *maxc = 125; + } else if (val == TEMP_INDUSTRIAL) { + *minc = -40; + *maxc = 105; + } else if (val == TEMP_EXTCOMMERCIAL) { + *minc = -20; + *maxc = 105; + } else { + *minc = 0; + *maxc = 95; + } + } + return val; +} + +static void set_cpu_info(struct ele_get_info_data *info) +{ + gd->arch.soc_rev = info->soc; + gd->arch.lifecycle = info->lc; + memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); +} + +u32 get_cpu_rev(void) +{ + u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; + + return (MXC_CPU_IMX95 << 12) | (CHIP_REV_1_0 + rev); +} + +#define UNLOCK_WORD 0xD928C520 +#define REFRESH_WORD 0xB480A602 + +static void disable_wdog(void __iomem *wdog_base) +{ + u32 val_cs = readl(wdog_base + 0x00); + int ret = 0; + + if (!(val_cs & 0x80)) + return; + + /* default is 32bits cmd */ + writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */ + + if (!(val_cs & 0x800)) { + writel(UNLOCK_WORD, (wdog_base + 0x04)); + while (!(readl(wdog_base + 0x00) & 0x800)) + ; + } + writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ + writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ + writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */ + + ret = readl_poll_timeout(wdog_base, val_cs, val_cs & 0x400, 100000); + if (ret < 0) + debug("%s timeout\n", __func__); +} + +static struct mm_region imx9_mem_map[] = { + { + /* M7 TCM */ + .virt = 0x203c0000UL, + .phys = 0x203c0000UL, + .size = 0x80000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OCRAM */ + .virt = 0x20480000UL, + .phys = 0x20480000UL, + .size = 0xA0000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* AIPS */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Flexible Serial Peripheral Interface */ + .virt = 0x28000000UL, + .phys = 0x28000000UL, + .size = 0x8000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DRAM1 */ + .virt = PHYS_SDRAM, + .phys = PHYS_SDRAM, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { +#ifdef PHYS_SDRAM_2_SIZE + /* DRAM2 */ + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = PHYS_SDRAM_2_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { +#endif + /* empty entry to split table entry 5 if needed when TEEs are used */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = imx9_mem_map; + +static unsigned int imx9_find_dram_entry_in_mem_map(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(imx9_mem_map); i++) + if (imx9_mem_map[i].phys == CFG_SYS_SDRAM_BASE) + return i; + + hang(); /* Entry not found, this must never happen. */ +} + +void enable_caches(void) +{ + /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch + * If OPTEE does not run, still update the MMU table according to dram banks structure + * to set correct dram size from board_phys_sdram_size + */ + int i = 0; + /* + * please make sure that entry initial value matches + * imx9_mem_map for DRAM1 + */ + int entry = imx9_find_dram_entry_in_mem_map(); + u64 attrs = imx9_mem_map[entry].attrs; + + while (i < CONFIG_NR_DRAM_BANKS && + entry < ARRAY_SIZE(imx9_mem_map)) { + if (gd->bd->bi_dram[i].start == 0) + break; + imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start; + imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start; + imx9_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx9_mem_map[entry].attrs = attrs; + debug("Added memory mapping (%d): %llx %llx\n", entry, + imx9_mem_map[entry].phys, imx9_mem_map[entry].size); + i++; entry++; + } + + icache_enable(); + dcache_enable(); +} + +__weak int board_phys_sdram_size(phys_size_t *size) +{ + phys_size_t start, end; + phys_size_t val; + + if (!size) + return -EINVAL; + + val = readl(REG_DDR_CS0_BNDS); + start = (val >> 16) << 24; + end = (val & 0xFFFF); + end = end ? end + 1 : 0; + end = end << 24; + *size = end - start; + + val = readl(REG_DDR_CS1_BNDS); + start = (val >> 16) << 24; + end = (val & 0xFFFF); + end = end ? end + 1 : 0; + end = end << 24; + *size += end - start; + + return 0; +} + +int dram_init(void) +{ + phys_size_t sdram_size; + int ret; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* rom_pointer[1] contains the size of TEE occupies */ + if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) + gd->ram_size = sdram_size - rom_pointer[1]; + else + gd->ram_size = sdram_size; + + return 0; +} + +int dram_init_banksize(void) +{ + int bank = 0; + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size, sdram_b2_size; + + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) { + sdram_b1_size = 0x100000000UL - PHYS_SDRAM; + sdram_b2_size = sdram_size - sdram_b1_size; + } else { + sdram_b1_size = sdram_size; + sdram_b2_size = 0; + } + + gd->bd->bi_dram[bank].start = PHYS_SDRAM; + if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) { + phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; + phys_size_t optee_size = (size_t)rom_pointer[1]; + + gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough\n"); + return -1; + } + + gd->bd->bi_dram[bank].start = optee_start + optee_size; + gd->bd->bi_dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->bd->bi_dram[bank].start; + } + } else { + gd->bd->bi_dram[bank].size = sdram_b1_size; + } + + if (sdram_b2_size) { + if (++bank >= CONFIG_NR_DRAM_BANKS) { + puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); + return -1; + } + gd->bd->bi_dram[bank].start = 0x100000000UL; + gd->bd->bi_dram[bank].size = sdram_b2_size; + } + + return 0; +} + +phys_size_t get_effective_memsize(void) +{ + int ret; + phys_size_t sdram_size; + phys_size_t sdram_b1_size; + + ret = board_phys_sdram_size(&sdram_size); + if (!ret) { + /* Bank 1 can't cross over 4GB space */ + if (sdram_size > 0x80000000) + sdram_b1_size = 0x100000000UL - PHYS_SDRAM; + else + sdram_b1_size = sdram_size; + + if (rom_pointer[1]) { + /* We will relocate u-boot to Top of dram1. Tee position has three cases: + * 1. At the top of dram1, Then return the size removed optee size. + * 2. In the middle of dram1, return the size of dram1. + * 3. Not in the scope of dram1, return the size of dram1. + */ + if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size)) + return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); + } + + return sdram_b1_size; + } else { + return PHYS_SDRAM_SIZE; + } +} + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + u32 val[2] = {}; + int ret, num_of_macs; + + ret = fuse_read(40, 5, &val[0]); + if (ret) + goto err; + + ret = fuse_read(40, 6, &val[1]); + if (ret) + goto err; + + num_of_macs = (val[1] >> 24) & 0xff; + if (num_of_macs <= (dev_id * 3)) { + printf("WARNING: no MAC address assigned for MAC%d\n", dev_id); + goto err; + } + + mac[0] = val[0] & 0xff; + mac[1] = (val[0] >> 8) & 0xff; + mac[2] = (val[0] >> 16) & 0xff; + mac[3] = (val[0] >> 24) & 0xff; + mac[4] = val[1] & 0xff; + mac[5] = (val[1] >> 8) & 0xff; + if (dev_id == 1) + mac[5] = mac[5] + 3; + if (dev_id == 2) + mac[5] = mac[5] + 6; + + debug("%s: MAC%d: %pM\n", __func__, dev_id, mac); + return; +err: + memset(mac, 0, 6); + printf("%s: fuse read err: %d\n", __func__, ret); +} + +const char *get_imx_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX95: + return "95";/* iMX95 FULL */ + default: + return "??"; + } +} + +void build_info(void) +{ + u32 fw_version, sha1, res = 0, status; + int ret; + + printf("\nBuildInfo:\n"); + + ret = ele_get_fw_status(&status, &res); + if (ret) { + printf(" - ELE firmware status failed %d, 0x%x\n", ret, res); + } else if ((status & 0xff) == 1) { + ret = ele_get_fw_version(&fw_version, &sha1, &res); + if (ret) { + printf(" - ELE firmware version failed %d, 0x%x\n", ret, res); + } else { + printf(" - ELE firmware version %u.%u.%u-%x", + (fw_version & (0x00ff0000)) >> 16, + (fw_version & (0x0000fff0)) >> 4, + (fw_version & (0x0000000f)), sha1); + ((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n"); + } + } else { + printf(" - ELE firmware not included\n"); + } + puts("\n"); +} + +int arch_misc_init(void) +{ + build_info(); + return 0; +} + +#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_SPL_BUILD) +int board_fix_fdt(void *fdt) +{ + return 0; +} +#endif + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + +#if IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +void get_board_serial(struct tag_serialnr *serialnr) +{ + printf("UID: %08x%08x%08x%08x\n", __be32_to_cpu(gd->arch.uid[0]), + __be32_to_cpu(gd->arch.uid[1]), __be32_to_cpu(gd->arch.uid[2]), + __be32_to_cpu(gd->arch.uid[3])); + + serialnr->low = __be32_to_cpu(gd->arch.uid[1]); + serialnr->high = __be32_to_cpu(gd->arch.uid[0]); +} +#endif + +static void gpio_reset(ulong gpio_base) +{ + writel(0, gpio_base + 0x10); + writel(0, gpio_base + 0x14); + writel(0, gpio_base + 0x18); + writel(0, gpio_base + 0x1c); +} + +int arch_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + disable_wdog((void __iomem *)WDG3_BASE_ADDR); + disable_wdog((void __iomem *)WDG4_BASE_ADDR); + + gpio_reset(GPIO2_BASE_ADDR); + gpio_reset(GPIO3_BASE_ADDR); + gpio_reset(GPIO4_BASE_ADDR); + gpio_reset(GPIO5_BASE_ADDR); + } + + return 0; +} + +int imx9_probe_mu(void) +{ + struct udevice *dev; + int ret; + u32 res; + struct ele_get_info_data info; + + ret = uclass_get_device_by_driver(UCLASS_SCMI_AGENT, DM_DRIVER_GET(scmi_mbox), &dev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_of_get_channel(dev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_PINCTRL, "protocol@19", &dev); + if (ret) + return ret; + +#if defined(CONFIG_SPL_BUILD) + ret = uclass_get_device_by_name(UCLASS_MISC, "mailbox@47530000", &dev); +#else + ret = uclass_get_device_by_name(UCLASS_MISC, "mailbox@47550000", &dev); +#endif + if (ret) + return ret; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + ret = ele_get_info(&info, &res); + if (ret) + return ret; + + set_cpu_info(&info); + + return 0; +} + +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu); + +int timer_init(void) +{ + gd->arch.tbl = 0; + gd->arch.tbu = 0; + + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + unsigned long freq = 24000000; + + asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); + + /* Clear the compare frame interrupt */ + unsigned long sctr_cmpcr_addr = SYSCNT_CMP_BASE_ADDR + 0x2c; + unsigned long sctr_cmpcr = readl(sctr_cmpcr_addr); + + sctr_cmpcr &= ~0x1; + writel(sctr_cmpcr, sctr_cmpcr_addr); + } + + return 0; +} + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_device dev = get_boot_device(); + enum env_location env_loc = ENVL_UNKNOWN; + + if (prio) + return env_loc; + + switch (dev) { + case QSPI_BOOT: + env_loc = ENVL_SPI_FLASH; + break; + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: + env_loc = ENVL_MMC; + break; + default: + env_loc = ENVL_NOWHERE; + break; + } + + return env_loc; +} + +enum imx9_soc_voltage_mode soc_target_voltage_mode(void) +{ + u32 speed = get_cpu_speed_grade_hz(); + enum imx9_soc_voltage_mode voltage = VOLT_OVER_DRIVE; + + if (is_imx95()) { + if (speed == 2000000000) + voltage = VOLT_SUPER_OVER_DRIVE; + else if (speed == 1800000000) + voltage = VOLT_OVER_DRIVE; + else if (speed == 1400000000) + voltage = VOLT_NOMINAL_DRIVE; + else /* boot not support low drive mode according to AS */ + printf("Unexpected A55 freq %u, default to OD\n", speed); + } + + return voltage; +} + +#if IS_ENABLED(CONFIG_SCMI_FIRMWARE) +enum boot_device get_boot_device(void) +{ + volatile gd_t *pgd = gd; + int ret; + u16 boot_type; + u8 boot_instance; + enum boot_device boot_dev = 0; + rom_passover_t *rdata; + +#if IS_ENABLED(CONFIG_SPL_BUILD) + rdata = &rom_passover_data; +#else + rom_passover_t rom_data = {0}; + + if (pgd->reloc_off == 0) + rdata = &rom_data; + else + rdata = &rom_passover_data; +#endif + if (rdata->tag == 0) { + ret = scmi_get_rom_data(rdata); + if (ret != 0) { + puts("SCMI: failure at rom_boot_info\n"); + return -1; + } + } + boot_type = rdata->boot_dev_type; + boot_instance = rdata->boot_dev_inst; + + set_gd(pgd); + + switch (boot_type) { + case BT_DEV_TYPE_SD: + boot_dev = boot_instance + SD1_BOOT; + break; + case BT_DEV_TYPE_MMC: + boot_dev = boot_instance + MMC1_BOOT; + break; + case BT_DEV_TYPE_NAND: + boot_dev = NAND_BOOT; + break; + case BT_DEV_TYPE_FLEXSPINOR: + boot_dev = QSPI_BOOT; + break; + case BT_DEV_TYPE_USB: + boot_dev = boot_instance + USB_BOOT; + if (IS_ENABLED(CONFIG_IMX95)) + boot_dev -= 3; //iMX95 usb instance start at 3 + break; + default: + break; + } + + return boot_dev; +} +#endif + +bool arch_check_dst_in_secure(void *start, ulong size) +{ + ulong ns_end = CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE; +#ifdef PHYS_SDRAM_2_SIZE + ns_end += PHYS_SDRAM_2_SIZE; +#endif + + if ((ulong)start < CFG_SYS_SDRAM_BASE || (ulong)start + size > ns_end) + return true; + + return false; +} + +void *arch_get_container_trampoline(void) +{ + return (void *)((ulong)CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE - SZ_16M); +} diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 41116e2c6a2..9901f8a7b56 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -10,6 +10,7 @@ #include <log.h> #include <asm/io.h> #include <linux/errno.h> +#include <linux/string.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 3982f4cca18..b7008df8e35 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -35,12 +35,10 @@ ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev) { u32 sector = 0; - /* - * Some boards use this value even though MMC is not enabled in SPL, for - * example imx8mn_bsh_smm_s2 - */ -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#if IS_ENABLED(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR) sector = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; +#elif IS_ENABLED(CONFIG_SPL_NAND_RAW_U_BOOT_USE_SECTOR) + sector = CONFIG_SPL_NAND_RAW_U_BOOT_SECTOR; #endif return image_offset + sector * 512 - 0x8000; diff --git a/arch/arm/mach-k3/am62x/boot.c b/arch/arm/mach-k3/am62x/boot.c index 132b42f7edb..a3a6cda6bdb 100644 --- a/arch/arm/mach-k3/am62x/boot.c +++ b/arch/arm/mach-k3/am62x/boot.c @@ -101,3 +101,43 @@ u32 get_boot_device(void) return bootmedia; } + +const char *get_reset_reason(void) +{ + u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC); + + /* After reading reset source register, software must clear it */ + if (reset_reason) + writel(reset_reason, CTRLMMR_MCU_RST_SRC); + + if (reset_reason == 0 || + (reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN | + RST_SRC_SW_MAIN_POR_FROM_MCU | + RST_SRC_DS_MAIN_PORZ))) + return "POR"; + + if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR)) + return "ESM"; + + if (reset_reason & RST_SRC_DM_WDT_RST) + return "WDOG"; + + if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN | + RST_SRC_SW_MAIN_WARM_FROM_MCU | + RST_SRC_SW_MCU_WARM_RST)) + return "RST"; + + if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST)) + return "DMSC"; + + if (reset_reason & RST_SRC_DEBUG_RST) + return "JTAG"; + + if (reset_reason & RST_SRC_THERMAL_RST) + return "THERMAL"; + + if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN)) + return "PIN"; + + return "UNKNOWN"; +} diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index fa8cd93d664..0323001d6d3 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -175,11 +175,17 @@ static const char *get_device_type_name(void) } } +__weak const char *get_reset_reason(void) +{ + return NULL; +} + int print_cpuinfo(void) { struct udevice *soc; char name[64]; int ret; + const char *reset_reason; printf("SoC: "); @@ -201,6 +207,10 @@ int print_cpuinfo(void) printf("%s\n", get_device_type_name()); + reset_reason = get_reset_reason(); + if (reset_reason) + printf("Reset reason: %s\n", reset_reason); + return 0; } #endif @@ -228,10 +238,6 @@ void spl_enable_cache(void) gd->arch.tlb_size = PGTABLE_SIZE; gd->ram_top += get_effective_memsize(); - /* keep ram_top in the 32-bit address space */ - if (gd->ram_top >= 0x100000000) - gd->ram_top = (phys_addr_t)0x100000000; - gd->relocaddr = gd->ram_top; ret = spl_reserve_video_from_ram_top(); diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 2ec60c7879a..02c74731fea 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -10,6 +10,9 @@ #include <asm/hardware.h> #include <mach/security.h> +/* keep ram_top in the 32-bit address space */ +#define CFG_MAX_MEM_MAPPED 0x100000000 + #define K3_FIREWALL_BACKGROUND_BIT (8) struct fwl_data { diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index bcbc4821c82..c33362696c4 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -79,6 +79,25 @@ #define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) +/* Reset Reason Detection */ +#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) + +#define RST_SRC_SAFETY_ERR BIT(31) +#define RST_SRC_MAIN_ESM_ERR BIT(30) +#define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25) +#define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24) +#define RST_SRC_DS_MAIN_PORZ BIT(23) +#define RST_SRC_DM_WDT_RST BIT(22) +#define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21) +#define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20) +#define RST_SRC_SW_MCU_WARM_RST BIT(16) +#define RST_SRC_SMS_WARM_RST BIT(13) +#define RST_SRC_SMS_COLD_RST BIT(12) +#define RST_SRC_DEBUG_RST BIT(8) +#define RST_SRC_THERMAL_RST BIT(4) +#define RST_SRC_MAIN_RESET_PIN BIT(2) +#define RST_SRC_MCU_RESET_PIN BIT(0) + /* Debounce register configuration */ #define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4)) diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index fc7bee4d00b..81b5f1fa45e 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -125,4 +125,5 @@ struct rom_extended_boot_data { }; u32 get_boot_device(void); +const char *get_reset_reason(void); #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 0b6604039f3..fa146549f13 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -5,6 +5,7 @@ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <env.h> #include <linux/printk.h> #include <linux/types.h> #include <asm/hardware.h> diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c index e9ecc05953a..7b94a80b725 100644 --- a/arch/arm/mach-keystone/cmd_clock.c +++ b/arch/arm/mach-keystone/cmd_clock.c @@ -8,6 +8,7 @@ #include <vsprintf.h> #include <command.h> +#include <linux/string.h> #include <asm/arch/hardware.h> #include <asm/arch/clock.h> #include <asm/arch/psc_defs.h> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 6761a9cb393..f1ccedba5d7 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -50,11 +50,13 @@ config TARGET_DS109 bool "Synology DS109" select KW88F6281 select SHEEVA_88SV131 + select KIRKWOOD_COMMON config TARGET_GURUPLUG bool "GuruPlug Board" select KW88F6281 select SHEEVA_88SV131 + select KIRKWOOD_COMMON config TARGET_SHEEVAPLUG bool "SheevaPlug Board" @@ -86,6 +88,7 @@ config TARGET_DNS325 bool "dns325 Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_ICONNECT bool "iconnect Board" @@ -103,15 +106,18 @@ config TARGET_NET2BIG_V2 bool "LaCie 2Big Network v2 NAS Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_NETSPACE_V2 bool "LaCie netspace_v2 Board" select FEROCEON_88FR131 + select KIRKWOOD_COMMON config TARGET_IB62X0 bool "ib62x0 Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_DOCKSTAR bool "Dockstar Board" @@ -129,6 +135,7 @@ config TARGET_NAS220 bool "BlackArmor NAS220" select FEROCEON_88FR131 select KW88F6192 + select KIRKWOOD_COMMON config TARGET_NSA310S bool "Zyxel NSA310S" @@ -146,11 +153,13 @@ config TARGET_SBx81LIFKW bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_SBx81LIFXCAT bool "Allied Telesis SBx81GP24/SBx81GT24" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON endchoice diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig index aeb55da609b..d373ab56ce9 100644 --- a/arch/arm/mach-renesas/Kconfig +++ b/arch/arm/mach-renesas/Kconfig @@ -76,6 +76,7 @@ config RZG2L imply MULTI_DTB_FIT imply MULTI_DTB_FIT_USER_DEFINED_AREA imply PINCTRL_RZG2L + imply RENESAS_RAVB imply RENESAS_SDHI imply RZG2L_GPIO imply SCIF_CONSOLE diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index e563bf455e6..128ee362f8a 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -5,7 +5,6 @@ choice config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" - select HAS_ROM select BOARD_LATE_INIT select ROCKCHIP_SPI_IMAGE help @@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_JERRY config TARGET_CHROMEBIT_MICKEY bool "Google/Rockchip Veyron-Mickey Chromebit" - select HAS_ROM select BOARD_LATE_INIT select ROCKCHIP_SPI_IMAGE help @@ -28,7 +26,6 @@ config TARGET_CHROMEBIT_MICKEY config TARGET_CHROMEBOOK_MINNIE bool "Google/Rockchip Veyron-Minnie Chromebook" - select HAS_ROM select BOARD_LATE_INIT select ROCKCHIP_SPI_IMAGE help @@ -41,7 +38,6 @@ config TARGET_CHROMEBOOK_MINNIE config TARGET_CHROMEBOOK_SPEEDY bool "Google/Rockchip Veyron-Speedy Chromebook" - select HAS_ROM select BOARD_LATE_INIT select ROCKCHIP_SPI_IMAGE help @@ -54,7 +50,6 @@ config TARGET_CHROMEBOOK_SPEEDY config TARGET_EVB_RK3288 bool "Evb-RK3288" - select HAS_ROM select BOARD_LATE_INIT select TPL help diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index b2430207ee9..5c21b08a5ae 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -5,7 +5,6 @@ choice config TARGET_CHROMEBOOK_BOB bool "Asus Flip C101PA Chromebook (RK3399)" - select HAS_ROM select ROCKCHIP_SPI_IMAGE help Bob is a small RK3299-based device similar in apperance to Minnie. @@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_BOB config TARGET_CHROMEBOOK_KEVIN bool "Samsung Chromebook Plus (RK3399)" - select HAS_ROM select ROCKCHIP_SPI_IMAGE help Kevin is a RK3399-based convertible chromebook. It has two USB 3.0 diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 8506d510413..bda12324803 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -7,6 +7,7 @@ #include <config.h> #include <errno.h> +#include <env.h> #include <fdtdec.h> #include <log.h> #include <init.h> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 04640e476e6..506ecac2ef0 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -6,6 +6,7 @@ #include <bootm.h> #include <command.h> #include <dfu.h> +#include <env.h> #include <image.h> #include <asm/arch/stm32prog.h> #include <linux/printk.h> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 4690dcb3ea6..c3c352eceb1 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -198,6 +198,23 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config SYS_CONFIG_NAME + default "tegra" + +config TEGRA_PRAM + select TEGRA_SUPPORT_NON_SECURE if TEGRA114 || TEGRA124 + bool "Support reservation of the protected RAM" + help + This option indicates the presence of a region of protected RAM. + +config TEGRA_PRAM_SIZE + hex "Size of pRAM region" + depends on TEGRA_PRAM + default 0x1000 + help + Size in kB of carevout which will be reserved as protected RAM starting + from the top of the RAM. + config TEGRA_SPI def_bool y depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 68534dcbb22..396851c5bd8 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -227,31 +227,6 @@ int board_early_init_f(void) arch_timer_init(); #endif -#if defined(CONFIG_DISABLE_SDMMC1_EARLY) - /* - * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT. - * We do this because earlier bootloaders have enabled power to - * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init() - * results in power being back-driven into the SD-card and SDMMC1 - * HW, which is 'bad' as per the HW team. - * - * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in - * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT - * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off - * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard - * voltage turns off. Since the SDCard voltage is no longer there, the - * SDMMC CLK/DAT lines are backdriving into what essentially is a - * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V" - * - * Note that this can probably be removed when we change over to storing - * all BL components on QSPI on Nano, and U-Boot then becomes the first - * one to turn on SDMMC1 power. Another fix would be to have CBoot - * disable power/gate SDMMC1 off before handing off to U-Boot/kernel. - */ - reset_set_enable(PERIPH_ID_SDMMC1, 1); - clock_set_enable(PERIPH_ID_SDMMC1, 0); -#endif /* CONFIG_DISABLE_SDMMC1_EARLY */ - pinmux_init(); board_init_uart_f(); diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c index f4ae602d523..96044ac78ce 100644 --- a/arch/arm/mach-tegra/dt-setup.c +++ b/arch/arm/mach-tegra/dt-setup.c @@ -3,6 +3,7 @@ * Copyright (c) 2010-2016, NVIDIA CORPORATION. */ +#include <env.h> #include <fdtdec.h> #include <stdlib.h> #include <asm/arch-tegra/cboot.h> diff --git a/arch/arm/mach-tegra/tegra124/bct.c b/arch/arm/mach-tegra/tegra124/bct.c index a71aa87fce1..4dc4b7138ab 100644 --- a/arch/arm/mach-tegra/tegra124/bct.c +++ b/arch/arm/mach-tegra/tegra124/bct.c @@ -7,6 +7,7 @@ #include <command.h> #include <log.h> #include <vsprintf.h> +#include <linux/string.h> #include <asm/arch-tegra/crypto.h> #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index a79fdc25650..bedbedade7b 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -54,6 +54,10 @@ config TARGET_SEABOARD select TEGRA_LP0 select TEGRA_PMU +config TARGET_STAR + bool "LG Tegra20 Star board" + select BOARD_LATE_INIT + config TARGET_TEC bool "Avionic Design Tamonten Evaluation Carrier" select BOARD_LATE_INIT @@ -88,6 +92,7 @@ source "board/compal/paz00/Kconfig" source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" source "board/nvidia/seaboard/Kconfig" +source "board/lg/star/Kconfig" source "board/avionic-design/tec/Kconfig" source "board/asus/transformer-t20/Kconfig" source "board/compulab/trimslice/Kconfig" diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c index b647b6b26d2..253cb243676 100644 --- a/arch/arm/mach-tegra/tegra20/bct.c +++ b/arch/arm/mach-tegra/tegra20/bct.c @@ -7,6 +7,7 @@ #include <command.h> #include <log.h> #include <vsprintf.h> +#include <linux/string.h> #include <asm/arch-tegra/crypto.h> #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c index 250009ea8d8..398ba1de386 100644 --- a/arch/arm/mach-tegra/tegra30/bct.c +++ b/arch/arm/mach-tegra/tegra30/bct.c @@ -7,6 +7,7 @@ #include <command.h> #include <log.h> #include <vsprintf.h> +#include <linux/string.h> #include <asm/arch-tegra/crypto.h> #include "bct.h" #include "uboot_aes.h" diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c index 629f8b90c9d..be4ce3265bb 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c @@ -9,6 +9,7 @@ #include <linux/io.h> #include <linux/printk.h> #include <linux/sizes.h> +#include <linux/string.h> #include "../soc-info.h" #include "ddrmphy-regs.h" diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index ca519d1c7e0..3ccafe20638 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -10,6 +10,7 @@ #include <linux/io.h> #include <linux/printk.h> #include <linux/sizes.h> +#include <linux/string.h> #include "../soc-info.h" #include "ddrphy-regs.h" |