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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi51
-rw-r--r--arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts47
-rw-r--r--arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi146
-rw-r--r--arch/arm/mach-stm32mp/Kconfig22
5 files changed, 266 insertions, 1 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0f54801d729..39ee7dcbacb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -989,6 +989,7 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-avenger96.dtb \
+ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
new file mode 100644
index 00000000000..96fe4612351
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "stm32mp157a-icore-stm32mp1-u-boot.dtsi"
+
+/{
+ aliases {
+ mmc0 = &sdmmc1;
+ };
+
+ chosen {
+ stdout-path = &uart4;
+ };
+};
+
+&sdmmc1 {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc1_b4_pins_a {
+ u-boot,dm-pre-reloc;
+
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ pins2 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+
+ pins2 {
+ u-boot,dm-pre-reloc;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
new file mode 100644
index 00000000000..ec9f1d1cd50
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+#include "stm32mp157.dtsi"
+#include "stm32mp157a-icore-stm32mp1.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit";
+ compatible = "engicam,icore-stm32mp1-edimm2.2",
+ "engicam,icore-stm32mp1", "st,stm32mp157";
+
+ aliases {
+ serial0 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ disable-wp;
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ st,neg-edge;
+ vmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
new file mode 100644
index 00000000000..d62c24d4ce2
--- /dev/null
+++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (c) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-u-boot.dtsi"
+#include "stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi"
+
+&vddcore {
+ u-boot,dm-pre-reloc;
+};
+
+&vdd {
+ u-boot,dm-pre-reloc;
+};
+
+&vdd_usb {
+ u-boot,dm-pre-reloc;
+};
+
+&vdda {
+ u-boot,dm-pre-reloc;
+};
+
+&vdd_ddr {
+ u-boot,dm-pre-reloc;
+};
+
+&vtt_ddr {
+ u-boot,dm-pre-reloc;
+};
+
+&vref_ddr {
+ u-boot,dm-pre-reloc;
+};
+
+&vdd_sd {
+ u-boot,dm-pre-reloc;
+};
+
+&v3v3 {
+ u-boot,dm-pre-reloc;
+};
+
+&v2v8 {
+ u-boot,dm-pre-reloc;
+};
+
+&v1v8 {
+ u-boot,dm-pre-reloc;
+};
+
+&rcc {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_DISABLED
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSE
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4R
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_LSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+ pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+ frac = < 0x1400 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+ pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
+ cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+ frac = < 0x1a04 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+ pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
+ cfg = < 3 98 5 7 7 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 4f5e69360cf..70a0fcd91e6 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -77,6 +77,25 @@ config TARGET_ST_STM32MP15x
Evalulation board (EV1) or Discovery board (DK1 and DK2).
The difference between board are managed with devicetree
+config TARGET_ICORE_STM32MP1
+ bool "Engicam i.Core STM32MP1 SOM"
+ select STM32MP15x
+ imply BOOTCOUNT_LIMIT
+ imply BOOTSTAGE
+ imply CMD_BOOTCOUNT
+ imply CMD_BOOTSTAGE
+ imply CMD_CLS if CMD_BMP
+ imply DISABLE_CONSOLE
+ imply PRE_CONSOLE_BUFFER
+ imply SILENT_CONSOLE
+ help
+ i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A.
+
+ i.Core STM32MP1 EDIMM2.2:
+ * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
+ * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for
+ creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit.
+
config TARGET_DH_STM32MP1_PDK2
bool "DH STM32MP1 PDK2"
select STM32MP15x
@@ -161,7 +180,8 @@ config DEBUG_UART_CLOCK
endif
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
-source "board/st/stm32mp1/Kconfig"
source "board/dhelectronics/dh_stm32mp1/Kconfig"
+source "board/engicam/stm32mp1/Kconfig"
+source "board/st/stm32mp1/Kconfig"
endif
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 02:32:41 +0000