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-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/rk3036-evb-u-boot.dtsi (renamed from arch/arm/dts/rk3036-sdk-u-boot.dtsi)6
-rw-r--r--arch/arm/dts/rk3036-kylin-u-boot.dtsi13
-rw-r--r--arch/arm/dts/rk3036-sdk.dts74
-rw-r--r--arch/arm/dts/rk3036.dtsi439
-rw-r--r--arch/arm/include/asm/arch-rockchip/grf_rk3399.h6
-rw-r--r--arch/arm/mach-rockchip/Kconfig1
-rw-r--r--arch/arm/mach-rockchip/rk3399/rk3399.c25
-rw-r--r--arch/arm/mach-rockchip/sdram.c6
9 files changed, 48 insertions, 525 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index acea0cc2ec1..267b0179a5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -52,9 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \
dtb-$(CONFIG_MACH_S700) += \
s700-cubieboard7.dtb
-dtb-$(CONFIG_ROCKCHIP_RK3036) += \
- rk3036-sdk.dtb
-
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
rk3128-evb.dtb
diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-evb-u-boot.dtsi
index ef7e0207c3e..f8857c736d0 100644
--- a/arch/arm/dts/rk3036-sdk-u-boot.dtsi
+++ b/arch/arm/dts/rk3036-evb-u-boot.dtsi
@@ -1,13 +1,13 @@
#include "rk3036-u-boot.dtsi"
-&uart2 {
+&grf {
bootph-all;
};
-&grf {
+&pinctrl {
bootph-all;
};
-&pinctrl {
+&uart2 {
bootph-all;
};
diff --git a/arch/arm/dts/rk3036-kylin-u-boot.dtsi b/arch/arm/dts/rk3036-kylin-u-boot.dtsi
new file mode 100644
index 00000000000..f8857c736d0
--- /dev/null
+++ b/arch/arm/dts/rk3036-kylin-u-boot.dtsi
@@ -0,0 +1,13 @@
+#include "rk3036-u-boot.dtsi"
+
+&grf {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&uart2 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts
deleted file mode 100644
index 3493150df92..00000000000
--- a/arch/arm/dts/rk3036-sdk.dts
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rk3036.dtsi"
-
-/ {
- model = "SDK-RK3036";
- compatible = "sdk,sdk-rk3036", "rockchip,rk3036";
-
- chosen {
- stdout-path = &uart2;
- };
-
- vcc5v0_otg: vcc5v0-otg-drv {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_otg";
- gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&otg_vbus_drv>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc5v0_host: vcc5v0-host-drv {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&host_vbus_drv>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&i2c1 {
- status = "okay";
-
- hym8563: hym8563@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- };
-};
-
-&usb_host {
- vbus-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&usb_otg {
- vbus-supply = <&vcc5v0_otg>;
- status = "okay";
-};
-
-&pinctrl {
- usb_otg {
- otg_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb_host {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi
deleted file mode 100644
index 75588de4863..00000000000
--- a/arch/arm/dts/rk3036.dtsi
+++ /dev/null
@@ -1,439 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/clock/rk3036-cru.h>
-#include "skeleton.dtsi"
-
-/ {
- compatible = "rockchip,rk3036";
-
- interrupt-parent = <&gic>;
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- i2c1 = &i2c1;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- };
-
- memory {
- device_type = "memory";
- reg = <0x60000000 0x40000000>;
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "rockchip,rk3036-smp";
-
- cpu0: cpu@f00 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf00>;
- operating-points = <
- /* KHz uV */
- 816000 1000000
- >;
- #cooling-cells = <2>; /* min followed by max */
- clock-latency = <40000>;
- clocks = <&cru ARMCLK>;
- resets = <&cru SRST_CORE0>;
- };
- cpu1: cpu@f01 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf01>;
- resets = <&cru SRST_CORE1>;
- };
- };
-
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@20078000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x20078000 0x4000>;
- arm,pl330-broken-no-flushp;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC2>;
- clock-names = "apb_pclk";
- };
- };
-
- xin24m: oscillator {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- arm,cpu-registers-not-fw-configured;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
- };
-
- cru: clock-controller@20000000 {
- compatible = "rockchip,rk3036-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- assigned-clocks = <&cru PLL_GPLL>;
- assigned-clock-rates = <594000000>;
- };
-
- uart0: serial@20060000 {
- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
- reg = <0x20060000 0x100>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- };
-
- uart1: serial@20064000 {
- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
- reg = <0x20064000 0x100>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer>;
- };
-
- uart2: serial@20068000 {
- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
- reg = <0x20068000 0x100>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_xfer>;
- };
-
- pwm0: pwm@20050000 {
- compatible = "rockchip,rk2928-pwm";
- reg = <0x20050000 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- status = "disabled";
- };
-
- pwm1: pwm@20050010 {
- compatible = "rockchip,rk2928-pwm";
- reg = <0x20050010 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm1_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- status = "disabled";
- };
-
- pwm2: pwm@20050020 {
- compatible = "rockchip,rk2928-pwm";
- reg = <0x20050020 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- status = "disabled";
- };
-
- pwm3: pwm@20050030 {
- compatible = "rockchip,rk2928-pwm";
- reg = <0x20050030 0x10>;
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- status = "disabled";
- };
-
- sram: sram@10080000 {
- compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
- reg = <0x10080000 0x2000>;
- };
-
- gic: interrupt-controller@10139000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
-
- reg = <0x10139000 0x1000>,
- <0x1013a000 0x1000>,
- <0x1013c000 0x2000>,
- <0x1013e000 0x2000>;
- interrupts = <GIC_PPI 9 0xf04>;
- };
-
- grf: syscon@20008000 {
- compatible = "rockchip,rk3036-grf", "syscon";
- reg = <0x20008000 0x1000>;
- };
-
- usb_otg: usb@10180000 {
- compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x10180000 0x40000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG0>;
- clock-names = "otg";
- dr_mode = "otg";
- g-np-tx-fifo-size = <16>;
- g-rx-fifo-size = <275>;
- g-tx-fifo-size = <256 128 128 64 64 32>;
- g-use-dma;
- status = "disabled";
- };
-
- usb_host: usb@101c0000 {
- compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x101c0000 0x40000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG1>;
- clock-names = "otg";
- dr_mode = "host";
- status = "disabled";
- };
-
- emmc: dwmmc@1021c000 {
- compatible = "rockchip,rk3288-dw-mshc";
- clock-frequency = <37500000>;
- max-frequency = <37500000>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
- dmas = <&pdma 12>;
- dma-names = "rx-tx";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x1021c000 0x4000>;
- broken-cd;
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- disable-wp;
- fifo-mode;
- non-removable;
- num-slots = <1>;
- default-sample-phase = <158>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- };
-
- sdmmc: dwmmc@10214000 {
- compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x10214000 0x4000>;
- clock-frequency = <37500000>;
- max-frequency = <37500000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3036-pinctrl";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gpio0: gpio0@2007c000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x2007c000 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO0>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio1@20080000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x20080000 0x100>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio2@20084000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x20084000 0x100>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
- emmc {
- /*
- * We run eMMC at max speed; bump up drive strength.
- * We also have external pulls, so disable the internal ones.
- */
- emmc_clk: emmc-clk {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- emmc_cmd: emmc-cmd {
- rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- emmc_bus8: emmc-bus8 {
- rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
- <1 25 RK_FUNC_2 &pcfg_pull_none>,
- <1 26 RK_FUNC_2 &pcfg_pull_none>,
- <1 27 RK_FUNC_2 &pcfg_pull_none>;
- /*
- <1 28 RK_FUNC_2 &pcfg_pull_up>,
- <1 29 RK_FUNC_2 &pcfg_pull_up>,
- <1 30 RK_FUNC_2 &pcfg_pull_up>,
- <1 31 RK_FUNC_2 &pcfg_pull_up>;
- */
- };
- };
-
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
- <0 17 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart0_cts: uart0-cts {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart0_rts: uart0-rts {
- rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
-
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
- <2 23 RK_FUNC_1 &pcfg_pull_none>;
- };
- /* no rts / cts for uart1 */
- };
-
- uart2 {
- uart2_xfer: uart2-xfer {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
- <1 19 RK_FUNC_2 &pcfg_pull_none>;
- };
- /* no rts / cts for uart2 */
- };
-
- pwm0 {
- pwm0_pin: pwm0-pin {
- rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
-
- pwm1 {
- pwm1_pin: pwm1-pin {
- rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
-
- pwm2 {
- pwm2_pin: pwm2-pin {
- rockchip,pins = <0 1 2 &pcfg_pull_none>;
- };
- };
-
- pwm3 {
- pwm3_pin: pwm3-pin {
- rockchip,pins = <0 27 1 &pcfg_pull_none>;
- };
- };
-
- i2c1 {
- i2c1_xfer: i2c1-xfer {
- rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
- <0 3 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
- };
-
- i2c1: i2c@20056000 {
- compatible = "rockchip,rk3288-i2c";
- reg = <0x20056000 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index dd89cd20505..e6125d6bf54 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -466,18 +466,18 @@ enum {
/* GRF_GPIO4C_IOMUX */
GRF_GPIO4C0_SEL_SHIFT = 0,
GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
- GRF_UART2DGBB_SIN = 2,
+ GRF_UART2DBGB_SIN = 2,
GRF_HDMII2C_SCL = 3,
GRF_GPIO4C1_SEL_SHIFT = 2,
GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
- GRF_UART2DGBB_SOUT = 2,
+ GRF_UART2DBGB_SOUT = 2,
GRF_HDMII2C_SDA = 3,
GRF_GPIO4C2_SEL_SHIFT = 4,
GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
GRF_PWM_0 = 1,
GRF_GPIO4C3_SEL_SHIFT = 6,
GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
- GRF_UART2DGBC_SIN = 1,
+ GRF_UART2DBGC_SIN = 1,
GRF_GPIO4C4_SEL_SHIFT = 8,
GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
GRF_UART2DBGC_SOUT = 1,
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 4d3157b2edd..adac11a6b89 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -29,6 +29,7 @@ config ROCKCHIP_RK3036
select CPU_V7A
select SUPPORT_SPL
select SPL
+ imply OF_UPSTREAM
imply USB_FUNCTION_ROCKUSB
imply CMD_ROCKUSB
imply ROCKCHIP_COMMON_BOARD
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 1ce43c6f0d4..99597076d2c 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -7,6 +7,7 @@
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <spl_gpio.h>
#include <syscon.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
@@ -15,7 +16,6 @@
#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/gpio.h>
#include <linux/bitops.h>
#include <linux/printk.h>
#include <power/regulator.h>
@@ -133,10 +133,31 @@ void board_debug_uart_init(void)
GRF_GPIO3B7_SEL_MASK,
GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
#else
+ struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
+
+ if (IS_ENABLED(CONFIG_XPL_BUILD) &&
+ (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
+ IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
+ rk_setreg(&grf->io_vsel, 1 << 0);
+
+ /*
+ * Let's enable these power rails here, we are already running
+ * the SPI-Flash-based code.
+ */
+ spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2),
+ GPIO_PULL_NORMAL);
+
+ spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4),
+ GPIO_PULL_NORMAL);
+ }
+
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
- GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
+ GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT);
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C4_SEL_MASK,
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 1fb01e1c4b1..f7d32829295 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -309,6 +309,8 @@ int dram_init_banksize(void)
if (ram_top > SZ_4G && top < SZ_4G) {
gd->bd->bi_dram[1].start = SZ_4G;
gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
+ } else if (ram_top > SZ_4G && top == SZ_4G) {
+ gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
}
#else
#ifdef CONFIG_SPL_OPTEE_IMAGE
@@ -476,6 +478,7 @@ int dram_init(void)
debug("Cannot get DRAM size: %d\n", ret);
return ret;
}
+ gd->ram_base = ram.base;
gd->ram_size = ram.size;
debug("SDRAM base=%lx, size=%lx\n",
(unsigned long)ram.base, (unsigned long)ram.size);
@@ -485,7 +488,8 @@ int dram_init(void)
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
- unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
+ /* Make sure U-Boot only uses the space below the 4G address boundary */
+ u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G);
return (gd->ram_top > top) ? top : gd->ram_top;
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-25 15:55:29 +0000