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-rw-r--r--arch/arm/dts/fsl-imx8qm-apalis.dts6
-rw-r--r--arch/arm/dts/fsl-imx8qxp-colibri.dts6
-rw-r--r--arch/arm/dts/rv1108-u-boot.dtsi4
-rw-r--r--arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi2
-rw-r--r--arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi4
-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-imx8m/clock_imx8mq.h10
-rw-r--r--arch/arm/include/asm/arch-mx7/crm_regs.h2
-rw-r--r--arch/arm/include/asm/mach-imx/sys_proto.h5
-rw-r--r--arch/arm/mach-imx/cpu.c4
-rw-r--r--arch/arm/mach-imx/imx8m/clock_imx8mm.c1
-rw-r--r--arch/arm/mach-imx/imx8m/soc.c12
-rw-r--r--arch/arm/mach-imx/mx6/ddr.c15
-rw-r--r--arch/arm/mach-mediatek/Kconfig6
-rwxr-xr-xarch/arm/mach-rockchip/make_fit_atf.py5
-rw-r--r--arch/arm/mach-stm32mp/cpu.c4
16 files changed, 49 insertions, 39 deletions
diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts
index 9b1f8aa32d0..5187b794527 100644
--- a/arch/arm/dts/fsl-imx8qm-apalis.dts
+++ b/arch/arm/dts/fsl-imx8qm-apalis.dts
@@ -12,8 +12,8 @@
#include "fsl-imx8qm-apalis-u-boot.dtsi"
/ {
- model = "Toradex Apalis iMX8QM";
- compatible = "toradex,apalis-imx8qm", "fsl,imx8qm";
+ model = "Toradex Apalis iMX8";
+ compatible = "toradex,apalis-imx8", "fsl,imx8qm";
chosen {
bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
@@ -38,7 +38,7 @@
<&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>,
<&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>;
- apalis-imx8qm {
+ apalis-imx8 {
pinctrl_gpio12: gpio12grp {
fsl,pins = <
/* Apalis GPIO1 */
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts
index 0c20edf2cf3..11ece34c024 100644
--- a/arch/arm/dts/fsl-imx8qxp-colibri.dts
+++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts
@@ -9,8 +9,8 @@
#include "fsl-imx8qxp-colibri-u-boot.dtsi"
/ {
- model = "Toradex Colibri iMX8QXP";
- compatible = "toradex,colibri-imx8qxp", "fsl,imx8qxp";
+ model = "Toradex Colibri iMX8X";
+ compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
chosen {
bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
@@ -32,7 +32,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
- colibri-imx8qxp {
+ colibri-imx8x {
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
diff --git a/arch/arm/dts/rv1108-u-boot.dtsi b/arch/arm/dts/rv1108-u-boot.dtsi
index 41ac054b81e..6a2098b8d41 100644
--- a/arch/arm/dts/rv1108-u-boot.dtsi
+++ b/arch/arm/dts/rv1108-u-boot.dtsi
@@ -4,3 +4,7 @@
*/
#include "rockchip-u-boot.dtsi"
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
index cb92fc9c141..1ae57e18542 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
@@ -75,6 +75,8 @@
};
pins2 {
u-boot,dm-pre-reloc;
+ /delete-property/ bias-disable;
+ bias-pull-up;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 7529068c517..c73318488d0 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -132,11 +132,11 @@
u-boot,dm-pre-reloc;
};
- /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
+ /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
- cfg = < 1 49 5 11 5 PQR(1,1,1) >;
+ cfg = < 3 98 5 7 5 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 75ff991248c..f37fe214460 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -41,9 +41,7 @@
#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
#define MXC_CPU_IMX8MP 0x182/* dummy ID */
-#define MXC_CPU_IMX8MP7 0x183 /* dummy ID */
#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */
-#define MXC_CPU_IMX8MP5 0x185 /* dummy ID */
#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */
#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
index 742cbf3bf80..340a61e55bd 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -316,7 +316,7 @@ enum clk_src_index {
#define FRAC_PLL_LOCK_MASK BIT(31)
#define FRAC_PLL_CLKE_MASK BIT(21)
#define FRAC_PLL_PD_MASK BIT(19)
-#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
+#define FRAC_PLL_REFCLK_SEL_MASK (0x3 << 16)
#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
#define FRAC_PLL_BYPASS_MASK BIT(14)
#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
@@ -358,10 +358,10 @@ enum clk_src_index {
#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
#define SSCG_PLL_REFCLK_SEL_MASK 0x3
-#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
-#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
-#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_25M (0)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M (1)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN (3)
#define SSCG_PLL_SSDS_MASK BIT(8)
#define SSCG_PLL_SSMD_MASK (0x7 << 5)
diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h
index f3515fab031..bfa68a9d2a0 100644
--- a/arch/arm/include/asm/arch-mx7/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx7/crm_regs.h
@@ -57,7 +57,7 @@ struct mxc_ccm_reg {
uint32_t reserved_0[4092];
struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
uint32_t reserved_1[3332];
- struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
+ struct mxc_ccm_root_slice root[125]; /* offset 0x8000 */
};
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 15d1cba8e74..5f0c1ae2182 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -67,13 +67,10 @@ struct bd_info;
#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL))
#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
- is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP7) || \
- is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MP5))
+ is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
-#define is_imx8mp7() (is_cpu_type(MXC_CPU_IMX8MP7))
#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
-#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index fe8d5947cce..4a175cb86f4 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -102,12 +102,8 @@ const char *get_imx_type(u32 imxtype)
return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
case MXC_CPU_IMX8MPL:
return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
- case MXC_CPU_IMX8MP7:
- return "8MP[7]"; /* Quad-core version of the imx8mp, VPU fused */
case MXC_CPU_IMX8MP6:
return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
- case MXC_CPU_IMX8MP5:
- return "8MP[5]"; /* Quad-core version of the imx8mp, ISP fused */
case MXC_CPU_IMX8MN:
return "8MNano Quad"; /* Quad-core version */
case MXC_CPU_IMX8MND:
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 3610f5b2fca..9dde11cdedf 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -360,6 +360,7 @@ void init_clk_ecspi(u32 index)
clock_enable(CCGR_ECSPI2, 0);
clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
clock_enable(CCGR_ECSPI2, 1);
+ return;
case 2:
clock_enable(CCGR_ECSPI3, 0);
clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 8dfc8645fc0..9bca5bf9727 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -343,12 +343,8 @@ static u32 get_cpu_variant_type(u32 type)
switch (flag) {
case 7:
return MXC_CPU_IMX8MPL;
- case 6:
- return MXC_CPU_IMX8MP5;
case 2:
return MXC_CPU_IMX8MP6;
- case 1:
- return MXC_CPU_IMX8MP7;
default:
break;
}
@@ -889,16 +885,16 @@ usb_modify_speed:
disable_cpu_nodes(blob, 3);
#elif defined(CONFIG_IMX8MP)
- if (is_imx8mpl() || is_imx8mp7())
+ if (is_imx8mpl())
disable_vpu_nodes(blob);
- if (is_imx8mpl() || is_imx8mp6() || is_imx8mp5())
+ if (is_imx8mpl() || is_imx8mp6())
disable_npu_nodes(blob);
- if (is_imx8mpl() || is_imx8mp5())
+ if (is_imx8mpl())
disable_isp_nodes(blob);
- if (is_imx8mpl() || is_imx8mp7() || is_imx8mp6() || is_imx8mp5())
+ if (is_imx8mpl() || is_imx8mp6())
disable_dsp_nodes(blob);
if (is_imx8mpd())
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index 16df71083db..f872bfdab31 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -250,16 +250,31 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
static void mmdc_set_sdqs(bool set)
{
+ struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux =
+ (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
(struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+ struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux =
+ (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
+ struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux =
+ (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
int i, sdqs_cnt;
u32 sdqs;
if (is_mx6sx()) {
sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
sdqs_cnt = 2;
+ } else if (is_mx6sl()) {
+ sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 2;
+ } else if (is_mx6ul() || is_mx6ull()) {
+ sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 2;
+ } else if (is_mx6sdl()) {
+ sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0);
+ sdqs_cnt = 8;
} else { /* MX6DQ */
sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
sdqs_cnt = 8;
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 0042e57017f..7f40ba93190 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -47,10 +47,10 @@ config TARGET_MT8512
select ARM64
select MT8512
help
- The MediaTek MT8512 is a ARM64-based SoC with a quad-core Cortex-A53.
+ The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53.
including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
- Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
- chip and several DDR3 and DDR4 options.
+ IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital
+ and several LPDDR3 and LPDDR4 options.
config TARGET_MT8516
bool "MediaTek MT8516 SoC"
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py
index d15c32b3032..f3224d25552 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -189,8 +189,9 @@ def unpack_elf(filename):
p_type, p_flags, p_offset = struct.unpack_from('<LLQ', elf, offset)
if p_type == 1: # PT_LOAD
p_paddr, p_filesz = struct.unpack_from('<2Q', elf, offset + 0x18)
- p_data = elf[p_offset:p_offset + p_filesz]
- segments.append((index, e_entry, p_paddr, p_data))
+ if p_filesz > 0:
+ p_data = elf[p_offset:p_offset + p_filesz]
+ segments.append((index, e_entry, p_paddr, p_data))
return segments
def main():
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index b7fcee2b367..f19e5c3f33a 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -580,8 +580,8 @@ __weak int setup_mac_address(void)
return -EINVAL;
}
pr_debug("OTP MAC address = %pM\n", enetaddr);
- ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
- if (!ret)
+ ret = eth_env_set_enetaddr("ethaddr", enetaddr);
+ if (ret)
pr_err("Failed to set mac address %pM from OTP: %d\n",
enetaddr, ret);
#endif
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 05:01:10 +0000