summaryrefslogtreecommitdiff
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/dts/armada-375.dtsi5
-rw-r--r--arch/arm/dts/armada-380.dtsi3
-rw-r--r--arch/arm/dts/armada-385.dtsi4
-rw-r--r--arch/arm/dts/armada-38x.dtsi1
-rw-r--r--arch/arm/dts/armada-cp110.dtsi2
-rw-r--r--arch/arm/dts/armada-xp-98dx3236.dtsi2
-rw-r--r--arch/arm/dts/armada-xp-mv78230.dtsi5
-rw-r--r--arch/arm/dts/armada-xp-mv78260.dtsi9
-rw-r--r--arch/arm/dts/armada-xp-mv78460.dtsi10
-rw-r--r--arch/arm/dts/armada-xp-synology-ds414.dts1
-rw-r--r--arch/arm/dts/armada-xp-theadorable.dts1
-rw-r--r--arch/arm/dts/armada-xp.dtsi1
-rw-r--r--arch/arm/mach-mvebu/Makefile26
-rw-r--r--arch/arm/mach-mvebu/include/mach/cpu.h5
-rw-r--r--arch/arm/mach-mvebu/kwbimage.cfg.in10
-rw-r--r--arch/arm/mach-mvebu/serdes/a38x/Makefile1
-rw-r--r--arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c64
-rw-r--r--arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h28
-rw-r--r--arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c19
-rw-r--r--arch/arm/mach-mvebu/system-controller.c105
20 files changed, 182 insertions, 120 deletions
diff --git a/arch/arm/dts/armada-375.dtsi b/arch/arm/dts/armada-375.dtsi
index 62a548a55f3..ff0ad7a9c7f 100644
--- a/arch/arm/dts/armada-375.dtsi
+++ b/arch/arm/dts/armada-375.dtsi
@@ -384,9 +384,10 @@
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
- system-controller@18200 {
+ systemc: system-controller@18200 {
compatible = "marvell,armada-375-system-controller";
reg = <0x18200 0x100>;
+ #reset-cells = <2>;
};
gateclk: clock-gating-control@18220 {
@@ -616,6 +617,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -634,6 +636,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
diff --git a/arch/arm/dts/armada-380.dtsi b/arch/arm/dts/armada-380.dtsi
index cff1269f3fb..f3d7f4b27dd 100644
--- a/arch/arm/dts/armada-380.dtsi
+++ b/arch/arm/dts/armada-380.dtsi
@@ -73,6 +73,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -92,6 +93,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -111,6 +113,7 @@
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
+ resets = <&systemc 0 2>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/armada-385.dtsi b/arch/arm/dts/armada-385.dtsi
index f0022d10c71..581a7d9beac 100644
--- a/arch/arm/dts/armada-385.dtsi
+++ b/arch/arm/dts/armada-385.dtsi
@@ -78,6 +78,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -97,6 +98,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -116,6 +118,7 @@
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
+ resets = <&systemc 0 2>;
status = "disabled";
};
@@ -138,6 +141,7 @@
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 7>;
+ resets = <&systemc 0 3>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi
index 72c49beb71a..061bd785208 100644
--- a/arch/arm/dts/armada-38x.dtsi
+++ b/arch/arm/dts/armada-38x.dtsi
@@ -328,6 +328,7 @@
compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
+ #reset-cells = <2>;
};
gateclk: clock-gating-control@18220 {
diff --git a/arch/arm/dts/armada-cp110.dtsi b/arch/arm/dts/armada-cp110.dtsi
index abf1e4ea087..ddc10d23740 100644
--- a/arch/arm/dts/armada-cp110.dtsi
+++ b/arch/arm/dts/armada-cp110.dtsi
@@ -231,7 +231,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&CP110_LABEL(syscon0) 1 2>;
- nand-enable-arbiter;
+ marvell,nand-enable-arbiter;
num-cs = <1>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
diff --git a/arch/arm/dts/armada-xp-98dx3236.dtsi b/arch/arm/dts/armada-xp-98dx3236.dtsi
index 5df1d1848db..1a48ff3c616 100644
--- a/arch/arm/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/dts/armada-xp-98dx3236.dtsi
@@ -85,6 +85,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
};
@@ -136,6 +137,7 @@
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
+ #reset-cells = <2>;
};
gateclk: clock-gating-control@18220 {
diff --git a/arch/arm/dts/armada-xp-mv78230.dtsi b/arch/arm/dts/armada-xp-mv78230.dtsi
index 8558bf6bb54..63d7f48cf45 100644
--- a/arch/arm/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/dts/armada-xp-mv78230.dtsi
@@ -92,6 +92,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -110,6 +111,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -128,6 +130,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -146,6 +149,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -164,6 +168,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/armada-xp-mv78260.dtsi b/arch/arm/dts/armada-xp-mv78260.dtsi
index 2d85fe8ac32..5dc413dd14b 100644
--- a/arch/arm/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/dts/armada-xp-mv78260.dtsi
@@ -107,6 +107,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -125,6 +126,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -143,6 +145,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -161,6 +164,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -179,6 +183,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -197,6 +202,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -215,6 +221,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -233,6 +240,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -251,6 +259,7 @@
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
+ resets = <&systemc 0 2>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/armada-xp-mv78460.dtsi b/arch/arm/dts/armada-xp-mv78460.dtsi
index 230a3fd36b3..6fbd0ce215f 100644
--- a/arch/arm/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/dts/armada-xp-mv78460.dtsi
@@ -128,6 +128,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -146,6 +147,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -164,6 +166,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -182,6 +185,7 @@
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
+ resets = <&systemc 0 0>;
status = "disabled";
};
@@ -200,6 +204,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -218,6 +223,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -236,6 +242,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -254,6 +261,7 @@
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
+ resets = <&systemc 0 1>;
status = "disabled";
};
@@ -272,6 +280,7 @@
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
+ resets = <&systemc 0 2>;
status = "disabled";
};
@@ -290,6 +299,7 @@
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
+ resets = <&systemc 0 3>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts
index 861967cd7e8..35909e3c69c 100644
--- a/arch/arm/dts/armada-xp-synology-ds414.dts
+++ b/arch/arm/dts/armada-xp-synology-ds414.dts
@@ -187,6 +187,7 @@
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
+ num-lanes = <4>;
};
/*
diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts
index 24cc1cc5278..a06a65af158 100644
--- a/arch/arm/dts/armada-xp-theadorable.dts
+++ b/arch/arm/dts/armada-xp-theadorable.dts
@@ -214,5 +214,6 @@
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
+ num-lanes = <4>;
};
};
diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi
index d856d960227..fb5640bbd93 100644
--- a/arch/arm/dts/armada-xp.dtsi
+++ b/arch/arm/dts/armada-xp.dtsi
@@ -78,6 +78,7 @@
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
+ #reset-cells = <2>;
};
gateclk: clock-gating-control@18220 {
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 7e9c206ed6b..a5a20877dda 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -21,6 +21,7 @@ else # CONFIG_ARCH_KIRKWOOD
obj-y = cpu.o
obj-y += dram.o
+obj-$(CONFIG_DM_RESET) += system-controller.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
@@ -30,6 +31,17 @@ obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
extra-y += kwbimage.cfg
+ifneq ($(CONFIG_ARMADA_370)$(CONFIG_ARMADA_XP),)
+ KWB_REPLACE += CPU
+ KWB_CFG_CPU = SHEEVA
+else ifneq ($(CONFIG_ARMADA_375)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
+ KWB_REPLACE += CPU
+ KWB_CFG_CPU = A9
+endif
+
+KWB_REPLACE += LOAD_ADDRESS
+KWB_CFG_LOAD_ADDRESS = $(CONFIG_SPL_TEXT_BASE)
+
KWB_REPLACE += BOOT_FROM
ifneq ($(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI),)
KWB_CFG_BOOT_FROM=spi
@@ -58,10 +70,20 @@ KWB_REPLACE += SEC_FUSE_DUMP
KWB_CFG_SEC_FUSE_DUMP = a38x
endif
+ifdef CONFIG_ARMADA_38X
+# BootROM output is by default enabled on pre-A38x and disabled on A38x
+# DEBUG flag on A38x for non-UART boot source only enable BootROM output and nothing more
+KWB_REPLACE += DEBUG
+KWB_CFG_DEBUG = 1
+endif
+
+quiet_cmd_kwbcfg = KWBCFG $@
+cmd_kwbcfg = sed -ne '$(foreach V,$(KWB_REPLACE),s/\#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \
+ <$< >$(dir $@)$(@F)
+
$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
include/config/auto.conf
- $(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \
- <$< >$(dir $@)$(@F)
+ $(call cmd,kwbcfg)
endif # CONFIG_SPL_BUILD
obj-y += gpio.o
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index a7a62c7e7d5..b99d86a87a0 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -74,10 +74,11 @@ enum {
/*
* Default Device Address MAP BAR values
*/
+#define MBUS_PCI_MAX_PORTS 6
#define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX
-#define MBUS_PCI_MEM_SIZE (128 << 20)
+#define MBUS_PCI_MEM_SIZE ((MBUS_PCI_MAX_PORTS * 128) << 20)
#define MBUS_PCI_IO_BASE 0xF1100000
-#define MBUS_PCI_IO_SIZE (64 << 10)
+#define MBUS_PCI_IO_SIZE ((MBUS_PCI_MAX_PORTS * 64) << 10)
#define MBUS_SPI_BASE 0xF4000000
#define MBUS_SPI_SIZE (8 << 20)
#define MBUS_DFX_BASE 0xF6000000
diff --git a/arch/arm/mach-mvebu/kwbimage.cfg.in b/arch/arm/mach-mvebu/kwbimage.cfg.in
index 049d23c6ef0..ccb09975817 100644
--- a/arch/arm/mach-mvebu/kwbimage.cfg.in
+++ b/arch/arm/mach-mvebu/kwbimage.cfg.in
@@ -5,8 +5,14 @@
# Armada 38x uses version 1 image format
VERSION 1
+# Type of the CPU core
+#@CPU
+
# Boot Media configurations
#@BOOT_FROM
-# Binary Header (bin_hdr) with DDR3 training code
-BINARY spl/u-boot-spl.bin
+# Enable BootROM output via DEBUG flag on SoCs which require it
+#@DEBUG
+
+# Include U-Boot SPL with DDR3 training code into Binary Header
+BINARY spl/u-boot-spl.bin #@LOAD_ADDRESS
diff --git a/arch/arm/mach-mvebu/serdes/a38x/Makefile b/arch/arm/mach-mvebu/serdes/a38x/Makefile
index 917fc1350ce..5a70b375966 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/Makefile
+++ b/arch/arm/mach-mvebu/serdes/a38x/Makefile
@@ -1,6 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_SPL_BUILD) = ctrl_pex.o
obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec-38x.o
obj-$(CONFIG_SPL_BUILD) += seq_exec.o
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
deleted file mode 100644
index 55c3f9ca390..00000000000
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-
-#include "ctrl_pex.h"
-#include "sys_env_lib.h"
-
-__weak void board_pex_config(void)
-{
- /* nothing in this weak default implementation */
-}
-
-int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
-{
- enum serdes_type serdes_type;
- u32 idx, tmp;
-
- DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
-
- tmp = reg_read(SOC_CONTROL_REG1);
- tmp &= ~0x03;
-
- for (idx = 0; idx < count; idx++) {
- serdes_type = serdes_map[idx].serdes_type;
- if ((serdes_type != PEX0) &&
- ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
- (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
- /* for PEX by4 - relevant for the first port only */
- continue;
- }
-
- switch (serdes_type) {
- case PEX0:
- tmp |= 0x1 << PCIE0_ENABLE_OFFS;
- break;
- case PEX1:
- tmp |= 0x1 << PCIE1_ENABLE_OFFS;
- break;
- case PEX2:
- tmp |= 0x1 << PCIE2_ENABLE_OFFS;
- break;
- case PEX3:
- tmp |= 0x1 << PCIE3_ENABLE_OFFS;
- break;
- default:
- break;
- }
- }
-
- reg_write(SOC_CONTROL_REG1, tmp);
-
- board_pex_config();
-
- return MV_OK;
-}
diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
deleted file mode 100644
index 64193d52888..00000000000
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- */
-
-#ifndef _CTRL_PEX_H
-#define _CTRL_PEX_H
-
-#include <pci.h>
-#include "high_speed_env_spec.h"
-
-/* Direct access to PEX0 Root Port's PCIe Capability structure */
-#define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60)
-
-/* SOC_CONTROL_REG1 fields */
-#define PCIE0_ENABLE_OFFS 0
-#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
-#define PCIE1_ENABLE_OFFS 1
-#define PCIE1_ENABLE_MASK (0x1 << PCIE1_ENABLE_OFFS)
-#define PCIE2_ENABLE_OFFS 2
-#define PCIE2_ENABLE_MASK (0x1 << PCIE2_ENABLE_OFFS)
-#define PCIE3_ENABLE_OFFS 3
-#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
-
-int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
-void board_pex_config(void);
-
-#endif
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index 9ba60b57aac..2e467b546d5 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -12,7 +12,6 @@
#include "high_speed_env_spec.h"
#include "sys_env_lib.h"
-#include "ctrl_pex.h"
/*
* serdes_seq_db - holds all serdes sequences, their size and the
@@ -1555,9 +1554,6 @@ int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count)
After finish the Power_up sequence for all lanes,
the lanes should be released from reset state. */
CHECK_STATUS(hws_pex_tx_config_seq(serdes_map, count));
-
- /* PEX configuration */
- CHECK_STATUS(hws_pex_config(serdes_map, count));
}
/* USB2 configuration */
@@ -1743,21 +1739,6 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
else
reg_data &= ~0x4000;
reg_write(SOC_CONTROL_REG1, reg_data);
-
- /*
- * Set Maximum Link Width to X1 or X4 in Root
- * Port's PCIe Link Capability register.
- * This register is read-only but if is not set
- * correctly then access to PCI config space of
- * endpoint card behind this Root Port does not
- * work.
- */
- reg_data = reg_read(PEX0_RP_PCIE_CFG_OFFSET +
- PCI_EXP_LNKCAP);
- reg_data &= ~PCI_EXP_LNKCAP_MLW;
- reg_data |= (is_pex_by1 ? 1 : 4) << 4;
- reg_write(PEX0_RP_PCIE_CFG_OFFSET +
- PCI_EXP_LNKCAP, reg_data);
}
CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
new file mode 100644
index 00000000000..ea858b269e8
--- /dev/null
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+// (C) 2021 Pali Rohár <pali@kernel.org>
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/io.h>
+
+#define MVEBU_SOC_CONTROL_1_REG 0x4
+
+#define MVEBU_PCIE_ID 0
+
+struct mvebu_reset_data {
+ void *base;
+};
+
+static int mvebu_reset_of_xlate(struct reset_ctl *rst,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count < 2)
+ return -EINVAL;
+
+ rst->id = args->args[0];
+ rst->data = args->args[1];
+
+ /* Currently only PCIe is implemented */
+ if (rst->id != MVEBU_PCIE_ID)
+ return -EINVAL;
+
+ /* Four PCIe enable bits are shared across more PCIe links */
+ if (!(rst->data >= 0 && rst->data <= 3))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int mvebu_reset_request(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int mvebu_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int mvebu_reset_assert(struct reset_ctl *rst)
+{
+ struct mvebu_reset_data *data = dev_get_priv(rst->dev);
+
+ clrbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data));
+ return 0;
+}
+
+static int mvebu_reset_deassert(struct reset_ctl *rst)
+{
+ struct mvebu_reset_data *data = dev_get_priv(rst->dev);
+
+ setbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data));
+ return 0;
+}
+
+static int mvebu_reset_status(struct reset_ctl *rst)
+{
+ struct mvebu_reset_data *data = dev_get_priv(rst->dev);
+
+ return !(readl(data->base + MVEBU_SOC_CONTROL_1_REG) & BIT(rst->data));
+}
+
+static int mvebu_reset_of_to_plat(struct udevice *dev)
+{
+ struct mvebu_reset_data *data = dev_get_priv(dev);
+
+ data->base = (void *)dev_read_addr(dev);
+ if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct udevice_id mvebu_reset_of_match[] = {
+ { .compatible = "marvell,armada-370-xp-system-controller" },
+ { .compatible = "marvell,armada-375-system-controller" },
+ { .compatible = "marvell,armada-380-system-controller" },
+ { .compatible = "marvell,armada-390-system-controller" },
+ { },
+};
+
+static struct reset_ops mvebu_reset_ops = {
+ .of_xlate = mvebu_reset_of_xlate,
+ .request = mvebu_reset_request,
+ .rfree = mvebu_reset_free,
+ .rst_assert = mvebu_reset_assert,
+ .rst_deassert = mvebu_reset_deassert,
+ .rst_status = mvebu_reset_status,
+};
+
+U_BOOT_DRIVER(mvebu_reset) = {
+ .name = "mvebu-reset",
+ .id = UCLASS_RESET,
+ .of_match = mvebu_reset_of_match,
+ .of_to_plat = mvebu_reset_of_to_plat,
+ .priv_auto = sizeof(struct mvebu_reset_data),
+ .ops = &mvebu_reset_ops,
+};
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 13:04:10 +0000