diff options
Diffstat (limited to 'arch/arm')
94 files changed, 0 insertions, 416 deletions
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 07ab04b7b08..0e100e6f13d 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -44,7 +44,6 @@ int cleanup_before_linux (void) disable_interrupts(); - /* turn off I/D-cache */ icache_disable(); dcache_disable(); diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index f25a8674dea..36c557d4a8f 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -49,7 +49,6 @@ unsigned long long get_ticks(void) return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; } - ulong timer_get_boot_us(void) { if (!gd->arch.timer_rate_hz) diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index b769c451105..fa8af1b6941 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -84,7 +84,6 @@ static int peri_clk_enable(struct clk *c, int enable) struct bcm_clk_gate *gate = &cd->gate; void *base = (void *)c->ccu_clk_mgr_base; - debug("%s: %s\n", __func__, c->name); clk_get_rate(c); /* Make sure rate and sel are filled in */ diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c index 3f2e021a307..71b3a9277b1 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -84,7 +84,6 @@ static int peri_clk_enable(struct clk *c, int enable) struct bcm_clk_gate *gate = &cd->gate; void *base = (void *)c->ccu_clk_mgr_base; - debug("%s: %s\n", __func__, c->name); clk_get_rate(c); /* Make sure rate and sel are filled in */ diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 74a2dcbc116..dccf2fb3eb1 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -224,7 +224,6 @@ void enable_caches(void) } #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ - uint get_svr(void) { struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 45af7662075..4a4d5be2bd6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -150,7 +150,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-385-atl-x530.dtb \ armada-385-atl-x530DP.dtb \ armada-385-db-88f6820-amc.dtb \ - armada-385-synology-ds116.dtb \ armada-385-thecus-n2350.dtb \ armada-385-turris-omnia.dtb \ armada-388-clearfog.dtb \ diff --git a/arch/arm/dts/armada-385-synology-ds116.dts b/arch/arm/dts/armada-385-synology-ds116.dts deleted file mode 100644 index 82a0373f7fb..00000000000 --- a/arch/arm/dts/armada-385-synology-ds116.dts +++ /dev/null @@ -1,291 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree file for Synology DS116 NAS - * - * Copyright (C) 2017 Willy Tarreau <w@1wt.eu> - */ - -/dts-v1/; -#include "armada-385.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Synology DS116"; - compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x40000000>; /* 1 GB */ - }; - - soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 - MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 - MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; - - internal-regs { - i2c@11000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - clock-frequency = <100000>; - - eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - }; - }; - - serial@12000 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; - }; - - serial@12100 { - /* A PIC16F1829 is connected to uart1 at 9600 bps, - * and takes single-character orders : - * "1" : power off // already handled by the poweroff node - * "2" : short beep - * "3" : long beep - * "4" : turn the power LED ON - * "5" : flash the power LED - * "6" : turn the power LED OFF - * "7" : turn the status LED OFF - * "8" : turn the status LED ON - * "9" : flash the status LED - * "A" : flash the motherboard LED (D8) - * "B" : turn the motherboard LED OFF - * "C" : hard reset - */ - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; - }; - - poweroff@12100 { - compatible = "synology,power-off"; - reg = <0x12100 0x100>; - clocks = <&coreclk 0>; - }; - - ethernet@70000 { - pinctrl-names = "default"; - phy = <&phy0>; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <0>; - status = "okay"; - }; - - mdio@72004 { - pinctrl-names = "default"; - pinctrl-0 = <&mdio_pins>; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; - - sata@a8000 { - pinctrl-names = "default"; - pinctrl-0 = <&sata0_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - sata0: sata-port@0 { - reg = <0>; - target-supply = <®_5v_sata0>; - }; - }; - - bm@c8000 { - status = "okay"; - }; - - usb3@f0000 { - usb-phy = <&usb3_0_phy>; - status = "okay"; - }; - - usb3@f8000 { - usb-phy = <&usb3_1_phy>; - status = "okay"; - }; - }; - - bm-bppi { - status = "okay"; - }; - - gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>, - <&gpio1 17 GPIO_ACTIVE_HIGH>, - <&gpio1 16 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 1500 1 - 2500 2 - 3000 3 - 3400 4 - 3700 5 - 3900 6 - 4000 7>; - #cooling-cells = <2>; - }; - - gpio-leds { - compatible = "gpio-leds"; - - /* The green part is on gpio0.20 which is also used by - * sata0, and accesses to SATA disk 0 make it blink so it - * doesn't need to be declared here. - */ - orange { - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - label = "ds116:orange:disk"; - default-state = "off"; - }; - }; - }; - - usb3_0_phy: usb3_0_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_0_vbus>; - #phy-cells = <0>; - }; - - usb3_1_phy: usb3_1_phy { - compatible = "usb-nop-xceiv"; - vcc-supply = <®_usb3_1_vbus>; - #phy-cells = <0>; - }; - - reg_usb3_0_vbus: usb3-vbus0 { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus0"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci0_vbus_pins>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - }; - - reg_usb3_1_vbus: usb3-vbus1 { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus1"; - pinctrl-names = "default"; - pinctrl-0 = <&xhci1_vbus_pins>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - }; - - reg_sata0: pwr-sata0 { - compatible = "regulator-fixed"; - regulator-name = "pwr_en_sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - enable-active-high; - regulator-boot-on; - gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - - reg_5v_sata0: v5-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v5.0-sata0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_sata0>; - }; - - reg_12v_sata0: v12-sata0 { - compatible = "regulator-fixed"; - regulator-name = "v12.0-sata0"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - vin-supply = <®_sata0>; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "macronix,mx25l6405d", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - - /* Note: there is a redboot partition table despite u-boot - * being used. The names presented here are the same as those - * found in the FIS directory. There is also a small device - * tree in the last 64kB of the RedBoot partition which is not - * enumerated. The MAC address and the serial number are listed - * in the "vendor" partition. - */ - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x000f0000>; - read-only; - }; - - partition@c0000 { - label = "zImage"; - reg = <0x000f0000 0x002d0000>; - }; - - partition@390000 { - label = "rd.gz"; - reg = <0x003c0000 0x00410000>; - }; - - partition@7d0000 { - label = "vendor"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - - partition@7e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; - read-only; - }; - - partition@7f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; - read-only; - }; - }; -}; - -&pinctrl { - /* use only one pin for UART1, as mpp20 is used by sata0 */ - uart1_pins: uart-pins-1 { - marvell,pins = "mpp19"; - marvell,function = "ua1"; - }; - - xhci0_vbus_pins: xhci0_vbus_pins { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - xhci1_vbus_pins: xhci1_vbus_pins { - marvell,pins = "mpp59"; - marvell,function = "gpio"; - }; -}; diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h index b7b7322a2d1..6775e4e3371 100644 --- a/arch/arm/dts/vf610-pinfunc.h +++ b/arch/arm/dts/vf610-pinfunc.h @@ -20,7 +20,6 @@ #define ALT6 0x6 #define ALT7 0x7 - #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 #define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ca5e33379ba..306f797f7a8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -190,7 +190,6 @@ #define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_USFCFG_MASK 0x00000400 - /* PCIe */ #define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h index c18c51ed2c7..b08274e361b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -37,7 +37,6 @@ * */ - #define FSL_INVALID_STREAM_ID 0 /* legacy devices */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 140849d4e1f..09199dfad25 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -97,7 +97,6 @@ #define FSL_PEX_STREAM_ID_END (0x100) #endif - /* DPAA2 - set in MC DPC and alloced by MC */ #define FSL_DPAA2_STREAM_ID_START 23 #define FSL_DPAA2_STREAM_ID_END 63 diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h index b98b45cc817..bcde48e4737 100644 --- a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -49,5 +49,4 @@ #define USB2_PHY01_REFCLK_SEL (1 << 12) #define USB2_PHY2_REFCLK_SEL (1 << 14) - #endif diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h b/arch/arm/include/asm/arch-hi6220/hi6220.h index 55729e306e4..6d8bba6f7eb 100644 --- a/arch/arm/include/asm/arch-hi6220/hi6220.h +++ b/arch/arm/include/asm/arch-hi6220/hi6220.h @@ -133,7 +133,6 @@ struct peri_sc_periph_regs { u32 reserved8_addr; /*0xd04*/ }; - /* CTRL1 bit definitions */ #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) @@ -143,7 +142,6 @@ struct peri_sc_periph_regs { #define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) #define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) - /* CTRL2 bit definitions */ #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) diff --git a/arch/arm/include/asm/arch-hi6220/pinmux.h b/arch/arm/include/asm/arch-hi6220/pinmux.h index d18d2142f6a..7ee51000d69 100644 --- a/arch/arm/include/asm/arch-hi6220/pinmux.h +++ b/arch/arm/include/asm/arch-hi6220/pinmux.h @@ -9,7 +9,6 @@ #include "periph.h" - /* iomg bit definition */ #define MUX_M0 0 #define MUX_M1 1 diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 41160384a4d..b2d87524f70 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -8,7 +8,6 @@ #ifndef _LPC32XX_CONFIG_H #define _LPC32XX_CONFIG_H - /* Basic CPU architecture */ #if !defined(CFG_SYS_NS16550_CLK) diff --git a/arch/arm/include/asm/arch-meson/gpio.h b/arch/arm/include/asm/arch-meson/gpio.h index d0142f16ef1..9eb42211579 100644 --- a/arch/arm/include/asm/arch-meson/gpio.h +++ b/arch/arm/include/asm/arch-meson/gpio.h @@ -6,5 +6,4 @@ #ifndef __ASM_ARCH_MESON_GPIO_H #define __ASM_ARCH_MESON_GPIO_H - #endif /* __ASM_ARCH_MESON_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx27/gpio.h b/arch/arm/include/asm/arch-mx27/gpio.h index 9f342eb7f71..af05d1eb887 100644 --- a/arch/arm/include/asm/arch-mx27/gpio.h +++ b/arch/arm/include/asm/arch-mx27/gpio.h @@ -4,7 +4,6 @@ * Philippe Reynes <tremyfr@yahoo.fr> */ - #ifndef __ASM_ARCH_MX27_GPIO_H #define __ASM_ARCH_MX27_GPIO_H diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 77794d7d03d..60499189b2c 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -236,7 +236,6 @@ struct fuse_bank0_regs { #define SDCS1_SEL (1 << 1) #define SDCS0_SEL (1 << 0) - /* important definition of some bits of WCR */ #define WCR_WDE 0x04 diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h index 45e9fc61937..1bfe28f95c9 100644 --- a/arch/arm/include/asm/arch-mx31/gpio.h +++ b/arch/arm/include/asm/arch-mx31/gpio.h @@ -4,7 +4,6 @@ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> */ - #ifndef __ASM_ARCH_MX31_GPIO_H #define __ASM_ARCH_MX31_GPIO_H diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index a0ab3a0e665..a608732f765 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -585,7 +585,6 @@ struct esdc_regs { #define GET_PLL_MFI(x) (((x) >> 10) & 0xf) #define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) - #define WEIM_ESDCTL0 0xB8001000 #define WEIM_ESDCFG0 0xB8001004 #define WEIM_ESDCTL1 0xB8001008 @@ -777,7 +776,6 @@ struct esdc_regs { #define MUX_CTL_NFC_ALE 0xD6 #define MUX_CTL_NFC_CLE 0xD7 - #define MUX_CTL_CAPTURE 0x150 #define MUX_CTL_COMPARE 0x151 diff --git a/arch/arm/include/asm/arch-mx5/gpio.h b/arch/arm/include/asm/arch-mx5/gpio.h index dad40bd3d7e..98f9d63e9a8 100644 --- a/arch/arm/include/asm/arch-mx5/gpio.h +++ b/arch/arm/include/asm/arch-mx5/gpio.h @@ -4,7 +4,6 @@ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> */ - #ifndef __ASM_ARCH_MX5_GPIO_H #define __ASM_ARCH_MX5_GPIO_H diff --git a/arch/arm/include/asm/arch-mx6/gpio.h b/arch/arm/include/asm/arch-mx6/gpio.h index b3913199337..f5c8d336991 100644 --- a/arch/arm/include/asm/arch-mx6/gpio.h +++ b/arch/arm/include/asm/arch-mx6/gpio.h @@ -4,7 +4,6 @@ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> */ - #ifndef __ASM_ARCH_MX6_GPIO_H #define __ASM_ARCH_MX6_GPIO_H diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8fd3dd2df3a..7f216c70e8b 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -385,7 +385,6 @@ ((is_mx6ull()) ? \ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) - extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); #define SRC_SCR_CORE_1_RESET_OFFSET 14 diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index bfa68a9d2a0..bb2642d46c8 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -229,7 +229,6 @@ struct mxc_ccm_anatop_reg { #define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) #define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) - #define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f #define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B #define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 @@ -1784,7 +1783,6 @@ struct mxc_ccm_anatop_reg { #define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 #define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) - /* HW_ANADIG_TEMPSENSE0 Bit Fields */ #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 @@ -1998,7 +1996,6 @@ struct mxc_ccm_anatop_reg { #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) - #define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i)) #define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i)) #define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i)) @@ -2091,7 +2088,6 @@ struct mxc_ccm_anatop_reg { #define CLK_ROOT_ALT6 0x06000000 #define CLK_ROOT_ALT7 0x07000000 - #define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 #define CLK_ROOT_POST_DIV_MASK 0x0000003f #define CLK_ROOT_POST_DIV_SHIFT 0 diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 6f5ae5173c0..849c5482241 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -71,7 +71,6 @@ #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) - /* Defines for Blocks connected via AIPS (SkyBlue) */ #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR @@ -1162,7 +1161,6 @@ struct rdc_sema_regs { #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 - extern void check_cpu_temperature(void); extern void pcie_power_up(void); diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 33a699ff71a..02e434f2e65 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -124,7 +124,6 @@ #define IOMUXC_PSMI_IMUX_ALT6 (0x6) #define IOMUXC_PSMI_IMUX_ALT7 (0x7) - #define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) #define SIM_SOPT1_PMIC_STBY_REQ (1<<2) #define SIM_SOPT1_A7_SW_RESET (1<<0) @@ -240,7 +239,6 @@ #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) #define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) - #define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) #define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) #define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h index f067c02062f..3eec2c78e56 100644 --- a/arch/arm/include/asm/arch-mx7ulp/iomux.h +++ b/arch/arm/include/asm/arch-mx7ulp/iomux.h @@ -69,7 +69,6 @@ typedef u64 iomux_cfg_t; #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ MUX_PAD_CTRL(pad)) - #define IOMUX_CONFIG_MPORTS 0x20 #define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ MUX_MODE_SHIFT) @@ -87,7 +86,6 @@ typedef u64 iomux_cfg_t; #define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) #define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) - void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, unsigned count); diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h index 8f0d7006286..09b9b9b8f34 100644 --- a/arch/arm/include/asm/arch-mx7ulp/pcc.h +++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h @@ -278,7 +278,6 @@ enum pcc3_entry { RSVD127_PCC3_SLOT = 127, }; - /* PCC registers */ #define PCC_PR_OFFSET 31 #define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) @@ -293,7 +292,6 @@ enum pcc3_entry { #define PCC_PCD_OFFSET 0 #define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) - enum pcc_clksrc_type { CLKSRC_PER_PLAT = 0, CLKSRC_PER_BUS = 1, @@ -353,7 +351,6 @@ enum pcc_clk { PER_CLK_GPU2D, }; - /* This structure keeps info for each pcc slot */ struct pcc_entry { u32 pcc_base; diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index 3b5b7f6803c..57e9fb2a27c 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -145,7 +145,6 @@ #define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000) - #define SCG_PLL_PFD3_GATE_MASK (0x80000000) #define SCG_PLL_PFD2_GATE_MASK (0x00800000) #define SCG_PLL_PFD1_GATE_MASK (0x00008000) diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index fce3568eca1..2b6cfde4114 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -463,7 +463,6 @@ enum { #define NET_LAN9221_GPMC_CONFIG6 0x87030000 #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c - /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index 39a7cba0f6b..2e34989ef9f 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -63,5 +63,4 @@ typedef struct t2 { #define OMAP_HSMMC2_BASE 0x480B4000 #define OMAP_HSMMC3_BASE 0x480AD000 - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index 4054dd8edcb..50436e828b0 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -100,7 +100,6 @@ #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - /* CM_<clock_domain>_<module>_CLKCTRL */ #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index b18ef459dec..eeb3c6f2a6c 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -111,7 +111,6 @@ #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - /* CM_<clock_domain>_<module>_CLKCTRL */ #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h index 1e44fb5ae97..efd816be2c6 100644 --- a/arch/arm/include/asm/arch-omap5/gpio.h +++ b/arch/arm/include/asm/arch-omap5/gpio.h @@ -33,7 +33,6 @@ #define OMAP54XX_GPIO7_BASE 0x48051000 #define OMAP54XX_GPIO8_BASE 0x48053000 - /* Get the GPIO index from the given bank number and bank gpio */ #define GPIO_TO_PIN(bank, bank_gpio) (32 * (bank - 1) + (bank_gpio)) diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h index 9559813e520..edacf102852 100644 --- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h @@ -532,7 +532,6 @@ check_member(rk3288_edp, pll_reg_5, 0xa00); #define EDID_HEADER 0x00 #define EDID_EXTENSION_FLAG 0x7e - enum dpcd_request { DPCD_READ, DPCD_WRITE, diff --git a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h index fb25504b12b..f4da391ba51 100644 --- a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h @@ -96,5 +96,4 @@ #define LVDS_24BIT (0 << 1) #define LVDS_18BIT (1 << 1) - #endif diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 14df3cc8f46..35ca0491ac9 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -262,7 +262,6 @@ struct sunxi_ccm_reg { #define CCM_DRAM_GATE_OFFSET_DE_BE0 26 #define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - #define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */ #define MBUS_CLK_GATE (0x1 << 31) @@ -295,7 +294,6 @@ struct sunxi_ccm_reg { #define APB2_RESET_TWI_SHIFT (0) #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) - #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int hz); void clock_set_pll5(unsigned int clk); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 0264bfe1c50..006f7761fc6 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -217,7 +217,6 @@ struct sunxi_ccm_reg { #define APB1_RESET_TWI_SHIFT 0 #define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) - #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int clk); void clock_set_pll6(unsigned int clk); diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index be02655cdd5..f0caecc807d 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -323,7 +323,6 @@ struct dram_para { const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; - static inline int ns_to_t(int nanoseconds) { const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h index 2a879963547..28b6560ff5b 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h @@ -146,7 +146,6 @@ struct sunxi_mctl_ctl_reg { u32 perfwr1; /* 0x1d8 */ }; - #define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x) #define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x) #define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h index 41df5fe5b6f..a77daecb107 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h @@ -40,7 +40,6 @@ struct sunxi_mctl_com_reg { u32 mdfstcr; /* 0x14c */ }; - struct sunxi_mctl_ctl_reg { u32 mstr; /* 0x00 master register */ u32 stat; /* 0x04 operating mode status register */ @@ -92,7 +91,6 @@ struct sunxi_mctl_ctl_reg { u32 perfwr1; /* 0x26c write CAM register 1 */ }; - struct sunxi_mctl_phy_reg { u8 res0[0x04]; /* 0x00 revision id ??? */ u32 pir; /* 0x04 PHY initialisation register */ diff --git a/arch/arm/include/asm/arch-tegra/bpmp_abi.h b/arch/arm/include/asm/arch-tegra/bpmp_abi.h index 373da526ed6..924361bab8d 100644 --- a/arch/arm/include/asm/arch-tegra/bpmp_abi.h +++ b/arch/arm/include/asm/arch-tegra/bpmp_abi.h @@ -29,7 +29,6 @@ * @file */ - /** * @defgroup MRQ MRQ Messages * @brief Messages sent to/from BPMP via IPC @@ -167,7 +166,6 @@ struct mrq_response { * @} */ - /** * @ingroup MRQ_Codes * @def MRQ_PING @@ -616,7 +614,6 @@ struct mrq_debugfs_response { #define DEBUGFS_S_IWUSR (1 << 7) /** @} */ - /** * @ingroup MRQ_Codes * @def MRQ_RESET diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 61ef81e7fe4..2957b97e6a5 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -130,7 +130,6 @@ void reset_periph(enum periph_id periph_id, int us_delay); */ void reset_set_enable(enum periph_id periph_id, int enable); - /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ enum crc_reset_id { /* Things we can hold in reset for each CPU */ diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h index bfde4c30ac0..9a53456370f 100644 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ b/arch/arm/include/asm/arch-tegra/warmboot.h @@ -117,7 +117,6 @@ union scratch3_reg { u32 word; }; - /** * Save warmboot memory settings for a later resume * diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h index 20cce7657e1..6a80be57506 100644 --- a/arch/arm/include/asm/byteorder.h +++ b/arch/arm/include/asm/byteorder.h @@ -15,7 +15,6 @@ #ifndef __ASM_ARM_BYTEORDER_H #define __ASM_ARM_BYTEORDER_H - #include <asm/types.h> #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 2141a4581c7..4a9e26f634d 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -880,7 +880,6 @@ struct dmm_lisa_map_regs { #define RL_FINAL 6 #endif - /* Interleaving policies at EMIF level- between banks and Chip Selects */ #define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 #define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 @@ -913,7 +912,6 @@ struct dmm_lisa_map_regs { */ #define READ_IDLE_INTERVAL_NORMAL (50*1000) - /* * Unless voltage is changing due to DVFS one ZQCS command every 50ms should * be enough. This shoule be enough also in the case when voltage is changing @@ -961,7 +959,6 @@ struct dmm_lisa_map_regs { #define REG_SR_TIM 0xF #define REG_PD_TIM 0xF - /* EMIF_PWR_MGMT_CTRL register */ #define EMIF_PWR_MGMT_CTRL (\ ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ diff --git a/arch/arm/include/asm/mach-imx/gpio.h b/arch/arm/include/asm/mach-imx/gpio.h index 25763526f5f..f7d751f4024 100644 --- a/arch/arm/include/asm/mach-imx/gpio.h +++ b/arch/arm/include/asm/mach-imx/gpio.h @@ -4,7 +4,6 @@ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> */ - #ifndef __ASM_ARCH_IMX_GPIO_H #define __ASM_ARCH_IMX_GPIO_H diff --git a/arch/arm/include/asm/mach-imx/mxc_i2c.h b/arch/arm/include/asm/mach-imx/mxc_i2c.h index e8b330f33d1..cf694de4970 100644 --- a/arch/arm/include/asm/mach-imx/mxc_i2c.h +++ b/arch/arm/include/asm/mach-imx/mxc_i2c.h @@ -91,7 +91,6 @@ struct mxc_i2c_bus { } \ }; - #define I2C_PADS_INFO(name) \ (is_mx6dq() || is_mx6dqp()) ? &mx6q_##name : &mx6s_##name #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 17fdfbcffb7..9945eeb66b8 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -814,7 +814,6 @@ static inline u8 is_dra76x_acd(void) #define HS_DEVICE 0x2 #define GP_DEVICE 0x3 - /* * SRAM scratch space entries */ diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h index 21b33442989..bc2f9e70810 100644 --- a/arch/arm/include/asm/opcodes.h +++ b/arch/arm/include/asm/opcodes.h @@ -15,7 +15,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); #define ARM_OPCODE_CONDTEST_PASS 1 #define ARM_OPCODE_CONDTEST_UNCOND 2 - /* * Assembler opcode byteswap helpers. * These are only intended for use by this header: don't use them directly, @@ -42,7 +41,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); #define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) #define ___asm_opcode_identity16(x) ((x) & 0xFFFF) - /* * Opcode byteswap helpers * @@ -94,7 +92,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); #endif /* ! __ASSEMBLY__ */ - #ifdef CONFIG_CPU_ENDIAN_BE8 #define __opcode_to_mem_arm(x) ___opcode_swab32(x) diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index e0e2d7e3606..b8ca50a6401 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -75,7 +75,6 @@ struct param_struct { char commandline[COMMAND_LINE_SIZE]; }; - /* * The new way of passing information: a list of tagged entries */ diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h index f51e47e55d5..6ca2c4ae6ff 100644 --- a/arch/arm/mach-at91/include/mach/at91_pio.h +++ b/arch/arm/mach-at91/include/mach/at91_pio.h @@ -13,7 +13,6 @@ #ifndef AT91_PIO_H #define AT91_PIO_H - #define AT91_ASM_PIO_RANGE 0x200 #define AT91_ASM_PIOC_ASR \ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index 40ec87e2ff9..6beab397ae1 100644 --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h @@ -59,7 +59,6 @@ struct atmel_mpddr { u32 version; /* 0xfc: IP version */ }; - int ddr2_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value); diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index ac6a719d9c0..acd7cc9301b 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -35,7 +35,6 @@ static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr) return 1; } - int ddr2_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value) diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 936b5e11667..78d50d4e719 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -146,7 +146,6 @@ static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) */ setbits_le32(®->pllctl, PLLCTL_PLLEN); - /* * clear EMIFA and EMIFB clock source settings, let them * run off SYSCLK diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index 4f56160ee50..a3fc7d9fbeb 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -61,7 +61,6 @@ enum l2_cache_params { CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27) }; - #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420) /* * Configure L2CTLR to get timings that keep us from hanging/crashing. diff --git a/arch/arm/mach-exynos/exynos4_setup.h b/arch/arm/mach-exynos/exynos4_setup.h index 23c9011fbc6..1a287a4ef6a 100644 --- a/arch/arm/mach-exynos/exynos4_setup.h +++ b/arch/arm/mach-exynos/exynos4_setup.h @@ -284,7 +284,6 @@ #define MFC_0_SEL MFC_SEL_MPLL #define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL)) - /* CLK_DIV_MFC */ #define MFC_RATIO 3 #define CLK_DIV_MFC_VAL (MFC_RATIO) @@ -498,7 +497,6 @@ struct mem_timings { | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\ | NUM_CHIP_2 | BL_8) - #define CHIP_BANK_8 (0x3 << 0) #define CHIP_ROW_14 (0x2 << 4) #define CHIP_COL_10 (0x3 << 8) diff --git a/arch/arm/mach-exynos/exynos5_setup.h b/arch/arm/mach-exynos/exynos5_setup.h index 4e508edba0c..6fa80221c8d 100644 --- a/arch/arm/mach-exynos/exynos5_setup.h +++ b/arch/arm/mach-exynos/exynos5_setup.h @@ -685,7 +685,6 @@ #define PWM_RATIO 8 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) - /* CLK_DIV_PERIC4 */ #define CLK_DIV_PERIC4_VAL NOT_AVAILABLE @@ -710,7 +709,6 @@ /* MPLL_CON1 */ #define MPLL_CON1_VAL (0x0020F300) - /* CPLL_CON1 */ #define CPLL_CON1_VAL 0x0020f300 @@ -720,7 +718,6 @@ /* GPLL_CON1 */ #define GPLL_CON1_VAL (NOT_AVAILABLE) - /* EPLL_CON1, CON2 */ #define EPLL_CON1_VAL 0x00000000 #define EPLL_CON2_VAL 0x00000080 @@ -750,7 +747,6 @@ #define CLK_DIV_ISP0_VAL 0x13131300 #define CLK_DIV_ISP1_VAL 0xbb110202 - /* CLK_FSYS */ #define CLK_SRC_FSYS0_VAL 0x33033300 #define CLK_DIV_FSYS0_VAL 0x0 diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h index dab148e3320..cf4580be189 100644 --- a/arch/arm/mach-exynos/include/mach/cpu.h +++ b/arch/arm/mach-exynos/include/mach/cpu.h @@ -190,7 +190,6 @@ #define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE - #ifndef __ASSEMBLY__ #include <asm/io.h> /* CPU detection macros */ diff --git a/arch/arm/mach-exynos/include/mach/dp_info.h b/arch/arm/mach-exynos/include/mach/dp_info.h index 3226eb95f01..a7f7667afd6 100644 --- a/arch/arm/mach-exynos/include/mach/dp_info.h +++ b/arch/arm/mach-exynos/include/mach/dp_info.h @@ -183,7 +183,6 @@ enum { VIDEO_TIMING_FROM_REGISTER }; - struct exynos_dp_platform_data { struct exynos_dp_priv *edp_dev_info; }; diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h index 757e1586bde..32534116cf8 100644 --- a/arch/arm/mach-exynos/include/mach/power.h +++ b/arch/arm/mach-exynos/include/mach/power.h @@ -1752,7 +1752,6 @@ void set_xclkout(void); */ uint32_t get_reset_status(void); - /* Read the resume function and call it */ void power_exit_wakeup(void); diff --git a/arch/arm/mach-exynos/include/mach/sound.h b/arch/arm/mach-exynos/include/mach/sound.h index 1a40e35f0b5..9672e977f07 100644 --- a/arch/arm/mach-exynos/include/mach/sound.h +++ b/arch/arm/mach-exynos/include/mach/sound.h @@ -4,7 +4,6 @@ * Rajeshwari Shinde <rajeshwari.s@samsung.com> */ - #ifndef __SOUND_ARCH_H__ #define __SOUND_ARCH_H__ diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 4061dd4aafa..07d19fd17ba 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -391,7 +391,6 @@ static void exynos5420_i2s_config(int peripheral) } } - void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index 599d3ccff60..1b61da6dc1a 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -20,7 +20,6 @@ static void exynos4_mipi_phy_control(unsigned int dev_index, else addr = (unsigned int)&pmu->mipi_phy1_control; - cfg = readl(addr); if (enable) cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); @@ -174,7 +173,6 @@ void set_ps_hold_ctrl(void) exynos5_set_ps_hold_ctrl(); } - static void exynos5_set_xclkout(void) { struct exynos5_power *power = diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index b368db49fce..7b3eacb43ed 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -86,7 +86,6 @@ void v7_outer_cache_enable(void) struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; unsigned int val, cache_id; - /* * Must disable the L2 before changing the latency parameters * and auxiliary control register. diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 627baa1d83f..accba502e49 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -519,7 +519,6 @@ phys_size_t get_effective_memsize(void) board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, &phys_sdram_2_start, &phys_sdram_2_size); - end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); @@ -699,7 +698,6 @@ static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, &phys_sdram_2_start, &phys_sdram_2_size); - end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 7e6c3748716..43e677deae2 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -733,7 +733,6 @@ static int frac_pll_init(u32 pll, enum frac_pll_out_val val) return 0; } - int clock_init(void) { u32 grade; diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index ab5de266577..03e1214c060 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -83,7 +83,6 @@ int litesom_mmc_init(struct bd_info *bis) #include <spl.h> #include <asm/arch/mx6-ddr.h> - static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { .grp_addds = 0x00000030, .grp_ddrmode_ctl = 0x00020000, diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index d4fb5389cac..59da7300dd6 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -428,7 +428,6 @@ static u32 scg_nic_get_rate(enum scg_clk clk) return rate; } - static enum scg_clk scg_scs_array[4] = { SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK, }; @@ -807,7 +806,6 @@ int scg_enable_usb_pll(bool usb_control) return 0; } - /* A7 domain system clock source is SPLL */ #define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT) diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index f164f95bf24..e5d70d2931e 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -26,7 +26,6 @@ #define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) #define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) - static inline u32 _boot_bit_mask(u32 x, u32 y) { u32 val = (1 << (x - y + 1)) - 1; diff --git a/arch/arm/mach-keystone/msmc.c b/arch/arm/mach-keystone/msmc.c index a20e0c98865..51c994f972f 100644 --- a/arch/arm/mach-keystone/msmc.c +++ b/arch/arm/mach-keystone/msmc.c @@ -53,7 +53,6 @@ struct msms_regs { struct mpax ses[16][8]; }; - void msmc_share_all_segments(int priv_id) { struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 7938820e513..3d224e20364 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -48,7 +48,6 @@ void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save) } debug("\n"); - while (*mpp_list) { unsigned int num = MPP_NUM(*mpp_list); unsigned int sel = MPP_SEL(*mpp_list); diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 9baeece3c85..c13416add1d 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -276,7 +276,6 @@ static int mvebu_mbus_alloc_window(phys_addr_t base, size_t size, target, attr); } - for (win = 0; win < MVEBU_MBUS_NUM_WINS; win++) if (mvebu_mbus_window_is_free(win)) return mvebu_mbus_setup_window(win, base, size, diff --git a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h index 9c3e7c08204..625c2a5dd71 100644 --- a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h +++ b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h @@ -76,7 +76,6 @@ #define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) - #define CORE_AVS_CONTROL_0REG 0x18300 #define CORE_AVS_CONTROL_2REG 0x18308 #define CPU_AVS_CONTROL2_REG 0x20868 @@ -86,7 +85,6 @@ #define MSAR_TCLK_OFFS 28 #define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS) - /* Controler environment registers offsets */ #define GEN_PURP_RES_1_REG 0x182F4 #define GEN_PURP_RES_2_REG 0x182F8 @@ -146,7 +144,6 @@ 0x40000 + ((port) % 2) * 0x4000) #define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port) - #define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04) #define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C) #define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18) @@ -182,7 +179,6 @@ #define SCR_PEX1_4BY1_OFFS 8 #define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS) - #define MV_MISC_REGS_OFFSET (0x18200) #define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET) #define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) @@ -226,7 +222,6 @@ #define PXCAR_REAL_EXT_REG_NUM_OFFS 8 #define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) - #define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60) #define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C) #define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70) diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h index b920f5ef090..a29d06cf3c2 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h @@ -21,7 +21,6 @@ typedef enum { SERDES_LAST_UNIT } MV_BIN_SERDES_UNIT_INDX; - typedef enum { PEX_BUS_DISABLED = 0, PEX_BUS_MODE_X1 = 1, @@ -63,7 +62,6 @@ typedef struct board_serdes_conf { MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change; } MV_BIN_SERDES_CFG; - #define BIN_SERDES_CFG { \ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \ {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \ diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c index 4765ce0adee..515b6f1b87c 100644 --- a/arch/arm/mach-omap2/am33xx/chilisom.c +++ b/arch/arm/mach-omap2/am33xx/chilisom.c @@ -102,7 +102,6 @@ void chilisom_spl_board_init(void) /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - if (i2c_probe(TPS65217_CHIP_PM)) return; diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c index f07003c95bc..cc955345db9 100644 --- a/arch/arm/mach-omap2/am33xx/clock.c +++ b/arch/arm/mach-omap2/am33xx/clock.c @@ -213,7 +213,6 @@ void do_disable_clocks(u32 *const *clk_domains, { u32 i, max = 100; - /* Clock modules that need to be put in SW_DISABLE */ for (i = 0; (i < max) && clk_modules_disable && clk_modules_disable[i]; i++) diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index 87afc096602..7ac67cb4899 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -74,7 +74,6 @@ u32 get_sys_clk_index(void) CTRL_SYSBOOT_15_14_SHIFT); } - #ifdef CONFIG_DISPLAY_CPUINFO static char *cpu_revs[] = { "1.0", diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 2a0c22841d0..18d099145c5 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -896,7 +896,6 @@ void do_disable_clocks(u32 const *clk_domains, { u32 i, max = 100; - /* Clock modules that need to be put in SW_DISABLE */ for (i = 0; (i < max) && clk_modules_disable[i]; i++) disable_clock_module(clk_modules_disable[i], diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 138501602c3..bb67e50fd56 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -268,7 +268,6 @@ void watchdog_init(void) writel(WD_UNLOCK2, &wd2_base->wspr); } - /* * This function finds the SDRAM size available in the system * based on DMM section configurations @@ -315,7 +314,6 @@ u32 omap_sdram_size(void) return total_size; } - /* * Routine: dram_init * Description: sets uboots idea of sdram size diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index c5ada607f97..1de343ff48e 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -405,7 +405,6 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); } - #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/arch/arm/mach-renesas/include/mach/rcar-base.h b/arch/arm/mach-renesas/include/mach/rcar-base.h index 4c2ee8187e0..a0f1c7762a0 100644 --- a/arch/arm/mach-renesas/include/mach/rcar-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-base.h @@ -328,7 +328,6 @@ #define MEDIA_AXI_VSP0W_BASE 0xFE966D00 #endif /* R8A7792 */ - #define SYS_AXI_AVBDMSCR 0xFF802000 #define SYS_AXI_SYX2DMSCR 0xFF802004 #define SYS_AXI_AX2MDMSCR 0xFF802004 diff --git a/arch/arm/mach-s5pc1xx/include/mach/cpu.h b/arch/arm/mach-s5pc1xx/include/mach/cpu.h index 78c905b866b..4b1b7118268 100644 --- a/arch/arm/mach-s5pc1xx/include/mach/cpu.h +++ b/arch/arm/mach-s5pc1xx/include/mach/cpu.h @@ -45,7 +45,6 @@ #define S5PC110_PHY_BASE 0xEC100000 #define S5PC110_USB_PHY_CONTROL 0xE010E80C - #ifndef __ASSEMBLY__ #include <asm/io.h> /* CPU detection macros */ diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 154ad2154ae..0a2c84c9e13 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -125,7 +125,6 @@ int cm_basic_init(const struct cm_config * const cfg) readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); - /* * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 7c86350d5ea..c8530c98043 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 Altera Corporation <www.altera.com> */ - #include <config.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index 7f10296dc74..18921169a6d 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -106,7 +106,6 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_INTER CLKMGR_S10_INTER #define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN - #define CLKMGR_CTRL_SAFEMODE BIT(0) #define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007 #define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index ad1ef0db186..a6cc78454da 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -39,7 +39,6 @@ static Altera_desc altera_fpga[] = { }, }; - /* * Print CPU information */ diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 9395122dae1..6a202bf227c 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 Altera Corporation <www.altera.com> */ - #include <mach/base_addr_ac5.h> #include <asm/io.h> #include <asm/arch/fpga_manager.h> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 967fa4e06c0..04640e476e6 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -187,7 +187,6 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog, " <size> = size of flashlayout (optional for image with STM32 header)\n" ); - bool stm32prog_get_fsbl_nor(void) { if (stm32prog_data) diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 9eeba084f95..c00d16a918d 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -118,7 +118,6 @@ void clock_set_pll5(unsigned int clk) udelay(5500); } - unsigned int clock_get_pll6(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index 5913e40cb65..abdab405445 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -14,7 +14,6 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h> - #ifdef CONFIG_SPL_BUILD static void clock_set_pll2(unsigned int clk) @@ -166,7 +165,6 @@ void clock_set_pll6(unsigned int clk) sdelay(2000); } - int clock_twi_onoff(int port, int state) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/mach-sunxi/dram_sun8i_a83t.c b/arch/arm/mach-sunxi/dram_sun8i_a83t.c index ef833321e37..dd0fc37b763 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a83t.c @@ -284,7 +284,6 @@ static int mctl_channel_init(struct dram_para *para) writel(0x0, MCTL_PROTECT); udelay(100); - /* Set ODT */ if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) rval = 0x0; diff --git a/arch/arm/mach-sunxi/dram_sun9i.c b/arch/arm/mach-sunxi/dram_sun9i.c index 002b6df39d5..58ecbb98356 100644 --- a/arch/arm/mach-sunxi/dram_sun9i.c +++ b/arch/arm/mach-sunxi/dram_sun9i.c @@ -262,7 +262,6 @@ static void mctl_sys_init(void) reg_val |= ((0x1<<24)|(0x1<<30)); mctl_write_w(CCM_PLL6_DDR_REG, reg_val); - while(mctl_read_w(CCM_PLL6_DDR_REG) & (0x1<<30)); } diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index e064ef329e6..4ed295909ce 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -650,7 +650,6 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) return 0; } - static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank) { /* detect row address bits */ |