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-rw-r--r--arch/arm/mach-kirkwood/include/mach/kw88f6281.h2
-rw-r--r--arch/arm/mach-meson/board-common.c34
-rw-r--r--arch/arm/mach-mvebu/include/mach/soc.h15
-rw-r--r--arch/arm/mach-mvebu/spl.c6
4 files changed, 15 insertions, 42 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
index 33e74142078..87406081cf5 100644
--- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h
@@ -15,8 +15,6 @@
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
/* TCLK Core Clock definition */
-#ifndef CONFIG_SYS_TCLK
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
-#endif
#endif /* _ASM_ARCH_KW88F6281_H */
diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
index 1690b6b1e65..7ceba7cede8 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -22,10 +22,7 @@
#include <efi_loader.h>
#include <u-boot/crc.h>
-#if CONFIG_IS_ENABLED(FASTBOOT)
#include <asm/psci.h>
-#include <fastboot.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -152,38 +149,7 @@ int board_late_init(void)
return meson_board_late_init();
}
-#if CONFIG_IS_ENABLED(FASTBOOT)
-static unsigned int reboot_reason = REBOOT_REASON_NORMAL;
-
-int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
-{
- if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
- return -ENOTSUPP;
-
- reboot_reason = REBOOT_REASON_BOOTLOADER;
-
- printf("Using reboot reason: 0x%x\n", reboot_reason);
-
- return 0;
-}
-
-void reset_cpu(void)
-{
- struct pt_regs regs;
-
- regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
- regs.regs[1] = reboot_reason;
-
- printf("Rebooting with reason: 0x%lx\n", regs.regs[1]);
-
- smc_call(&regs);
-
- while (1)
- ;
-}
-#else
void reset_cpu(void)
{
psci_system_reset();
}
-#endif
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 3f3b15aa8ab..8e8a4058550 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -33,11 +33,6 @@
#define MV_88F68XX_A0_ID 0x4
#define MV_88F68XX_B0_ID 0xa
-/* TCLK Core Clock definition */
-#ifndef CONFIG_SYS_TCLK
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-#endif
-
/* SOC specific definations */
#define INTREG_BASE 0xd0000000
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
@@ -150,6 +145,9 @@
#define BOOT_FROM_UART 0x30
#define BOOT_FROM_SPI 0x38
+
+#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
+ 200000000 : 166000000)
#elif defined(CONFIG_ARMADA_38X)
/* SAR values for Armada 38x */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
@@ -170,6 +168,9 @@
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
+
+#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
+ 200000000 : 250000000)
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
@@ -186,6 +187,8 @@
#define BOOT_FROM_NAND 0x1
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
+
+#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
#else
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
@@ -205,6 +208,8 @@
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
+
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#endif
#endif /* _MVEBU_SOC_H */
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 3b6bc389709..f0cf60bb148 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -345,7 +345,11 @@ void board_init_f(ulong dummy)
serdes_phy_config();
/* Setup DDR */
- ddr3_init();
+ ret = ddr3_init();
+ if (ret) {
+ debug("ddr3_init() failed: %d\n", ret);
+ hang();
+ }
#endif
/* Initialize Auto Voltage Scaling */