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-rw-r--r--arch/arm/dts/rk3288-u-boot.dtsi24
-rw-r--r--arch/arm/dts/rk3288-veyron-u-boot.dtsi8
-rw-r--r--arch/arm/dts/rk3399-gru-u-boot.dtsi4
-rw-r--r--arch/arm/dts/rk3399-u-boot.dtsi35
-rw-r--r--arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi11
-rw-r--r--arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi20
-rw-r--r--arch/arm/dts/rockchip-u-boot.dtsi291
-rw-r--r--arch/arm/include/asm/arch-rockchip/grf_rk3288.h16
-rw-r--r--arch/arm/mach-rockchip/rk3288/Kconfig5
-rw-r--r--arch/arm/mach-rockchip/rk3399/Kconfig2
10 files changed, 206 insertions, 210 deletions
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index 2205caabc51..bb0078588fe 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -46,30 +46,6 @@
};
};
-#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
-&binman {
- rom {
- filename = "u-boot.rom";
- size = <0x400000>;
- pad-byte = <0xff>;
-
- mkimage {
- args = "-n rk3288 -T rkspi";
- u-boot-spl {
- };
- };
- u-boot-img {
- offset = <0x20000>;
- };
- u-boot {
- offset = <0x300000>;
- };
- fdtmap {
- };
- };
-};
-#endif
-
&bus_intmem {
ddr_sram: ddr-sram@1000 {
compatible = "rockchip,rk3288-ddr-sram";
diff --git a/arch/arm/dts/rk3288-veyron-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
index 4f9c59c6757..89093e2311c 100644
--- a/arch/arm/dts/rk3288-veyron-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-veyron-u-boot.dtsi
@@ -11,6 +11,14 @@
};
};
+#if defined(CONFIG_ROCKCHIP_SPI_IMAGE)
+&binman {
+ simple-bin-spi {
+ size = <0x400000>;
+ };
+};
+#endif
+
&dmc {
logic-supply = <&vdd_logic>;
rockchip,odt-disable-freq = <333000000>;
diff --git a/arch/arm/dts/rk3399-gru-u-boot.dtsi b/arch/arm/dts/rk3399-gru-u-boot.dtsi
index 5517176aa4a..dfc7be4c621 100644
--- a/arch/arm/dts/rk3399-gru-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-gru-u-boot.dtsi
@@ -15,11 +15,13 @@
};
};
+#if defined(CONFIG_ROCKCHIP_SPI_IMAGE)
&binman {
- rom {
+ simple-bin-spi {
size = <0x800000>;
};
};
+#endif
&cros_ec {
ec-interrupt = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 70f35b6c197..587eef9504e 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -29,41 +29,6 @@
};
};
-#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
-&binman {
- multiple-images;
- rom {
- filename = "u-boot.rom";
- size = <0x400000>;
- pad-byte = <0xff>;
-
- mkimage {
- args = "-n rk3399 -T rkspi";
- multiple-data-files;
-#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
- rockchip-tpl {
- };
-#elif defined(CONFIG_TPL)
- u-boot-tpl {
- };
-#endif
- u-boot-spl {
- };
- };
- fit {
- type = "blob";
- filename = "u-boot.itb";
- offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
- };
- u-boot {
- offset = <0x300000>;
- };
- fdtmap {
- };
- };
-};
-#endif /* CONFIG_ROCKCHIP_SPI_IMAGE && CONFIG_HAS_ROM */
-
&cru {
bootph-all;
};
diff --git a/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi b/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi
new file mode 100644
index 00000000000..0c8e7018f13
--- /dev/null
+++ b/arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+&rgb_led_r {
+ default-state = "off";
+};
+
+&rgb_led_b {
+ default-state = "off";
+};
diff --git a/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi
new file mode 100644
index 00000000000..afd33dd3248
--- /dev/null
+++ b/arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+&fspim2_pins {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+&sfc {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index c8c928c7e50..cc2feed6464 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -5,6 +5,36 @@
#include <config.h>
+#ifdef CONFIG_ARM64
+#define FIT_ARCH "arm64"
+#else
+#define FIT_ARCH "arm"
+#endif
+
+#if defined(CONFIG_SPL_GZIP)
+#define FIT_UBOOT_COMP "gzip"
+#elif defined(CONFIG_SPL_LZMA)
+#define FIT_UBOOT_COMP "lzma"
+#else
+#define FIT_UBOOT_COMP "none"
+#endif
+
+/*
+ * SHA256 should be enabled in SPL when signature validation is involved,
+ * CRC32 should only be used for basic checksum validation of FIT images.
+ */
+#if defined(CONFIG_SPL_FIT_SIGNATURE)
+#if defined(CONFIG_SPL_SHA256)
+#define FIT_HASH_ALGO "sha256"
+#elif defined(CONFIG_SPL_CRC32)
+#define FIT_HASH_ALGO "crc32"
+#endif
+#endif
+
+#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
+#define HAS_FIT
+#endif
+
/ {
binman: binman {
multiple-images;
@@ -13,6 +43,126 @@
#ifdef CONFIG_SPL
&binman {
+#ifdef HAS_FIT
+ fit_template: template-1 {
+ type = "fit";
+#ifdef CONFIG_ARM64
+ description = "FIT image for U-Boot with bl31 (TF-A)";
+#else
+ description = "FIT image with OP-TEE";
+#endif
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,align = <512>;
+ images {
+ u-boot {
+ description = "U-Boot";
+ type = "standalone";
+ os = "u-boot";
+ arch = FIT_ARCH;
+ compression = FIT_UBOOT_COMP;
+ load = <CONFIG_TEXT_BASE>;
+ entry = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
+ compress = FIT_UBOOT_COMP;
+ };
+#ifdef FIT_HASH_ALGO
+ hash {
+ algo = FIT_HASH_ALGO;
+ };
+#endif
+ };
+
+#ifdef CONFIG_ARM64
+ @atf-SEQ {
+ fit,operation = "split-elf";
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = FIT_ARCH;
+ os = "arm-trusted-firmware";
+ compression = "none";
+ fit,load;
+ fit,entry;
+ fit,data;
+
+ atf-bl31 {
+ };
+#ifdef FIT_HASH_ALGO
+ hash {
+ algo = FIT_HASH_ALGO;
+ };
+#endif
+ };
+ @tee-SEQ {
+ fit,operation = "split-elf";
+ description = "TEE";
+ type = "tee";
+ arch = FIT_ARCH;
+ os = "tee";
+ compression = "none";
+ fit,load;
+ fit,entry;
+ fit,data;
+
+ tee-os {
+ optional;
+ };
+#ifdef FIT_HASH_ALGO
+ hash {
+ algo = FIT_HASH_ALGO;
+ };
+#endif
+ };
+#else /* !CONFIG_ARM64 */
+ op-tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = FIT_ARCH;
+ os = "tee";
+ compression = "none";
+ load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+ entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+
+ tee-os {
+ };
+#ifdef FIT_HASH_ALGO
+ hash {
+ algo = FIT_HASH_ALGO;
+ };
+#endif
+ };
+#endif /* CONFIG_ARM64 */
+
+ @fdt-SEQ {
+ description = "fdt-NAME";
+ compression = "none";
+ type = "flat_dt";
+#ifdef FIT_HASH_ALGO
+ hash {
+ algo = FIT_HASH_ALGO;
+ };
+#endif
+ };
+ };
+
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+ @config-SEQ {
+ description = "NAME.dtb";
+ fdt = "fdt-SEQ";
+#ifdef CONFIG_ARM64
+ fit,firmware = "atf-1", "u-boot";
+#else
+ fit,firmware = "op-tee", "u-boot";
+#endif
+ fit,loadables;
+ fit,compatible;
+ };
+ };
+ };
+#endif /* HAS_FIT */
+
simple-bin {
filename = "u-boot-rockchip.bin";
pad-byte = <0xff>;
@@ -33,143 +183,15 @@
};
};
-#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
- fit: fit {
-#ifdef CONFIG_ARM64
- description = "FIT image for U-Boot with bl31 (TF-A)";
-#else
- description = "FIT image with OP-TEE";
-#endif
- #address-cells = <1>;
- fit,fdt-list = "of-list";
+#ifdef HAS_FIT
+ fit {
filename = "u-boot.itb";
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
- fit,align = <512>;
- offset = <CONFIG_SPL_PAD_TO>;
- images {
- u-boot {
- description = "U-Boot";
- type = "standalone";
- os = "U-Boot";
-#ifdef CONFIG_ARM64
- arch = "arm64";
-#else
- arch = "arm";
-#endif
-#if defined(CONFIG_SPL_GZIP)
- compression = "gzip";
-#elif defined(CONFIG_SPL_LZMA)
- compression = "lzma";
-#else
- compression = "none";
-#endif
- load = <CONFIG_TEXT_BASE>;
- entry = <CONFIG_TEXT_BASE>;
- u-boot-nodtb {
-#if defined(CONFIG_SPL_GZIP)
- compress = "gzip";
-#elif defined(CONFIG_SPL_LZMA)
- compress = "lzma";
-#endif
- };
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
- };
-
-#ifdef CONFIG_ARM64
- @atf-SEQ {
- fit,operation = "split-elf";
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- os = "arm-trusted-firmware";
- compression = "none";
- fit,load;
- fit,entry;
- fit,data;
-
- atf-bl31 {
- };
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
- };
- @tee-SEQ {
- fit,operation = "split-elf";
- description = "TEE";
- type = "tee";
- arch = "arm64";
- os = "tee";
- compression = "none";
- fit,load;
- fit,entry;
- fit,data;
-
- tee-os {
- optional;
- };
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
- };
-#else
- op-tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm";
- os = "tee";
- compression = "none";
- load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
- entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
-
- tee-os {
- };
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
- };
-#endif
-
- @fdt-SEQ {
- description = "fdt-NAME";
- compression = "none";
- type = "flat_dt";
-#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
- };
- };
-
- configurations {
- default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- description = "NAME.dtb";
- fdt = "fdt-SEQ";
-#ifdef CONFIG_ARM64
- fit,firmware = "atf-1", "u-boot";
-#else
- fit,firmware = "op-tee", "u-boot";
-#endif
- fit,loadables;
- };
- };
- };
+ insert-template = <&fit_template>;
#else
u-boot-img {
+#endif
offset = <CONFIG_SPL_PAD_TO>;
};
-#endif
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
@@ -193,10 +215,9 @@
};
};
-#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)
+#ifdef HAS_FIT
fit {
- type = "blob";
- filename = "u-boot.itb";
+ insert-template = <&fit_template>;
#else
u-boot-img {
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 894d3a40b09..0111b3a0ded 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -934,21 +934,21 @@ enum {
RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT),
RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT),
- GMAC_SPEED_SHIFT = 0xa,
- GMAC_SPEED_MASK = 1,
- GMAC_SPEED_10M = 0,
- GMAC_SPEED_100M,
+ RK3288_GMAC_SPEED_SHIFT = 0xa,
+ RK3288_GMAC_SPEED_MASK = (1 << RK3288_GMAC_SPEED_SHIFT),
+ RK3288_GMAC_SPEED_10M = (0 << RK3288_GMAC_SPEED_SHIFT),
+ RK3288_GMAC_SPEED_100M = (1 << RK3288_GMAC_SPEED_SHIFT),
- GMAC_FLOWCTRL_SHIFT = 0x9,
- GMAC_FLOWCTRL_MASK = 1,
+ RK3288_GMAC_FLOWCTRL_SHIFT = 0x9,
+ RK3288_GMAC_FLOWCTRL_MASK = (1 << RK3288_GMAC_FLOWCTRL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
- HOST_REMAP_SHIFT = 0x5,
- HOST_REMAP_MASK = 1
+ RK3288_HOST_REMAP_SHIFT = 0x5,
+ RK3288_HOST_REMAP_MASK = (1 << RK3288_HOST_REMAP_SHIFT),
};
/* GRF_SOC_CON2 */
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index e563bf455e6..128ee362f8a 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -5,7 +5,6 @@ choice
config TARGET_CHROMEBOOK_JERRY
bool "Google/Rockchip Veyron-Jerry Chromebook"
- select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_JERRY
config TARGET_CHROMEBIT_MICKEY
bool "Google/Rockchip Veyron-Mickey Chromebit"
- select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -28,7 +26,6 @@ config TARGET_CHROMEBIT_MICKEY
config TARGET_CHROMEBOOK_MINNIE
bool "Google/Rockchip Veyron-Minnie Chromebook"
- select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -41,7 +38,6 @@ config TARGET_CHROMEBOOK_MINNIE
config TARGET_CHROMEBOOK_SPEEDY
bool "Google/Rockchip Veyron-Speedy Chromebook"
- select HAS_ROM
select BOARD_LATE_INIT
select ROCKCHIP_SPI_IMAGE
help
@@ -54,7 +50,6 @@ config TARGET_CHROMEBOOK_SPEEDY
config TARGET_EVB_RK3288
bool "Evb-RK3288"
- select HAS_ROM
select BOARD_LATE_INIT
select TPL
help
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index b2430207ee9..5c21b08a5ae 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -5,7 +5,6 @@ choice
config TARGET_CHROMEBOOK_BOB
bool "Asus Flip C101PA Chromebook (RK3399)"
- select HAS_ROM
select ROCKCHIP_SPI_IMAGE
help
Bob is a small RK3299-based device similar in apperance to Minnie.
@@ -16,7 +15,6 @@ config TARGET_CHROMEBOOK_BOB
config TARGET_CHROMEBOOK_KEVIN
bool "Samsung Chromebook Plus (RK3399)"
- select HAS_ROM
select ROCKCHIP_SPI_IMAGE
help
Kevin is a RK3399-based convertible chromebook. It has two USB 3.0
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-03 20:02:44 +0000