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-rw-r--r--arch/arm/dts/px30-u-boot.dtsi4
-rw-r--r--arch/arm/dts/rk3328-roc-cc-u-boot.dtsi2
-rw-r--r--arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi226
-rw-r--r--arch/arm/dts/rk3528-generic-u-boot.dtsi9
-rw-r--r--arch/arm/dts/rk3528-generic.dts17
-rw-r--r--arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi13
-rw-r--r--arch/arm/dts/rk3528-u-boot.dtsi18
-rw-r--r--arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi18
-rw-r--r--arch/arm/dts/rk3576-generic-u-boot.dtsi3
-rw-r--r--arch/arm/dts/rk3576-generic.dts63
-rw-r--r--arch/arm/dts/rk3576-u-boot.dtsi4
-rw-r--r--arch/arm/dts/rk3588-generic-u-boot.dtsi18
-rw-r--r--arch/arm/dts/rk3588-generic.dts16
-rw-r--r--arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi20
-rw-r--r--arch/arm/mach-rockchip/px30/px30.c61
-rw-r--r--arch/arm/mach-rockchip/rk3528/rk3528.c6
-rw-r--r--arch/arm/mach-rockchip/rk3576/MAINTAINERS11
-rw-r--r--arch/arm/mach-rockchip/rk3576/rk3576.c54
-rw-r--r--arch/arm/mach-rockchip/rk3588/Kconfig18
-rw-r--r--arch/arm/mach-rockchip/rk3588/rk3588.c8
20 files changed, 535 insertions, 54 deletions
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index 157d0ea6930..2f726b0aaba 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -27,6 +27,10 @@
};
};
+&otp {
+ bootph-some-ram;
+};
+
&uart2 {
clock-frequency = <24000000>;
bootph-all;
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 582d6ba49b4..c47d29c59de 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -4,7 +4,7 @@
*/
#include "rk3328-u-boot.dtsi"
-#include "rk3328-sdram-ddr4-666.dtsi"
+#include "rk3328-sdram-ddr4-1600.dtsi"
/ {
smbios {
diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
new file mode 100644
index 00000000000..9594bb42839
--- /dev/null
+++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+
+&dmc {
+ rockchip,sdram-params = <
+ 0x1
+ 0xA
+ 0x2
+ 0x1
+ 0x0
+ 0x0
+ 0x11
+ 0x0
+ 0x11
+ 0x0
+ 0
+
+ 0x94496354
+ 0x00000000
+ 0x0000002a
+ 0x000004e2
+ 0x00000015
+ 0x0000034a
+ 0x000000ff
+
+ 800
+ 0
+ 1
+ 0
+ 0
+
+ 0x00000000
+ 0x43041010
+ 0x00000064
+ 0x0061008c
+ 0x000000d0
+ 0x000200c5
+ 0x000000d4
+ 0x00500000
+ 0x000000d8
+ 0x00000100
+ 0x000000dc
+ 0x03140401
+ 0x000000e0
+ 0x00000000
+ 0x000000e4
+ 0x00110000
+ 0x000000e8
+ 0x00000420
+ 0x000000ec
+ 0x00000400
+ 0x000000f4
+ 0x000f011f
+ 0x00000100
+ 0x0c0e1b0e
+ 0x00000104
+ 0x00030314
+ 0x00000108
+ 0x0506050b
+ 0x0000010c
+ 0x0040400c
+ 0x00000110
+ 0x06030307
+ 0x00000114
+ 0x04040302
+ 0x00000120
+ 0x06060b06
+ 0x00000124
+ 0x00020308
+ 0x00000180
+ 0x01000040
+ 0x00000184
+ 0x00000000
+ 0x00000190
+ 0x07040003
+ 0x00000198
+ 0x05001100
+ 0x000001a0
+ 0xc0400003
+ 0x00000240
+ 0x0600060c
+ 0x00000244
+ 0x00000201
+ 0x00000250
+ 0x00000f00
+ 0x00000490
+ 0x00000001
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+ 0xffffffff
+
+ 0x00000004
+ 0x0000000c
+ 0x00000028
+ 0x0000000c
+ 0x0000002c
+ 0x00000000
+ 0x00000030
+ 0x00000009
+ 0xffffffff
+ 0xffffffff
+
+ 0x77
+ 0x88
+ 0x79
+ 0x79
+ 0x87
+ 0x97
+ 0x87
+ 0x78
+ 0x77
+ 0x78
+ 0x87
+ 0x88
+ 0x87
+ 0x87
+ 0x77
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x78
+ 0x77
+ 0x79
+ 0x9
+
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x78
+ 0x69
+ 0x9
+
+ 0x77
+ 0x78
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x77
+ 0x79
+ 0x9
+ >;
+};
diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi
index cc830b51456..9e1fb2a7eef 100644
--- a/arch/arm/dts/rk3528-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi
@@ -1,12 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3528-u-boot.dtsi"
-
-&sdmmc {
- bus-width = <4>;
- cap-sd-highspeed;
- disable-wp;
- no-mmc;
- no-sdio;
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
index 3f6f0bed108..637ca03325e 100644
--- a/arch/arm/dts/rk3528-generic.dts
+++ b/arch/arm/dts/rk3528-generic.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Minimal generic DT for RK3528 with eMMC enabled
+ * Minimal generic DT for RK3528 with eMMC and SD-card enabled
*/
/dts-v1/;
@@ -10,6 +10,12 @@
model = "Generic RK3528";
compatible = "rockchip,rk3528";
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial0 = &uart0;
+ };
+
chosen {
stdout-path = "serial0:1500000n8";
};
@@ -25,6 +31,15 @@
status = "okay";
};
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
index 1372d8f1e38..16c47e6b9a9 100644
--- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -6,11 +6,10 @@
mmc-hs200-1_8v;
};
-&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- vmmc-supply = <&vcc_3v3>;
- status = "okay";
+&vdd_arm {
+ regulator-init-microvolt = <953000>;
+};
+
+&vdd_logic {
+ regulator-init-microvolt = <900000>;
};
diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi
index eb6a55cd5c9..a18d33b3d36 100644
--- a/arch/arm/dts/rk3528-u-boot.dtsi
+++ b/arch/arm/dts/rk3528-u-boot.dtsi
@@ -27,24 +27,6 @@
compatible = "rockchip,rk3528-otp";
reg = <0x0 0xffce0000 0x0 0x4000>;
};
-
- sdmmc: mmc@ffc30000 {
- compatible = "rockchip,rk3528-dw-mshc",
- "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xffc30000 0x0 0x4000>;
- clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- max-frequency = <150000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
- <&sdmmc_det>;
- resets = <&cru SRST_H_SDMMC0>;
- reset-names = "reset";
- rockchip,default-sample-phase = <90>;
- status = "disabled";
- };
};
};
diff --git a/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi
new file mode 100644
index 00000000000..7e0530d85d1
--- /dev/null
+++ b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+};
+
+&red_led {
+ default-state = "on";
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+};
diff --git a/arch/arm/dts/rk3576-generic-u-boot.dtsi b/arch/arm/dts/rk3576-generic-u-boot.dtsi
new file mode 100644
index 00000000000..632fabb6af5
--- /dev/null
+++ b/arch/arm/dts/rk3576-generic-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3576-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3576-generic.dts b/arch/arm/dts/rk3576-generic.dts
new file mode 100644
index 00000000000..123be5378d9
--- /dev/null
+++ b/arch/arm/dts/rk3576-generic.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "rk3576.dtsi"
+
+/ {
+ model = "Generic RK3576";
+ compatible = "rockchip,rk3576";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
+
+&usb_drd0_dwc3 {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
index be99a48a630..fb5a107f47d 100644
--- a/arch/arm/dts/rk3576-u-boot.dtsi
+++ b/arch/arm/dts/rk3576-u-boot.dtsi
@@ -49,6 +49,10 @@
bootph-all;
};
+&otp {
+ bootph-some-ram;
+};
+
&pcfg_pull_none {
bootph-all;
};
diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi
index f67301d87a6..853ed58cfe5 100644
--- a/arch/arm/dts/rk3588-generic-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi
@@ -1,21 +1,3 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3588s-u-boot.dtsi"
-
-&u2phy0 {
- status = "okay";
-};
-
-&u2phy0_otg {
- status = "okay";
-};
-
-&usbdp_phy0 {
- status = "okay";
-};
-
-&usb_host0_xhci {
- dr_mode = "peripheral";
- maximum-speed = "high-speed";
- status = "okay";
-};
diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts
index 95d757676f1..6740f9866f1 100644
--- a/arch/arm/dts/rk3588-generic.dts
+++ b/arch/arm/dts/rk3588-generic.dts
@@ -39,7 +39,23 @@
status = "okay";
};
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi
new file mode 100644
index 00000000000..1ab31a4ec5a
--- /dev/null
+++ b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+&fspim1_pins {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+&sfc {
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index 8ce9ac561f0..5a5c119328f 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -2,10 +2,14 @@
/*
* Copyright (c) 2017 Rockchip Electronics Co., Ltd
*/
+
+#define LOG_CATEGORY LOGC_ARCH
+
#include <clk.h>
#include <dm.h>
#include <fdt_support.h>
#include <init.h>
+#include <misc.h>
#include <spl.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
@@ -15,6 +19,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_px30.h>
#include <dt-bindings/clock/px30-cru.h>
+#include <linux/bitfield.h>
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000",
@@ -442,3 +447,59 @@ void board_debug_uart_init(void)
#endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */
}
#endif /* CONFIG_DEBUG_UART_BOARD_INIT */
+
+#define PX30_OTP_SPECIFICATION_OFFSET 0x06
+
+#define DDR_GRF_BASE_ADDR 0xff630000
+#define DDR_GRF_CON(n) (0 + (n) * 4)
+
+int checkboard(void)
+{
+ struct udevice *dev;
+ u8 specification;
+ u32 base_soc;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+ if (ret) {
+ log_debug("Could not find otp device, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */
+ ret = misc_read(dev, 0, &base_soc, 4);
+ if (ret < 0) {
+ log_debug("Could not read specification, ret=%d\n", ret);
+ return 0;
+ }
+
+ if (base_soc != 0x26334b52 && base_soc != 0x30335850) {
+ log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc);
+ return 0;
+ }
+
+ /* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */
+ ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1);
+ if (ret < 0) {
+ log_debug("Could not read specification, ret=%d\n", ret);
+ return 0;
+ }
+
+ if (specification == 0x2b) {
+ printf("SoC: PX30K\n");
+ return 0;
+ }
+
+ /* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */
+ specification = FIELD_GET(GENMASK(15, 14),
+ readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1)));
+ log_debug("DDR specification is %d\n", specification);
+ printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30",
+ specification == 0x3 ? "S" : "");
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c
index 4892ff6ba9d..f9bfc445b85 100644
--- a/arch/arm/mach-rockchip/rk3528/rk3528.c
+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -9,6 +9,9 @@
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
+#define VPU_GRF_BASE 0xff340000
+#define USB3OTG_CON1 0x44
+
#define FIREWALL_DDR_BASE 0xff2e0000
#define FW_DDR_MST6_REG 0x58
#define FW_DDR_MST7_REG 0x5c
@@ -69,6 +72,9 @@ int arch_cpu_init(void)
val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+ /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */
+ writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1);
+
return 0;
}
diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
new file mode 100644
index 00000000000..94ef74d429f
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS
@@ -0,0 +1,11 @@
+GENERIC-RK3576
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3576-generic*
+F: configs/generic-rk3576_defconfig
+
+SIGE5-RK3576
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3576-armsom-sige5*
+F: configs/sige5-rk3576_defconfig
diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
index ba5c94b4b3d..a6c2fbdc484 100644
--- a/arch/arm/mach-rockchip/rk3576/rk3576.c
+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
@@ -3,6 +3,10 @@
* Copyright (c) 2024 Rockchip Electronics Co., Ltd
*/
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <dm.h>
+#include <misc.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
@@ -29,6 +33,9 @@
#define SGRF_DOMAIN_CON4 0x10
#define SGRF_DOMAIN_CON5 0x14
+#define USB_GRF_BASE 0x2601E000
+#define USB3OTG0_CON1 0x0030
+
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
@@ -151,5 +158,52 @@ int arch_cpu_init(void)
*/
writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
+ /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
+ writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+
+ return 0;
+}
+
+#define RK3576_OTP_CPU_CODE_OFFSET 0x02
+#define RK3576_OTP_SPECIFICATION_OFFSET 0x08
+
+int checkboard(void)
+{
+ u8 cpu_code[2], specification;
+ struct udevice *dev;
+ char suffix[2];
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+ if (ret) {
+ log_debug("Could not find otp device, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* cpu-code: SoC model, e.g. 0x35 0x76 */
+ ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2);
+ if (ret < 0) {
+ log_debug("Could not read cpu-code, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* specification: SoC variant, e.g. 0xA for RK3576J */
+ ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1);
+ if (ret < 0) {
+ log_debug("Could not read specification, ret=%d\n", ret);
+ return 0;
+ }
+ specification &= 0x1f;
+
+ /* for RK3576J i.e. '@' + 0xA = 'J' */
+ suffix[0] = specification > 1 ? '@' + specification : '\0';
+ suffix[1] = '\0';
+
+ printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
+
return 0;
}
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 4e7942ada87..9fbe3f225aa 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588
- 3.5mm Headphone out, 2.0mm PH-2A Mic in
- 5V Fan connector, PWM beeper, IR receiver, RTC battery connector
+config TARGET_GAMEFORCE_ACE_RK3588S
+ bool "GameForce Ace"
+ help
+ The GameForce Ace is a handheld game console from GameForce with
+ the Rockchip RK3588S SoC.
+
+ Hardware features:
+ - Rockchip RK3588S SoC
+ - 12GB LPDDR4x RAM
+ - 128GB eMMC
+ - MicroSD card slot
+ - 1x USB 3.0 Type-C with DP AltMode support
+ - 1x HDMI 2.1 micro-HDMI out
+ - 1920x1080 touchscreen MIPI-DSI panel
+ - Analog joysticks and L/R triggers
+ - 16 digital buttons
+
config TARGET_GENBOOK_CM5_RK3588
bool "Cool Pi CM5 GenBook"
help
@@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig"
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig"
source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
+source "board/gameforce/ace-rk3588s/Kconfig"
source "board/hardkernel/odroid_m2/Kconfig"
source "board/indiedroid/nova/Kconfig"
source "board/khadas/khadas-edge2-rk3588s/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index e2278ff792b..c01a4002089 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -15,6 +15,10 @@
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/ioc_rk3588.h>
+#define USB_GRF_BASE 0xfd5ac000
+#define USB3OTG0_CON1 0x001c
+#define USB3OTG1_CON1 0x0034
+
#define FIREWALL_DDR_BASE 0xfe030000
#define FW_DDR_MST5_REG 0x54
#define FW_DDR_MST13_REG 0x74
@@ -184,6 +188,10 @@ int arch_cpu_init(void)
/* Disable JTAG exposed on SDMMC */
rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
#endif
+
+ /* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */
+ writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+ writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1);
#endif
return 0;
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-28 18:43:45 +0000