diff options
Diffstat (limited to 'arch/arm')
231 files changed, 618 insertions, 4184 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index dbeedbe544b..cb87a684754 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) CONFIG_CPU_V7A= CONFIG_CPU_ARM720T=y endif @@ -24,7 +24,7 @@ endif # On Tegra systems we must build SPL for the armv4 core on the device # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) arch-y += -D__LINUX_ARM_ARCH__=4 else arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) @@ -106,7 +106,7 @@ libs-y += $(machdirs) head-y := arch/arm/cpu/$(CPU)/start.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs") head-y := arch/arm/cpu/arm926ejs/mxs/start.o endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 5530d02b66c..e0045e22271 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -40,7 +40,7 @@ PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm endif # Choose between ARM/Thumb instruction sets -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \ $(call cc-option, -mthumb -mthumb-interwork,\ @@ -53,7 +53,7 @@ PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \ endif # Only test once -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) archprepare: checkthumb checkgcc6 checkthumb: @@ -99,7 +99,7 @@ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI) ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) # This file is parsed many times, so the string may get added multiple # times. Also, the prefix needs to be different based on whether -# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry +# CONFIG_XPL_BUILD is defined or not. 'filter-out' the existing entry # before adding the correct one. PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \ $(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) @@ -116,7 +116,7 @@ LDFLAGS_u-boot += -pie # # http://sourceware.org/bugzilla/show_bug.cgi?id=12532 # -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) ifeq ($(GAS_BUG_12532),) export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \ then echo y; else echo n; fi) @@ -126,7 +126,7 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls endif endif -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) # Check that only R_ARM_RELATIVE relocations are generated. INPUTS-y += checkarmreloc # The movt / movw can hardcode 16 bit parts of the addresses in the @@ -160,7 +160,7 @@ endif ifdef CONFIG_MACH_IMX ifneq ($(CONFIG_IMX_CONFIG),"") ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-y += SPL endif else diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile index 5dfa01ae8d0..38a3e4d95e2 100644 --- a/arch/arm/cpu/arm11/Makefile +++ b/arch/arm/cpu/arm11/Makefile @@ -5,6 +5,6 @@ obj-y = cpu.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_EFI_LOADER) += sctlr.o endif diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 78a9cc173a3..d3ab5928eee 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -65,7 +65,7 @@ cpu_init_crit: * When booting from NAND - it has definitely been a reset, so, no need * to flush caches and disable the MMU */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * flush v4 I/D caches */ diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 5ac3740621c..06456fe5a81 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -9,6 +9,6 @@ obj-y += cpu.o # some files can only build in ARM mode -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD CFLAGS_cpu.o := -marm endif diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 8cfe3f0fbbc..750cb94dc6e 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -6,7 +6,7 @@ extra-y = start.o obj-y = cpu.o cache.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_NO_CPU_SUPPORT extra-y := endif @@ -17,7 +17,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 1638ef8fd8d..f633e54ba62 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -3,11 +3,11 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -extra-$(CONFIG_SPL_BUILD) := start.o +extra-$(CONFIG_XPL_BUILD) := start.o obj-y = clock.o mxs.o iomux.o timer.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk index 76ffec9df6a..50899d20316 100644 --- a/arch/arm/cpu/arm926ejs/sunxi/config.mk +++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk @@ -1,6 +1,6 @@ # Build a combined spl + u-boot image ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ALL-y += u-boot-sunxi-with-spl.bin endif endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 99cf9eb515f..6461f5f5bde 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,12 +12,12 @@ obj-y += syslib.o obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_EFI_LOADER) += sctlr.o obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o endif -ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y) +ifneq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index aa981faef00..8082f369ed6 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -32,7 +32,7 @@ int cleanup_before_linux_select(int flags) * * we turn off caches etc ... */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD disable_interrupts(); #endif diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 3c8c07fe016..a6c844b7e3d 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -26,7 +26,7 @@ WEAK(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr sp, =CONFIG_SPL_STACK #else ldr sp, =SYS_INIT_SP_ADDR @@ -39,7 +39,7 @@ WEAK(lowlevel_init) * Set up global data for boards that still need it. This will be * removed soon. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD ldr r9, =gdata #else sub sp, sp, #GD_SIZE diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index 0985420fe5c..4660ff0057e 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_ARCH_NEXELL obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o else obj-y += cpu_info.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += timer.o obj-y += sromc.o endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7730a16e512..b63481b43ca 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -279,7 +279,7 @@ ENTRY(cpu_init_cp15) orr r2, r4, r2 @ r2 has combined CPU variant + revision /* Early stack for ERRATA that needs into call C code */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(SYS_INIT_SP_ADDR) diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 3e975b366c4..0624e93efde 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,10 +12,10 @@ obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o obj-$(CONFIG_MACH_SUN6I) += sram.o obj-$(CONFIG_MACH_SUN8I) += sram.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index bba4f570dbb..8747d2eb186 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -6,14 +6,14 @@ extra-y := start.o obj-y += cpu.o -ifndef CONFIG_$(SPL_TPL_)TIMER +ifndef CONFIG_$(PHASE_)TIMER obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o endif -ifndef CONFIG_$(SPL_)SYS_DCACHE_OFF +ifndef CONFIG_$(XPL_)SYS_DCACHE_OFF obj-y += cache_v8.o obj-y += cache.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o else obj-y += exceptions.o @@ -27,14 +27,14 @@ endif obj-y += cpu-dt.o obj-$(CONFIG_ARM_SMCCC) += smccc-call.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o else obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o endif -obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o +obj-$(CONFIG_$(XPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o endif diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 631d9efa5e1..e6be6359c5d 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -1016,7 +1016,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) * running however really wants to have dcache and the MMU active. Check that * everything is sane and give the developer a hint if it isn't. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache. #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index eefdf12369c..e2033dc5aff 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -5,7 +5,7 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2dbfdd08a0..f9c2083677a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -122,7 +122,7 @@ static struct mm_region early_map[] = { { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -181,7 +181,7 @@ static struct mm_region early_map[] = { { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -1055,7 +1055,7 @@ int cpu_eth_init(struct bd_info *bis) { int error = 0; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) error = fsl_mc_ldpaa_init(bis); #endif return error; @@ -1285,7 +1285,7 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) { phys_size_t ram_top = ram_size; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) ram_top = mc_get_dram_block_size(); if (ram_top > ram_size) return ram_size + ram_top; @@ -1381,7 +1381,7 @@ static int tfa_dram_init_banksize(void) if (i > 0) ret = 0; -#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1467,7 +1467,7 @@ int dram_init_banksize(void) } #endif /* CFG_SYS_MEM_RESERVE_SECURE */ -#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1624,7 +1624,7 @@ __weak int dram_init(void) #ifdef CONFIG_SYS_FSL_DDR fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ - defined(CONFIG_SPL_BUILD) + defined(CONFIG_XPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9a24d4b3031..1f03f5e2ecd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -93,7 +93,7 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) rcw_tmp = in_be32(&gur->rcwsr[7]); switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { case 2: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index b768790437f..b5213c780fb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -25,7 +25,7 @@ static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) int xfi_dpmac[XFI14 + 1]; int sgmii_dpmac[SGMII18 + 1]; @@ -162,7 +162,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, debug("Unknown SerDes lane protocol %d\n", lane_prtcl); else { serdes_prtcl_map[lane_prtcl] = 1; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], @@ -553,7 +553,7 @@ int setup_serdes_volt(u32 svdd) void fsl_serdes_init(void) { -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) int i , j; #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index 04ffefafbf7..aa0af077d2f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -23,7 +23,7 @@ static void set_icid(struct icid_id_table *tbl, int size) out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); } -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) static void set_fman_icids(struct fman_icid_id_table *tbl, int size) { int i; @@ -41,12 +41,12 @@ void set_icids(void) /* setup general icid offsets */ set_icid(icid_tbl, icid_tbl_sz); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids) { int i, ret; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 4358c6ed11c..75c204e8309 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -183,7 +183,7 @@ ENTRY(lowlevel_init) #endif /* Initialize GIC Secure Bank Status */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f bl get_gic_offset @@ -306,7 +306,7 @@ ENTRY(lowlevel_init) #endif #if !defined(CONFIG_TFABOOT) && \ - (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD)) bl fsl_ocram_init #endif @@ -314,7 +314,7 @@ ENTRY(lowlevel_init) ret ENDPROC(lowlevel_init) -#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD) ENTRY(fsl_ocram_init) mov x28, lr /* Save LR */ bl fsl_clear_ocram diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index ec80e42055d..48b95627bae 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -60,7 +60,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index a73dd316f8d..ab175b60c6c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index a739ff2da58..1f1e3d4a97b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -41,7 +41,7 @@ u32 spl_boot_device(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { @@ -136,4 +136,4 @@ int spl_start_uboot(void) return 1; } #endif /* CONFIG_SPL_OS_BOOT */ -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 74612802617..4a3b9f60e46 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -58,7 +58,7 @@ reset: .globl save_boot_params_ret save_boot_params_ret: -#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD) +#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_XPL_BUILD) /* Verify that we're 4K aligned. */ adr x0, _start ands x0, x0, #0xfff @@ -104,7 +104,7 @@ pie_skip_reloc: pie_fixup_done: #endif -#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD) .macro set_vbar, regname, reg msr \regname, \reg .endm @@ -174,7 +174,7 @@ pie_fixup_done: /* Processor specific initialization */ bl lowlevel_init -#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_XPL_BUILD) branch_if_master x0, master_cpu b spin_table_secondary_jump /* never return */ @@ -354,7 +354,7 @@ ENDPROC(smp_kick_all_cpus) /*-----------------------------------------------------------------------*/ ENTRY(c_runtime_cpu_setup) -#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD) /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 65176c8fb83..123e121e7e7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -721,13 +721,6 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-pine-h64-model-b.dtb \ sun50i-h6-tanix-tx6.dtb \ sun50i-h6-tanix-tx6-mini.dtb -dtb-$(CONFIG_MACH_SUN50I_H616) += \ - sun50i-h313-tanix-tx1.dtb \ - sun50i-h616-orangepi-zero2.dtb \ - sun50i-h618-orangepi-zero2w.dtb \ - sun50i-h618-orangepi-zero3.dtb \ - sun50i-h618-transpeed-8k618-t.dtb \ - sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ sun50i-a64-bananapi-m64.dtb \ @@ -967,7 +960,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ - imx8mp-debix-model-a.dtb \ imx8mp-dhcom-drc02.dtb \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ diff --git a/arch/arm/dts/bcm6846.dtsi b/arch/arm/dts/bcm6846.dtsi deleted file mode 100644 index 8aa47a2583b..00000000000 --- a/arch/arm/dts/bcm6846.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "brcm,bcm6846", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CA7_0>, <&CA7_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x1b>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm96846.dts b/arch/arm/dts/bcm96846.dts deleted file mode 100644 index c70ebccabc1..00000000000 --- a/arch/arm/dts/bcm96846.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6846.dtsi" - -/ { - model = "Broadcom BCM96846 Reference Board"; - compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi index 33bd89a8434..d5bd9f591e5 100644 --- a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi @@ -20,6 +20,14 @@ }; }; +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + bootph-pre-ram; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-pre-ram; +}; + &crypto { bootph-pre-ram; }; @@ -88,14 +96,6 @@ bootph-pre-ram; }; -&pmic { - bootph-pre-ram; - - regulators { - bootph-pre-ram; - }; -}; - ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts deleted file mode 100644 index 58dae612b4b..00000000000 --- a/arch/arm/dts/imx8mp-debix-model-a.dts +++ /dev/null @@ -1,507 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - * Copyright 2022 Ideas on Board Oy - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/usb/pd.h> - -#include "imx8mp.dtsi" - -/ { - model = "Polyhex Debix Model A i.MX8MPlus board"; - compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-connection-type = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { /* RTL8211E */ - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - reset-assert-us = <20>; - reset-deassert-us = <200000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4{ - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - }; -}; - -&i2c6 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { - /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* SD Card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f - MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f - MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c6: i2c6grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 - MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 - >; - }; -}; - diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi index d316e869516..af229501a4d 100644 --- a/arch/arm/dts/imx8qm-u-boot.dtsi +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -10,7 +10,7 @@ }; &binman { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u-boot-spl-ddr { align = <4>; align-size = <4>; diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi index 7622c40906f..62791c34c77 100644 --- a/arch/arm/dts/imx8qxp-u-boot.dtsi +++ b/arch/arm/dts/imx8qxp-u-boot.dtsi @@ -10,7 +10,7 @@ }; &binman { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u-boot-spl-ddr { align = <4>; align-size = <4>; diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi index 8070b62af5b..6629f3256a8 100644 --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi @@ -17,10 +17,6 @@ }; }; -&canvas { - status = "disabled"; -}; - &vpu { reg = <0x0 0xff900000 0x0 0x100000>, <0x0 0xff63c000 0x0 0x1000>, diff --git a/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi b/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi new file mode 100644 index 00000000000..cbada739042 --- /dev/null +++ b/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> + */ + +#include "meson-g12-common-u-boot.dtsi" + +&sd_emmc_c { + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>; + bus-width = <4>; +}; + +&spifc { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi b/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi new file mode 100644 index 00000000000..1c4f019120f --- /dev/null +++ b/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> + */ + +#include "meson-g12-common-u-boot.dtsi" + +&sd_emmc_c { + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>; + bus-width = <4>; +}; + +&spifc { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h313-tanix-tx1.dts b/arch/arm/dts/sun50i-h313-tanix-tx1.dts deleted file mode 100644 index bb2cde59bd0..00000000000 --- a/arch/arm/dts/sun50i-h313-tanix-tx1.dts +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2024 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Tanix TX1"; - compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - ethernet0 = &sdio_wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key { - label = "hidden"; - linux,code = <BTN_0>; - gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_BLUE>; - gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - default-state = "on"; - }; - }; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - max-frequency = <100000000>; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL, so needs to be always on. */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1120000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts b/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts deleted file mode 100644 index 4bfb52609c9..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. - */ - -/dts-v1/; - -#include "sun50i-h616-bigtreetech-cb1.dtsi" - -/ { - model = "BigTreeTech CB1"; - compatible = "bigtreetech,cb1-manta", "bigtreetech,cb1", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi deleted file mode 100644 index d12b01c5f41..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - aliases { - ethernet0 = &rtl8189ftv; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - }; - }; - - reg_vcc5v: regulator-vcc5v { - /* board wide 5V supply from carrier boards */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc33_wifi: vcc33-wifi { - compatible = "regulator-fixed"; - regulator-name = "vcc33-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; - - reg_vcc_wifi_io: vcc-wifi-io { - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <®_vcc33_wifi>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - post-power-on-delay-ms = <200>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&mmc0 { - vmmc-supply = <®_dldo1>; - /* Card detection pin is not connected */ - broken-cd; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc33_wifi>; - vqmmc-supply = <®_vcc_wifi_io>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - mmc-ddr-1_8v; - status = "okay"; - - rtl8189ftv: wifi@1 { - reg = <1>; - }; -}; - -&r_i2c { - status = "okay"; - - axp313a: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - reg_dcdc1: dcdc1 { - regulator-name = "vdd-gpu-sys"; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-always-on; - }; - - reg_dcdc2: dcdc2 { - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-ramp-delay = <200>; - regulator-always-on; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_aldo1: aldo1 { - regulator-name = "vcc-1v8-pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_dldo1: dldo1 { - regulator-name = "vcc-3v3-io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts b/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts deleted file mode 100644 index ff84a379447..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin@biqu3d.com>. - */ - -/dts-v1/; - -#include "sun50i-h616-bigtreetech-cb1.dtsi" - -/ { - model = "BigTreeTech Pi"; - compatible = "bigtreetech,pi", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi b/arch/arm/dts/sun50i-h616-cpu-opp.dtsi deleted file mode 100644 index aca22a7f019..00000000000 --- a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2023 Martin Botka <martin@somainline.org> - -/ { - cpu_opp_table: opp-table-cpu { - compatible = "allwinner,sun50i-h616-operating-points"; - nvmem-cells = <&cpu_speed_grade>; - opp-shared; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x12>; - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-microvolt-speed1 = <900000>; - opp-microvolt-speed4 = <940000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x12>; - }; - - opp-936000000 { - opp-hz = /bits/ 64 <936000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt-speed0 = <950000>; - opp-microvolt-speed1 = <940000>; - opp-microvolt-speed2 = <950000>; - opp-microvolt-speed3 = <950000>; - opp-microvolt-speed4 = <1020000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt-speed0 = <1000000>; - opp-microvolt-speed2 = <1000000>; - opp-microvolt-speed3 = <1000000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt-speed0 = <1050000>; - opp-microvolt-speed1 = <1020000>; - opp-microvolt-speed2 = <1050000>; - opp-microvolt-speed3 = <1050000>; - opp-microvolt-speed4 = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1d>; - }; - - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt-speed1 = <1100000>; - opp-microvolt-speed3 = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0a>; - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu1 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu2 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu3 { - operating-points-v2 = <&cpu_opp_table>; -}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi deleted file mode 100644 index fc7315b9440..00000000000 --- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Arm Ltd. - * - * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3. - * Excludes PMIC nodes and properties, since they are different between the two. - */ - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_RED>; - gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - default-state = "on"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; - enable-active-high; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - }; -}; - -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on headers only. */ - -&emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-handle = <&ext_rgmii_phy>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts deleted file mode 100644 index a360d8567f9..00000000000 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616-orangepi-zero.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -/ { - model = "OrangePi Zero2"; - compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&emac0 { - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - phy-mode = "rgmii"; - phy-supply = <®_dcdce>; -}; - -&mmc0 { - vmmc-supply = <®_dcdce>; -}; - -&r_rsb { - status = "okay"; - - axp305: pmic@745 { - compatible = "x-powers,axp305", "x-powers,axp805", - "x-powers,axp806"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x745>; - - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-sys"; - }; - - reg_aldo2: aldo2 { /* 3.3V on headers */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext"; - }; - - reg_aldo3: aldo3 { /* 3.3V on headers */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext2"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - bldo2 { - /* unused */ - }; - - bldo3 { - /* unused */ - }; - - bldo4 { - /* unused */ - }; - - cldo1 { - /* reserved */ - }; - - cldo2 { - /* unused */ - }; - - cldo3 { - /* unused */ - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-dram"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-eth-mmc"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pf-supply = <®_aldo1>; - vcc-pg-supply = <®_bldo1>; - vcc-ph-supply = <®_aldo1>; - vcc-pi-supply = <®_aldo1>; -}; diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts deleted file mode 100644 index 26d25b5b59e..00000000000 --- a/arch/arm/dts/sun50i-h616-x96-mate.dts +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "X96 Mate"; - compatible = "hechuang,x96-mate", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdce>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_dcdce>; - vqmmc-supply = <®_bldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp305: pmic@745 { - compatible = "x-powers,axp305", "x-powers,axp805", - "x-powers,axp806"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x745>; - - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-sys"; - }; - - /* Enabled by the Android BSP */ - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext"; - status = "disabled"; - }; - - /* Enabled by the Android BSP */ - reg_aldo3: aldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext2"; - status = "disabled"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Enabled by the Android BSP */ - reg_bldo2: bldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8-2"; - status = "disabled"; - }; - - bldo3 { - /* unused */ - }; - - bldo4 { - /* unused */ - }; - - cldo1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc2v5"; - }; - - cldo2 { - /* unused */ - }; - - cldo3 { - /* unused */ - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vdd-dram"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-eth-mmc"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi deleted file mode 100644 index 921d5f61d8d..00000000000 --- a/arch/arm/dts/sun50i-h616.dtsi +++ /dev/null @@ -1,930 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Arm Ltd. -// based on the H6 dtsi, which is: -// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/sun50i-h616-ccu.h> -#include <dt-bindings/clock/sun50i-h6-r-ccu.h> -#include <dt-bindings/clock/sun6i-rtc.h> -#include <dt-bindings/reset/sun50i-h616-ccu.h> -#include <dt-bindings/reset/sun50i-h6-r-ccu.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * 256 KiB reserved for Trusted Firmware-A (BL31). - * This is added by BL31 itself, but some bootloaders fail - * to propagate this into the DTB handed to kernels. - */ - secmon@40000000 { - reg = <0x0 0x40000000 0x0 0x40000>; - no-map; - }; - }; - - osc24M: osc24M-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - arm,no-tick-in-suspend; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; - - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h616-system-control"; - reg = <0x03000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@28000 { - compatible = "mmio-sram"; - reg = <0x00028000 0x30000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00028000 0x30000>; - }; - }; - - ccu: clock@3001000 { - compatible = "allwinner,sun50i-h616-ccu"; - reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - dma: dma-controller@3002000 { - compatible = "allwinner,sun50i-h616-dma", - "allwinner,sun50i-a100-dma"; - reg = <0x03002000 0x1000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; - clock-names = "bus", "mbus"; - dma-channels = <16>; - dma-requests = <49>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - sid: efuse@3006000 { - compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; - reg = <0x03006000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@14 { - reg = <0x14 0x8>; - }; - - cpu_speed_grade: cpu-speed-grade@0 { - reg = <0x0 2>; - }; - }; - - watchdog: watchdog@30090a0 { - compatible = "allwinner,sun50i-h616-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x030090a0 0x20>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-h616-pinctrl"; - reg = <0x0300b000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - ext_rgmii_pins: rgmii-pins { - pins = "PI0", "PI1", "PI2", "PI3", "PI4", - "PI5", "PI7", "PI8", "PI9", "PI10", - "PI11", "PI12", "PI13", "PI14", "PI15", - "PI16"; - function = "emac0"; - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PI5", "PI6"; - function = "i2c0"; - }; - - i2c3_ph_pins: i2c3-ph-pins { - pins = "PH4", "PH5"; - function = "i2c3"; - }; - - ir_rx_pin: ir-rx-pin { - pins = "PH10"; - function = "ir_rx"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC0", "PC1", "PC5", "PC6", - "PC8", "PC9", "PC10", "PC11", - "PC13", "PC14", "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - spi0_pins: spi0-pins { - pins = "PC0", "PC2", "PC4"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs0_pin: spi0-cs0-pin { - pins = "PC3"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi1_pins: spi1-pins { - pins = "PH6", "PH7", "PH8"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs0_pin: spi1-cs0-pin { - pins = "PH5"; - function = "spi1"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH4"; - function = "spdif"; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH0", "PH1"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - /omit-if-no-ref/ - x32clk_fanout_pin: x32clk-fanout-pin { - pins = "PG10"; - function = "clock"; - }; - }; - - gic: interrupt-controller@3021000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - mmc0: mmc@4020000 { - compatible = "allwinner,sun50i-h616-mmc", - "allwinner,sun50i-a100-mmc"; - reg = <0x04020000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@4021000 { - compatible = "allwinner,sun50i-h616-mmc", - "allwinner,sun50i-a100-mmc"; - reg = <0x04021000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@4022000 { - compatible = "allwinner,sun50i-h616-emmc", - "allwinner,sun50i-a100-emmc"; - reg = <0x04022000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@5000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000000 0x400>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - dmas = <&dma 14>, <&dma 14>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@5000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000400 0x400>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@5000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000800 0x400>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - dmas = <&dma 16>, <&dma 16>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@5000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000c00 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - dmas = <&dma 17>, <&dma 17>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@5001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05001000 0x400>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - dmas = <&dma 18>, <&dma 18>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - uart5: serial@5001400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05001400 0x400>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART5>; - dmas = <&dma 19>, <&dma 19>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART5>; - status = "disabled"; - }; - - i2c0: i2c@5002000 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002000 0x400>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C0>; - dmas = <&dma 43>, <&dma 43>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@5002400 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002400 0x400>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C1>; - dmas = <&dma 44>, <&dma 44>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@5002800 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002800 0x400>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C2>; - dmas = <&dma 45>, <&dma 45>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@5002c00 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002c00 0x400>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C3>; - dmas = <&dma 46>, <&dma 46>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@5003000 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05003000 0x400>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C4>; - dmas = <&dma 47>, <&dma 47>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@5010000 { - compatible = "allwinner,sun50i-h616-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x05010000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@5011000 { - compatible = "allwinner,sun50i-h616-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x05011000 0x1000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac0: ethernet@5020000 { - compatible = "allwinner,sun50i-h616-emac0", - "allwinner,sun50i-a64-emac"; - reg = <0x05020000 0x10000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_EMAC0>; - clock-names = "stmmaceth"; - resets = <&ccu RST_BUS_EMAC0>; - reset-names = "stmmaceth"; - syscon = <&syscon>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - spdif: spdif@5093000 { - compatible = "allwinner,sun50i-h616-spdif"; - reg = <0x05093000 0x400>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - resets = <&ccu RST_BUS_SPDIF>; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - ths: thermal-sensor@5070400 { - compatible = "allwinner,sun50i-h616-ths"; - reg = <0x05070400 0x400>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_THS>; - clock-names = "bus"; - resets = <&ccu RST_BUS_THS>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - allwinner,sram = <&syscon>; - #thermal-sensor-cells = <1>; - }; - - usbotg: usb@5100000 { - compatible = "allwinner,sun50i-h616-musb", - "allwinner,sun8i-h3-musb"; - reg = <0x05100000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@5100400 { - compatible = "allwinner,sun50i-h616-usb-phy"; - reg = <0x05100400 0x24>, - <0x05101800 0x14>, - <0x05200800 0x14>, - <0x05310800 0x14>, - <0x05311800 0x14>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>, - <&ccu CLK_BUS_EHCI2>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy", - "pmu2_clk"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@5101000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05101000 0x100>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@5101400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05101400 0x100>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@5200000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05200000 0x100>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_BUS_EHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>, - <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@5200400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05200400 0x100>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@5310000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05310000 0x100>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_BUS_EHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>, - <&ccu RST_BUS_EHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@5310400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05310400 0x100>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@5311000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05311000 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_BUS_EHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>, - <&ccu RST_BUS_EHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@5311400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05311400 0x100>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h616-rtc"; - reg = <0x07000000 0x400>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, - <&ccu CLK_PLL_SYSTEM_32K>; - clock-names = "bus", "hosc", - "pll-32k"; - #clock-cells = <1>; - }; - - r_ccu: clock@7010000 { - compatible = "allwinner,sun50i-h616-r-ccu"; - reg = <0x07010000 0x210>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - nmi_intc: interrupt-controller@7010320 { - compatible = "allwinner,sun50i-h616-nmi", - "allwinner,sun9i-a80-nmi"; - reg = <0x07010320 0xc>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - }; - - r_pio: pinctrl@7022000 { - compatible = "allwinner,sun50i-h616-r-pinctrl"; - reg = <0x07022000 0x400>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - - /omit-if-no-ref/ - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - }; - }; - - ir: ir@7040000 { - compatible = "allwinner,sun50i-h616-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x07040000 0x400>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1_IR>, - <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_R_APB1_IR>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_rx_pin>; - status = "disabled"; - }; - - r_i2c: i2c@7081400 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x07081400 0x400>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB2_I2C>; - dmas = <&dma 48>, <&dma 48>; - dma-names = "rx", "tx"; - resets = <&r_ccu RST_R_APB2_I2C>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_rsb: rsb@7083000 { - compatible = "allwinner,sun50i-h616-rsb", - "allwinner,sun8i-a23-rsb"; - reg = <0x07083000 0x400>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB2_RSB>; - clock-frequency = <3000000>; - resets = <&r_ccu RST_R_APB2_RSB>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <500>; - polling-delay = <1000>; - thermal-sensors = <&ths 2>; - sustainable-power = <1000>; - - trips { - cpu_threshold: cpu-trip-0 { - temperature = <60000>; - type = "passive"; - hysteresis = <0>; - }; - cpu_target: cpu-trip-1 { - temperature = <70000>; - type = "passive"; - hysteresis = <0>; - }; - cpu_critical: cpu-trip-2 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <500>; - polling-delay = <1000>; - thermal-sensors = <&ths 0>; - sustainable-power = <1100>; - - trips { - gpu_temp_critical: gpu-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - ve-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - - trips { - ve_temp_critical: ve-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 3>; - - trips { - ddr_temp_critical: ddr-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi b/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi deleted file mode 100644 index e92d150aaf1..00000000000 --- a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) Jisheng Zhang <jszhang@kernel.org> - */ - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8-pll"; - }; - - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-io"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; diff --git a/arch/arm/dts/sun50i-h618-longanpi-3h.dts b/arch/arm/dts/sun50i-h618-longanpi-3h.dts deleted file mode 100644 index 18b29c6b867..00000000000 --- a/arch/arm/dts/sun50i-h618-longanpi-3h.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) Jisheng Zhang <jszhang@kernel.org> - */ - -/dts-v1/; - -#include "sun50i-h618-longan-module-3h.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Sipeed Longan Pi 3H"; - compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618"; - - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - color = <LED_COLOR_ID_ORANGE>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <0>; - gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ - }; - - led-1 { - color = <LED_COLOR_ID_ORANGE>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */ - }; - }; - - reg_vcc5v: regulator-vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; -}; - -&axp313 { - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -/* WiFi & BT combo module is connected to this Host */ -&ehci3 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - phy-supply = <®_vcc3v3>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v>; - usb2_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts b/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts deleted file mode 100644 index 6a4f0da9723..00000000000 --- a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "OrangePi Zero 2W"; - compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: vcc3v3 { - /* SY8089 DC/DC converter */ - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_vcc5v>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on the FPC connector (or the exansion board) */ - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; /* internally via VCC-IO */ - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; /* internally via VCC-IO */ - vcc-pi-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL and DRAM */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts deleted file mode 100644 index e1cd7572a14..00000000000 --- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616-orangepi-zero.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -/ { - model = "OrangePi Zero3"; - compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&emac0 { - allwinner,tx-delay-ps = <700>; - phy-mode = "rgmii-rxid"; - phy-supply = <®_dldo1>; -}; - -&ext_rgmii_phy { - motorcomm,clk-out-frequency-hz = <125000000>; -}; - -&mmc0 { - /* - * The schematic shows the card detect pin wired up to PF6, via an - * inverter, but it just doesn't work. - */ - broken-cd; - vmmc-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL, so needs to be always on. */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; diff --git a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts b/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts deleted file mode 100644 index d6631bfe629..00000000000 --- a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Transpeed 8K618-T"; - compatible = "transpeed,8k618-t", "allwinner,sun50i-h618"; - - aliases { - ethernet1 = &sdio_wifi; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: vcc3v3 { - /* discrete 3.3V regulator */ - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dldo1>; - cd-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>; /* PI16 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8-pll"; - }; - - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-io-mmc"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pg-supply = <®_dldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts deleted file mode 100644 index ee30584b6ad..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Anbernic RG35XX 2024"; - chassis-type = "handset"; - compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys_gamepad: gpio-keys-gamepad { - compatible = "gpio-keys"; - - button-a { - label = "Action-Pad A"; - gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_EAST>; - }; - - button-b { - label = "Action-Pad B"; - gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_SOUTH>; - }; - - button-down { - label = "D-Pad Down"; - gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_DOWN>; - }; - - button-l1 { - label = "Key L1"; - gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TL>; - }; - - button-l2 { - label = "Key L2"; - gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TL2>; - }; - - button-left { - label = "D-Pad left"; - gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_LEFT>; - }; - - button-menu { - label = "Key Menu"; - gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_MODE>; - }; - - button-r1 { - label = "Key R1"; - gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TR>; - }; - - button-r2 { - label = "Key R2"; - gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TR2>; - }; - - button-right { - label = "D-Pad Right"; - gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_RIGHT>; - }; - - button-select { - label = "Key Select"; - gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_SELECT>; - }; - button-start { - label = "Key Start"; - gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_START>; - }; - - button-up { - label = "D-Pad Up"; - gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_UP>; - }; - - button-x { - label = "Action-Pad X"; - gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_NORTH>; - }; - - button-y { - label = "Action Pad Y"; - gpios = <&pio 0 2 GPIO_ACTIVE_LOW>; /* PA2 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_WEST>; - }; - }; - - gpio-keys-volume { - compatible = "gpio-keys"; - autorepeat; - - button-vol-up { - label = "Key Volume Up"; - gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; /* PE1 */ - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; - }; - - button-vol-down { - label = "Key Volume Down"; - gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PE2 */ - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ - default-state = "on"; - }; - }; - - reg_vcc5v: regulator-vcc5v { /* USB-C power input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc1>; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_cldo3>; - disable-wp; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_cldo3>; - vcc-pc-supply = <®_cldo3>; - vcc-pe-supply = <®_cldo3>; - vcc-pf-supply = <®_cldo3>; - vcc-pg-supply = <®_aldo4>; - vcc-ph-supply = <®_cldo3>; - vcc-pi-supply = <®_cldo3>; -}; - -&r_rsb { - status = "okay"; - - axp717: pmic@3a3 { - compatible = "x-powers,axp717"; - reg = <0x3a3>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - vin4-supply = <®_vcc5v>; - - regulators { - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <940000>; - regulator-max-microvolt = <940000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - - reg_aldo1: aldo1 { - /* 1.8v - unused */ - }; - - reg_aldo2: aldo2 { - /* 1.8v - unused */ - }; - - reg_aldo3: aldo3 { - /* 1.8v - unused */ - }; - - reg_aldo4: aldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pg"; - }; - - reg_bldo1: bldo1 { - /* 1.8v - unused */ - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pll"; - }; - - reg_bldo3: bldo3 { - /* 2.8v - unused */ - }; - - reg_bldo4: bldo4 { - /* 1.2v - unused */ - }; - - reg_cldo1: cldo1 { - /* 3.3v - audio codec - not yet implemented */ - }; - - reg_cldo2: cldo2 { - /* 3.3v - unused */ - }; - - reg_cldo3: cldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-io"; - }; - - reg_cldo4: cldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_boost: boost { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5200000>; - regulator-name = "boost"; - }; - - reg_cpusldo: cpusldo { - /* unused */ - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */ -&usbotg { - dr_mode = "peripheral"; /* USB type-C receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts deleted file mode 100644 index 63036256917..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - * Copyright (C) 2024 Chris Morgan <macroalpha82@gmail.com>. - */ - -#include "sun50i-h700-anbernic-rg35xx-plus.dts" - -/ { - model = "Anbernic RG35XX H"; - compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; -}; - -&gpio_keys_gamepad { - button-thumbl { - label = "GPIO Thumb Left"; - gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_THUMBL>; - }; - - button-thumbr { - label = "GPIO Thumb Right"; - gpios = <&pio 4 9 GPIO_ACTIVE_LOW>; /* PE9 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_THUMBR>; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts deleted file mode 100644 index 60a8e492210..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - */ - -#include "sun50i-h700-anbernic-rg35xx-2024.dts" - -/ { - model = "Anbernic RG35XX Plus"; - compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700"; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - post-power-on-delay-ms = <200>; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; -}; - -/* SDIO WiFi RTL8821CS */ -&mmc1 { - vmmc-supply = <®_cldo4>; - vqmmc-supply = <®_aldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - interrupt-parent = <&pio>; - interrupts = <6 15 IRQ_TYPE_LEVEL_LOW>; /* PG15 */ - interrupt-names = "host-wake"; - }; -}; - -/* Bluetooth RTL8821CS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; - device-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */ - enable-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>; /* PG19 */ - host-wake-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16 */ - }; -}; diff --git a/arch/arm/dts/tegra-u-boot.dtsi b/arch/arm/dts/tegra-u-boot.dtsi index b3d0dec7757..c200f2d3a0b 100644 --- a/arch/arm/dts/tegra-u-boot.dtsi +++ b/arch/arm/dts/tegra-u-boot.dtsi @@ -19,6 +19,27 @@ }; }; +#ifdef CONFIG_MULTI_DTB_FIT + image2 { + filename = "u-boot-dtb-tegra.bin"; + pad-byte = <0xff>; + u-boot-spl { + }; + u-boot-nodtb { + offset = <(U_BOOT_OFFSET)>; + }; + fit-dtb { +#ifdef CONFIG_MULTI_DTB_FIT_LZO + filename = "fit-dtb.blob.lzo"; +#elif CONFIG_MULTI_DTB_FIT_GZIP + filename = "fit-dtb.blob.gz"; +#else + filename = "fit-dtb.blob"; +#endif + type = "blob"; + }; + }; +#else /* Same as image1 - some tools still expect the -dtb suffix */ image2 { filename = "u-boot-dtb-tegra.bin"; @@ -29,6 +50,7 @@ offset = <(U_BOOT_OFFSET)>; }; }; +#endif image3 { filename = "u-boot-nodtb-tegra.bin"; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index d5f63f4a7ed..22671d4bbfd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -12,13 +12,13 @@ #include <asm/armv8/sec_firmware.h> struct icid_id_table { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD const char *compat; phys_addr_t compat_addr; #endif phys_addr_t reg_addr; u32 reg; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD u32 id; #endif bool le; @@ -35,7 +35,7 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void); void fdt_fixup_icid(void *blob); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ { .reg = regA, \ .reg_addr = addr, \ diff --git a/arch/arm/include/asm/arch-imx8/boot0.h b/arch/arm/include/asm/arch-imx8/boot0.h index 5ce781adb75..fc580b20a46 100644 --- a/arch/arm/include/asm/arch-imx8/boot0.h +++ b/arch/arm/include/asm/arch-imx8/boot0.h @@ -3,7 +3,7 @@ * Copyright 2019 NXP */ -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* * We use absolute address not PC relative address to jump. * When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000, diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 4675dc3c533..b499d975526 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -16,7 +16,7 @@ void lpc32xx_slc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); void lpc32xx_ssp_init(void); void lpc32xx_usb_init(void); -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) void ddr_init(const struct emc_dram_settings *dram); #endif #endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-mx6/litesom.h b/arch/arm/include/asm/arch-mx6/litesom.h index 37a16d2c309..642ed22bffc 100644 --- a/arch/arm/include/asm/arch-mx6/litesom.h +++ b/arch/arm/include/asm/arch-mx6/litesom.h @@ -8,7 +8,7 @@ int litesom_mmc_init(struct bd_info *bis); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void litesom_init_f(void); #endif diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index dbc97b25df8..ad9c1ac906a 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -5,7 +5,7 @@ #ifndef __ASM_ARCH_MX6_DDR_H__ #define __ASM_ARCH_MX6_DDR_H__ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifdef CONFIG_MX6Q #include "mx6q-ddr.h" #else @@ -488,7 +488,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, const struct mx6_mmdc_calibration *, const void *); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define MX6_MMDC_P0_MDCTL 0x021b0000 #define MX6_MMDC_P0_MDPDC 0x021b0004 diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 17afd1b29e4..f8a56495acd 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -14,7 +14,7 @@ int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int), int (*cd)(int)); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if defined(CONFIG_MX23) #include <asm/arch/iomux-mx23.h> diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h index 6bf3828c84e..eaf81554f5b 100644 --- a/arch/arm/include/asm/arch-rk3066/boot0.h +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -10,7 +10,7 @@ * (containing the magic 'RK30'). This magic constant will be written into * the final image by the rkimage tool, but we need to reserve space for it here. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD b 1f /* if overwritten, entry-address is at the next word */ 1: #endif @@ -68,7 +68,7 @@ back_to_bootrom: pop {r1-r12, pc} #endif -#if (defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_XPL_BUILD)) /* U-Boot proper of armv7 does not need this */ b reset #endif diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 0c375e543a5..edb2a31c348 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -12,7 +12,7 @@ * To make life easier for everyone, we build the SPL binary with * space for this 4-byte header already included in the binary. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * We need to add 4 bytes of space for the 'RK33' at the * beginning of the executable. However, as we want to keep @@ -39,7 +39,7 @@ entry_counter: .word 0 #endif -#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64)) +#if (defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARM64)) /* U-Boot proper of armv7 do not need this */ b reset #endif @@ -54,7 +54,7 @@ _start: ARM_VECTORS #endif -#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \ +#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_XPL_BUILD) && \ (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h index 49a1f763795..ae273de3144 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h @@ -11,7 +11,7 @@ #define KHz 1000 #define OSC_HZ (24 * MHz) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define APLL_HZ (1008 * MHz) #else #define APLL_HZ (816 * MHz) @@ -20,7 +20,7 @@ #define CPLL_HZ (500 * MHz) #define HPLL_HZ (1400 * MHz) #define PCLK_PDPMU_HZ (100 * MHz) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define ACLK_PDBUS_HZ (396 * MHz) #else #define ACLK_PDBUS_HZ (500 * MHz) @@ -32,7 +32,7 @@ #define HCLK_PDCORE_HZ (200 * MHz) #define HCLK_PDAUDIO_HZ (150 * MHz) #define CLK_OSC0_DIV_HZ (32768) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define ACLK_PDVI_HZ (297 * MHz) #define CLK_ISP_HZ (297 * MHz) #define ACLK_PDISPP_HZ (297 * MHz) @@ -324,7 +324,7 @@ enum { DCLK_VOP_DIV_SHIFT = 0, DCLK_VOP_DIV_MASK = 0xff, -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) /* CRU_CLK_SEL49_CON */ ACLK_PDVI_SEL_SHIFT = 6, ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT, @@ -397,7 +397,7 @@ enum { CLK_GMAC_SRC_DIV_SHIFT = 0, CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT, -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) /* CRU_CLK_SEL68_CON */ ACLK_PDISPP_SEL_SHIFT = 6, ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT, diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index cad25c50bc6..6b2bb5a4586 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -5,7 +5,7 @@ #include <asm/arch/cpu.h> -#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_XPL_BUILD) /* reserve space for BOOT0 header information */ b reset .space 1532 @@ -49,7 +49,7 @@ .word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr .word SUNXI_SRAMC_BASE .word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_TEXT_BASE diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h index 064602292b6..92c7721a530 100644 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -23,7 +23,7 @@ void sdelay(unsigned long); void return_to_fel(uint32_t lr, uint32_t sp); /* Board / SoC level designware gmac init */ -#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC +#if !defined CONFIG_XPL_BUILD && defined CONFIG_SUN7I_GMAC void eth_init_board(void); #else static inline void eth_init_board(void) {} diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 7a4e0972fb7..a399c94213b 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -68,8 +68,9 @@ struct timerus { /* These are the available SKUs (product types) for Tegra */ enum { - SKU_ID_T20_7 = 0x7, + SKU_ID_AP20 = 0x7, SKU_ID_T20 = 0x8, + SKU_ID_AP20H = 0xf, SKU_ID_T25SE = 0x14, SKU_ID_AP25 = 0x17, SKU_ID_T25 = 0x18, diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index 6e6ea1443cb..2ae109ab6c1 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -336,10 +336,13 @@ struct usb_ctlr { #define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 #define UTMIP_XCVR_HSSLEW_MSB_MASK \ (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 -#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_SHIFT 0 -#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) + +#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) +#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) +#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) +#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) +#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) +#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) /* USBx_UTMIP_XCVR_CFG1_0 */ #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h index 2e8b3359161..05414061a23 100644 --- a/arch/arm/include/asm/arch-tegra30/funcmux.h +++ b/arch/arm/include/asm/arch-tegra30/funcmux.h @@ -16,5 +16,6 @@ enum { /* UART configs */ FUNCMUX_UART1_ULPI = 0, + FUNCMUX_UART5_SDMMC1 = 1, }; #endif /* _TEGRA30_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 15627c96e90..382a6d420a2 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,8 +8,8 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_CHAIN_OF_TRUST -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif /* #ifndef CONFIG_XPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index d4ac567e7ed..19d12696a1e 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -47,6 +47,8 @@ #define ELE_ATTEST_REQ (0xDB) #define ELE_RELEASE_PATCH_REQ (0xDC) #define ELE_OTP_SEQ_SWITH_REQ (0xDD) +#define ELE_WRITE_SHADOW_REQ (0xF2) +#define ELE_READ_SHADOW_REQ (0xF3) /* ELE failure indications */ #define ELE_ROM_PING_FAILURE_IND (0x0A) @@ -154,4 +156,6 @@ int ele_release_m33_trout(void); int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response); int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); int ele_start_rng(void); +int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response); +int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); #endif diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h index a96a8382fb6..514086a1bc4 100644 --- a/arch/arm/include/asm/ti-common/sys_proto.h +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -57,7 +57,7 @@ static inline u8 uboot_loaded_by_spl(void) */ static inline u32 omap_hw_init_context(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD return OMAP_INIT_CONTEXT_SPL; #else if (uboot_loaded_by_spl()) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 67275fba616..f254186c525 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -21,7 +21,7 @@ else obj-y += setjmp.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifdef CONFIG_ARM64 obj-y += relocate_64.o else @@ -34,7 +34,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o else -obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o +obj-$(CONFIG_$(PHASE_)FRAMEWORK) += spl.o ifdef CONFIG_SPL_FRAMEWORK obj-$(CONFIG_CMD_BOOTI) += image.o obj-$(CONFIG_CMD_BOOTZ) += zimage.o @@ -42,14 +42,14 @@ endif obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o endif ifdef CONFIG_ARM64 -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset-arm64.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy-arm64.o else -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy.o endif -obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o -obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o +obj-$(CONFIG_$(PHASE_)SYS_L2_PL310) += cache-pl310.o +obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),) obj-y += save_prev_bl_data.o @@ -73,7 +73,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_$(SPL_TPL_)SYSRESET +ifndef CONFIG_$(PHASE_)SYSRESET obj-y += reset.o endif @@ -94,7 +94,7 @@ endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL ifndef CONFIG_HAS_THUMB2 @@ -129,11 +129,3 @@ CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI) CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI) CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI) - -extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC) -# TODO: As of v2019.01 the relocation code for the EFI application cannot -# be built on ARMv7-M. -ifndef CONFIG_CPU_V7M -#extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC) -endif -extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 648edf308f6..516754caeaf 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -60,7 +60,7 @@ int check_cache_range(unsigned long start, unsigned long stop) ok = 0; if (!ok) { - warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + warn_non_xpl("CACHE: Misaligned operation at range [%08lx, %08lx]\n", start, stop); } diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a0311438b45..3e4906e273d 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -102,7 +102,7 @@ ENTRY(_main) #if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) ldr r0, =(CONFIG_TPL_STACK) -#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(SYS_INIT_SP_ADDR) @@ -119,14 +119,14 @@ ENTRY(_main) bl debug_uart_init #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS) CLEAR_BSS #endif mov r0, #0 bl board_init_f -#if ! defined(CONFIG_SPL_BUILD) +#if ! defined(CONFIG_XPL_BUILD) /* * Set up intermediate environment (new sp and gd) and call @@ -171,13 +171,13 @@ here: bl c_runtime_cpu_setup /* we still call old routine here */ #endif -#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) +#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) -#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS) +#if !defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS) CLEAR_BSS #endif -# ifdef CONFIG_SPL_BUILD +# ifdef CONFIG_XPL_BUILD /* Use a DRAM stack for the rest of SPL, if requested */ bl spl_relocate_stack_gd cmp r0, #0 @@ -185,7 +185,7 @@ here: movne r9, r0 # endif -#if ! defined(CONFIG_SPL_BUILD) +#if ! defined(CONFIG_XPL_BUILD) bl coloured_LED_init bl red_led_on #endif diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index dcc924dd2f4..32401f544a7 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -71,7 +71,7 @@ ENTRY(_main) */ #if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) ldr x0, =(CONFIG_TPL_STACK) -#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) #elif defined(CONFIG_INIT_SP_RELATIVE) #if CONFIG_POSITION_INDEPENDENT @@ -99,7 +99,7 @@ ENTRY(_main) mov x0, #0 bl board_init_f -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /* * Set up intermediate environment (new sp and gd) and call * relocate_code(addr_moni). Trick here is that we'll return @@ -139,9 +139,9 @@ relocation_return: * Set up final (full) environment */ bl c_runtime_cpu_setup /* still call old routine */ -#endif /* !CONFIG_SPL_BUILD */ -#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) -#if defined(CONFIG_SPL_BUILD) +#endif /* !CONFIG_XPL_BUILD */ +#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) +#if defined(CONFIG_XPL_BUILD) bl spl_relocate_stack_gd /* may return NULL */ /* set up gd here, outside any C code, if new stack is returned */ cmp x0, #0 diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index 0a96ba1355f..602efe04c04 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -12,7 +12,7 @@ int raise (int signum) { /* Even if printf() is available, it's large. Punt it for SPL builds */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) printf("raise: Signal # %d caught\n", signum); #endif return 0; diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index 2b21ec0734e..78507b76894 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; int arch_reserve_stacks(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ gd->irq_sp = gd->start_addr_sp; #else diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index b6b879339df..cf3f6c3e65c 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -133,7 +133,7 @@ _fiq: .word fiq /* SPL interrupt handling: just hang */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) .align 5 @@ -166,7 +166,7 @@ fiq: b 1b /* hang and never return */ #endif -#else /* !CONFIG_SPL_BUILD */ +#else /* !CONFIG_XPL_BUILD */ /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN @@ -332,4 +332,4 @@ fiq: bad_save_user_regs bl do_fiq -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c index 51287251b3f..7e1cd4dd8bc 100644 --- a/arch/arm/lib/zimage.c +++ b/arch/arm/lib/zimage.c @@ -24,14 +24,14 @@ int bootz_setup(ulong image, ulong *start, ulong *end) if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC && zi->zi_magic != BAREBOX_IMAGE_MAGIC) { - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) puts("zimage: Bad magic!\n"); return 1; } *start = zi->zi_start; *end = zi->zi_end; - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start, *end); diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile index 448d3201aff..18f9f75e8ef 100644 --- a/arch/arm/mach-aspeed/ast2600/Makefile +++ b/arch/arm/mach-aspeed/ast2600/Makefile @@ -1,2 +1,2 @@ obj-y += lowlevel_init.o board_common.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/arch/arm/mach-aspeed/ast2600/lowlevel_init.S b/arch/arm/mach-aspeed/ast2600/lowlevel_init.S index 594963d039d..d1c31068685 100644 --- a/arch/arm/mach-aspeed/ast2600/lowlevel_init.S +++ b/arch/arm/mach-aspeed/ast2600/lowlevel_init.S @@ -97,7 +97,7 @@ .globl lowlevel_init lowlevel_init: -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) mov pc, lr #else /* setup ARM arch timer frequency */ diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index cbd0ed68c27..447cd80642c 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o -ifneq ($(CONFIG_SPL_BUILD),) +ifneq ($(CONFIG_XPL_BUILD),) obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index a8916862b3f..8f0bc5d997e 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o obj-$(CONFIG_SAM9X60) += sam9x60_devices.o obj-y += clock.o obj-y += cpu.o -ifndef CONFIG_$(SPL_TPL_)SYSRESET +ifndef CONFIG_$(PHASE_)SYSRESET obj-y += reset.o endif ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) @@ -32,7 +32,7 @@ obj-y += lowlevel_init.o endif endif -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cache.o := -marm diff --git a/arch/arm/mach-at91/config.mk b/arch/arm/mach-at91/config.mk index 5426394651e..a31612b8179 100644 --- a/arch/arm/mach-at91/config.mk +++ b/arch/arm/mach-at91/config.mk @@ -3,7 +3,7 @@ PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) endif ifeq ($(CONFIG_CPU_V7A),y) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-y += u-boot.img endif endif diff --git a/arch/arm/mach-bcmbca/bcm6846/Kconfig b/arch/arm/mach-bcmbca/bcm6846/Kconfig index 229ab88dbb0..1f5639f46df 100644 --- a/arch/arm/mach-bcmbca/bcm6846/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6846/Kconfig @@ -8,6 +8,10 @@ if BCM6846 config TARGET_BCM96846 bool "Broadcom 6846 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM + imply MTD_RAW_NAND + imply NAND_BRCMNAND + imply NAND_BRCMNAND_BCMBCA config SYS_SOC default "bcm6846" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index ae171e3ee22..c994f97bab8 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -9,7 +9,7 @@ obj-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o obj-$(CONFIG_SOC_DA850) += da850_pinmux.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o endif diff --git a/arch/arm/mach-davinci/config.mk b/arch/arm/mach-davinci/config.mk index edbac8e8e21..3b972a26c0c 100644 --- a/arch/arm/mach-davinci/config.mk +++ b/arch/arm/mach-davinci/config.mk @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2012, Texas Instruments, Incorporated - https://www.ti.com/ -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais endif diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 6c97e5810cd..07125eac7cd 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index dd097cf5418..ebdc3b89d05 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o obj-$(CONFIG_EXYNOS5420) += sec_boot.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 0967ab995a9..0c50b2e2b99 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -221,8 +221,8 @@ int do_lowlevel_init(void) if (actions & DO_CLOCKS) { system_clock_init(); #ifdef CONFIG_DEBUG_UART -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ - !defined(CONFIG_SPL_BUILD) +#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ + !defined(CONFIG_XPL_BUILD) exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); debug_uart_init(); #endif diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 07d19fd17ba..48c325190d5 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -171,7 +171,7 @@ static int exynos5420_mmc_config(int peripheral, int flags) * this same assumption. */ if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD gpio_request(i, "sdmmc0_vdden"); #endif gpio_set_value(i, 1); diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index f8903afc92e..21d955b4aef 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -10,7 +10,7 @@ obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),imx8m)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o @@ -22,7 +22,7 @@ obj-y += cpu.o endif ifeq ($(SOC),$(filter $(SOC),imx8m imx9)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-y += fdt.o endif endif @@ -38,7 +38,7 @@ endif ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imx9 imxrt)) obj-y += misc.o obj-$(CONFIG_CMD_PRIBLOB) += priblob.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o @@ -46,7 +46,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o endif ifeq ($(SOC),$(filter $(SOC),mx7 imx8m)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o endif endif @@ -57,10 +57,10 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o init.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif -obj-$(CONFIG_$(SPL_)SATA) += sata.o +obj-$(CONFIG_$(XPL_)SATA) += sata.o obj-$(CONFIG_IMX_HAB) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif @@ -73,18 +73,18 @@ obj-y += ddrmc-vf610.o obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o endif ifeq ($(SOC),$(filter $(SOC),imx8)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif endif -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o endif -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o endif @@ -128,7 +128,7 @@ container.cfg: $(IMX_CONTAINER_CFG) FORCE ifeq ($(CONFIG_ARCH_IMX8), y) CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh IMAGE_TYPE := imx8image -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi) endif DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index ceee31eecd7..17de9ff98ec 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -39,7 +39,7 @@ u32 get_imx_reset_cause(void) if (reset_cause == -1) { reset_cause = readl(&src_regs->srsr); /* preserve the value for U-Boot proper */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) writel(reset_cause, &src_regs->srsr); #endif } @@ -47,7 +47,7 @@ u32 get_imx_reset_cause(void) return reset_cause; } -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) static char *get_reset_cause(void) { switch (get_imx_reset_cause()) { @@ -92,7 +92,7 @@ static char *get_reset_cause(void) } #endif -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) const char *get_imx_type(u32 imxtype) { diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 85d90686f68..a8107f46ae5 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -245,7 +245,7 @@ void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset, return ret; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */ @@ -727,7 +727,7 @@ U_BOOT_CMD( "" ); -#endif /* !defined(CONFIG_SPL_BUILD) */ +#endif /* !defined(CONFIG_XPL_BUILD) */ /* Get CSF Header length */ static int get_hab_hdr_len(struct hab_hdr *hdr) @@ -939,7 +939,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, puts("Dumping CSF Header\n"); print_buffer(ivt->csf, (void *)(uintptr_t)(ivt->csf), 4, 0x10, 0); -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) get_hab_status(); #endif @@ -989,7 +989,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, } hab_exit_failure_print_status: -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) get_hab_status(); #endif diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index ed44df394b1..324e010bb2c 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -345,9 +345,9 @@ int ahab_close(void) u16 lc; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in get lifecycle\n"); - return -EIO; + return err; } if (lc != 0x20) { @@ -357,9 +357,9 @@ int ahab_close(void) } err = sc_seco_forward_lifecycle(-1, 16); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in forward lifecycle to OEM closed\n"); - return -EIO; + return err; } return 0; diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 834aca82bcf..37a5473ac7c 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -48,7 +48,7 @@ static char *get_reset_cause(void) { sc_pm_reset_reason_t reason; - if (sc_pm_reset_reason(-1, &reason) != SC_ERR_NONE) + if (sc_pm_reset_reason(-1, &reason)) return "Unknown reset"; switch (reason) { @@ -89,11 +89,11 @@ __weak void reset_cpu(void) int arch_cpu_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) spl_save_restore_data(); #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct pass_over_info_t *pass_over; if (is_soc_rev(CHIP_REV_A)) { @@ -160,6 +160,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) sc_faddr_t tcml_addr; u32 tcml_size = SZ_128K; ulong addr; + int ret; switch (core_id) { case 0: @@ -187,10 +188,12 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Power on M4 and MU\n"); - if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON); + if (ret) + return ret; - if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON); + if (ret) return -EIO; printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr); @@ -199,7 +202,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) memcpy((void *)tcml_addr, (void *)addr, tcml_size); printf("Start M4 %u\n", core_id); - if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE) + ret = sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr); + if (ret) return -EIO; printf("bootaux complete\n"); @@ -214,6 +218,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) sc_faddr_t aux_core_ram; u32 size; ulong addr; + int ret; switch (core_id) { case 0: @@ -242,20 +247,23 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Power on aux core %d\n", core_id); - if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON); + if (ret) + return ret; if (mu_rsrc != SC_R_NONE) { - if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON); + if (ret) return -EIO; } if (core_id == 1) { struct power_domain pd; - if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) { + ret = sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false); + if (ret) { printf("Error enable clock\n"); - return -EIO; + return ret; } if (!imx8_power_domain_lookup_name("audio_sai0", &pd)) { @@ -286,8 +294,9 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); - if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram); + if (ret) + return ret; printf("bootaux complete\n"); return 0; @@ -313,7 +322,7 @@ int arch_auxiliary_core_check_up(u32 core_id) return 0; } - if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE) + if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode)) return 0; if (power_mode != SC_PM_PW_MODE_OFF) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index d1fdaec7043..9d1fabe91c0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -197,6 +197,7 @@ config TARGET_IMX8MP_DEBIX_MODEL_A select IMX8MP select IMX8M_LPDDR4 select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d7fd102c955..d5745f67262 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -51,7 +51,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 43e677deae2..2f53430b4d0 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -611,7 +611,7 @@ void dram_disable_bypass(void) CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void dram_pll_init(ulong pll_val) { u32 val; @@ -791,7 +791,7 @@ int clock_init(void) /* * Dump some clockes. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5293cb85e56..a72329ea919 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -45,7 +45,7 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = { int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); @@ -255,7 +255,7 @@ int dram_init(void) return ret; /* rom_pointer[1] contains the size of TEE occupies */ - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) gd->ram_size = sdram_size - rom_pointer[1]; else gd->ram_size = sdram_size; @@ -284,7 +284,7 @@ int dram_init_banksize(void) } gd->bd->bi_dram[bank].start = PHYS_SDRAM; - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; @@ -329,7 +329,7 @@ phys_size_t get_effective_memsize(void) sdram_b1_size = sdram_size; } - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { /* We will relocate u-boot to Top of dram1. Tee position has two cases: * 1. At the top of dram1, Then return the size removed optee size. @@ -612,7 +612,7 @@ static void early_enable_caches(void) phys_size_t sdram_size; int entry, ret; - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return; if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) @@ -646,7 +646,7 @@ int arch_cpu_init(void) * ROM might disable clock for SCTR, * enable the clock before timer_init. */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) clock_enable(CCGR_SCTR, 1); /* * Init timer at very early state, because sscg pll setting @@ -654,7 +654,7 @@ int arch_cpu_init(void) */ timer_init(); - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { clock_init(); imx_set_wdog_powerdown(false); @@ -1477,7 +1477,7 @@ int arch_misc_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) bool serror_need_skip = true; diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 2c9938fcdf0..b478dab59d0 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -6,6 +6,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += upower/ endif diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index fadf165ece2..c390f20d769 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -519,7 +519,7 @@ u32 get_lpuart_clk(void) return pcc_clock_get_rate(lpuart_pcc[index], lpuart_pcc_slots[index]); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S index 791c26407c9..9ede695dbba 100644 --- a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S +++ b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S @@ -16,7 +16,7 @@ rom_pointer: .global save_boot_params save_boot_params: -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* The firmware provided ATAG/FDT address can be found in r2/x0 */ adr x0, rom_pointer stp x1, x2, [x0], #16 diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index c3722c60836..b5dc45296d1 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -104,7 +104,7 @@ enum bt_mode get_boot_mode(void) bool m33_image_booted(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { u32 gp6 = 0; /* DGO_GP6 */ @@ -124,7 +124,7 @@ bool m33_image_booted(void) bool rdc_enabled_in_boot(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { u32 val = 0; int ret; bool rdc_en = true; /* Default assume DBD_EN is set */ @@ -146,7 +146,7 @@ bool rdc_enabled_in_boot(void) static void spl_pass_boot_info(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { bool m33_booted = m33_image_booted(); bool rdc_en = rdc_enabled_in_boot(); u32 val = 0; @@ -164,7 +164,7 @@ static void spl_pass_boot_info(void) bool is_m33_handshake_necessary(void) { /* Only need handshake in u-boot */ - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) return (m33_image_booted() || rdc_enabled_in_boot()); else return false; @@ -716,7 +716,7 @@ void set_lpav_qos(void) int arch_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* Enable System Reset Interrupt using WDOG_AD */ setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13)); /* Clear AD_PERIPH Power switch domain out of reset interrupt flag */ @@ -805,7 +805,7 @@ int imx8ulp_dm_post_init(void) } EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init); -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index e1b09ab5341..45a9105a75a 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -5,6 +5,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o clock_root.o trdc.o -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD obj-y += imx_bootaux.o #endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 12685f970de..dda57ed7f55 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -640,7 +640,7 @@ void enable_usboh3_clk(unsigned char enable) } } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void dram_pll_init(ulong pll_val) { configure_fracpll(DRAM_PLL_CLK, pll_val); @@ -950,7 +950,7 @@ int set_clk_enet(enum enet_freq type) /* * Dump some clockes. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { u32 freq; diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S index 1dc1dbfcddc..97d85911041 100644 --- a/arch/arm/mach-imx/imx9/lowlevel_init.S +++ b/arch/arm/mach-imx/imx9/lowlevel_init.S @@ -16,7 +16,7 @@ rom_pointer: .global save_boot_params save_boot_params: -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* The firmware provided ATAG/FDT address can be found in r2/x0 */ adr x0, rom_pointer stp x1, x2, [x0], #16 diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 04b21207a28..7c28fa39e14 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -383,7 +383,7 @@ int dram_init(void) return ret; /* rom_pointer[1] contains the size of TEE occupies */ - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) gd->ram_size = sdram_size - rom_pointer[1]; else gd->ram_size = sdram_size; @@ -412,7 +412,7 @@ int dram_init_banksize(void) } gd->bd->bi_dram[bank].start = PHYS_SDRAM; - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; @@ -457,7 +457,7 @@ phys_size_t get_effective_memsize(void) else sdram_b1_size = sdram_size; - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { /* We will relocate u-boot to top of dram1. TEE position has two cases: * 1. At the top of dram1, Then return the size removed optee size. * 2. In the middle of dram1, return the size of dram1. @@ -629,7 +629,7 @@ static int low_drive_freq_update(void *blob) } #ifdef CONFIG_OF_BOARD_FIXUP -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int board_fix_fdt(void *fdt) { /* Update dtb clocks for low drive mode */ @@ -701,7 +701,7 @@ static void save_reset_cause(void) int arch_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* Disable wdog */ init_wdog(); @@ -745,7 +745,7 @@ EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu); int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 0b8a10fd729..41116e2c6a2 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -940,7 +940,7 @@ void mxc_set_sata_internal_clock(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx6/Makefile b/arch/arm/mach-imx/mx6/Makefile index 7ea8f91e4f0..da461b0be9b 100644 --- a/arch/arm/mach-imx/mx6/Makefile +++ b/arch/arm/mach-imx/mx6/Makefile @@ -7,7 +7,7 @@ obj-y := soc.o clock.o obj-$(CONFIG_IMX_MODULE_FUSE) += module_fuse.o -obj-$(CONFIG_SPL_BUILD) += ddr.o +obj-$(CONFIG_XPL_BUILD) += ddr.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_MX6UL_LITESOM) += litesom.o obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index fb9f56d2e63..b5aa606b8d0 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1367,7 +1367,7 @@ void disable_ipu_clock(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 03e1214c060..c6bf933df94 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -78,7 +78,7 @@ int litesom_mmc_init(struct bd_info *bis) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/mx6-ddr.h> diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index 340e6147b63..6a79dcb5bd1 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -79,7 +79,7 @@ int dram_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <asm/arch/mx6-ddr.h> #include <linux/libfdt.h> #include <spl.h> @@ -210,4 +210,4 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 2c0c77e1a56..9b40fe9235a 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -37,7 +37,7 @@ struct scu_regs { u32 fpga_rev; }; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx6_thermal_plat = { .regs = (void *)ANATOP_BASE_ADDR, .fuse_bank = 1, @@ -565,7 +565,7 @@ int board_postclk_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * cfg_val will be used for * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] @@ -600,7 +600,7 @@ const struct boot_mode soc_boot_modes[] = { void reset_misc(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO) lcdif_power_down(); #endif diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index a8606fa9b24..a8328a0b224 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -1100,7 +1100,7 @@ void epdc_clock_disable(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 16c77cbf7be..1b891a2db3d 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -432,7 +432,7 @@ void s_init(void) return; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD const struct boot_mode soc_boot_modes[] = { {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, {"primary", MAKE_CFGVAL_PRIMARY_BOOT}, @@ -450,7 +450,7 @@ int boot_mode_getprisec(void) void reset_misc(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO) lcdif_power_down(); #endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index fb19c62a520..eca92955a17 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -327,7 +327,7 @@ void hab_caam_clock_enable(unsigned char enable) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 198ae2d919c..980e0226156 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -171,7 +171,7 @@ static bool ldo_mode_is_enabled(void) return false; } -#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) +#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_XPL_BUILD)) #if defined(CONFIG_LDO_ENABLED_MODE) static void init_ldo_mode(void) { diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 922f851c56b..96fe2c7c17b 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec) return usec; } -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_SPL_BUILD) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_XPL_BUILD) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile index 1717ca343d6..e2ef88196f8 100644 --- a/arch/arm/mach-k3/am62ax/Makefile +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o -obj-$(CONFIG_SPL_BUILD) += am62a7_init.o +obj-$(CONFIG_XPL_BUILD) += am62a7_init.o diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile index eed91a033eb..3165435f265 100644 --- a/arch/arm/mach-k3/am62px/Makefile +++ b/arch/arm/mach-k3/am62px/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o -obj-$(CONFIG_SPL_BUILD) += am62p5_init.o +obj-$(CONFIG_XPL_BUILD) += am62p5_init.o diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile index 8494cdda482..ca10b6a8d3d 100644 --- a/arch/arm/mach-k3/am62x/Makefile +++ b/arch/arm/mach-k3/am62x/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o -obj-$(CONFIG_SPL_BUILD) += am625_init.o +obj-$(CONFIG_XPL_BUILD) += am625_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile index d0b286276c8..053a8239999 100644 --- a/arch/arm/mach-k3/am64x/Makefile +++ b/arch/arm/mach-k3/am64x/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += am642_init.o +obj-$(CONFIG_XPL_BUILD) += am642_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am65x/Makefile b/arch/arm/mach-k3/am65x/Makefile index 20d5f1d3bf1..34734f24ff7 100644 --- a/arch/arm/mach-k3/am65x/Makefile +++ b/arch/arm/mach-k3/am65x/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o -obj-$(CONFIG_SPL_BUILD) += am654_init.o +obj-$(CONFIG_XPL_BUILD) += am654_init.o diff --git a/arch/arm/mach-k3/arm64/cache.S b/arch/arm/mach-k3/arm64/cache.S index 17cfb12f108..6a507ae3af5 100644 --- a/arch/arm/mach-k3/arm64/cache.S +++ b/arch/arm/mach-k3/arm64/cache.S @@ -7,7 +7,7 @@ #include <config.h> #include <linux/linkage.h> -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) ENTRY(__asm_invalidate_l3_dcache) /* Invalidate SPL address range */ mov x0, #CONFIG_SPL_TEXT_BASE diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile index 982b88db57d..e4b0e5a8193 100644 --- a/arch/arm/mach-k3/j721e/Makefile +++ b/arch/arm/mach-k3/j721e/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o -obj-$(CONFIG_SPL_BUILD) += j721e_init.o +obj-$(CONFIG_XPL_BUILD) += j721e_init.o diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile index ceef68297c9..051ef1b11d8 100644 --- a/arch/arm/mach-k3/j721s2/Makefile +++ b/arch/arm/mach-k3/j721s2/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o -obj-$(CONFIG_SPL_BUILD) += j721s2_init.o +obj-$(CONFIG_XPL_BUILD) += j721s2_init.o diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index 05453fcad41..64c34d3dbd6 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -312,7 +312,7 @@ void do_dt_magic(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { k3_spl_init(); diff --git a/arch/arm/mach-k3/j722s/Makefile b/arch/arm/mach-k3/j722s/Makefile index 2b1fec131ed..9b0dd8afd8b 100644 --- a/arch/arm/mach-k3/j722s/Makefile +++ b/arch/arm/mach-k3/j722s/Makefile @@ -4,4 +4,4 @@ # Jayesh Choudhary <j-choudhary@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j722s_fdt.o -obj-$(CONFIG_SPL_BUILD) += j722s_init.o +obj-$(CONFIG_XPL_BUILD) += j722s_init.o diff --git a/arch/arm/mach-k3/j784s4/Makefile b/arch/arm/mach-k3/j784s4/Makefile index 6d1841e3f9e..1d51bcf6e8c 100644 --- a/arch/arm/mach-k3/j784s4/Makefile +++ b/arch/arm/mach-k3/j784s4/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o -obj-$(CONFIG_SPL_BUILD) += j784s4_init.o +obj-$(CONFIG_XPL_BUILD) += j784s4_init.o diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile index d3886caa064..f533c5e7743 100644 --- a/arch/arm/mach-k3/r5/Makefile +++ b/arch/arm/mach-k3/r5/Makefile @@ -16,6 +16,6 @@ obj-y += common.o obj-y += lowlevel_init.o obj-y += r5_mpu.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 7c46914d9dd..3468a370a45 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -126,7 +126,7 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index 6c7c25090a2..c864317baea 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -10,7 +10,7 @@ obj-y += psc.o obj-y += clock.o obj-y += mon.o CFLAGS_REMOVE_mon.o := $(LTO_CFLAGS) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cmd_clock.o obj-y += cmd_mon.o obj-y += cmd_poweroff.o diff --git a/arch/arm/mach-keystone/config.mk b/arch/arm/mach-keystone/config.mk index 8eccbdb3018..925a2deee23 100644 --- a/arch/arm/mach-keystone/config.mk +++ b/arch/arm/mach-keystone/config.mk @@ -7,7 +7,7 @@ include $(srctree)/arch/arm/mach-omap2/config_secure.mk -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifeq ($(CONFIG_TI_SECURE_DEVICE),y) INPUTS-y += u-boot_HS_MLO else @@ -25,7 +25,7 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE $(call if_changed,pad_cat) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) -n U-Boot MLO: u-boot.bin FORCE diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index b945e19ec77..f99b9fbca2e 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -134,7 +134,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile index 6303570beea..f551abb4772 100644 --- a/arch/arm/mach-lpc32xx/Makefile +++ b/arch/arm/mach-lpc32xx/Makefile @@ -5,4 +5,4 @@ obj-y = cpu.o clk.o devices.o timer.o -obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o +obj-$(CONFIG_XPL_BUILD) += dram.o lowlevel_init.o diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 46bdab88206..3d9e4684fb4 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += cpu.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT7622) += mt7622/ diff --git a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S index 0a0672cbea7..9f19003e43b 100644 --- a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S +++ b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S @@ -16,7 +16,7 @@ ENTRY(lowlevel_init) -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Return to U-Boot via saved link register */ mov pc, lr #else diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 329c2e49153..35fd2d0a1d2 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -22,7 +22,7 @@ else # CONFIG_ARCH_KIRKWOOD obj-y = cpu.o obj-y += dram.o obj-y += lowlevel.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o @@ -110,11 +110,11 @@ $(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ include/config/auto.conf $(call cmd,kwbcfg) -endif # CONFIG_SPL_BUILD +endif # CONFIG_XPL_BUILD obj-y += gpio.o obj-y += mbus.o -obj-$(CONFIG_SPL_BUILD) += spl.o -obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += lowlevel_spl.o obj-$(CONFIG_ARMADA_38X) += serdes/a38x/ obj-$(CONFIG_ARMADA_XP) += serdes/axp/ diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 8a145a5f742..da44727cf4f 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -52,7 +52,7 @@ void lowlevel_init(void) */ } -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) void reset_cpu(void) { struct mvebu_system_registers *reg = @@ -549,7 +549,7 @@ static void ahci_mvebu_mbus_config(void __iomem *base) int i; /* mbus is not initialized in SPL; keep the ROM settings */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return; dram = mvebu_mbus_dram_info(); diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index af6ce2920e6..37a00501214 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -66,7 +66,7 @@ enum cpu_attrib { /* * Default Device Address MAP BAR values */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_ARMADA_38X #define MBUS_PCI_MEM_BASE 0x88000000 #define MBUS_PCI_MEM_SIZE ((3 * 128) << 20) @@ -81,19 +81,19 @@ enum cpu_attrib { #define MBUS_PCI_IO_BASE 0xF1100000 #define MBUS_PCI_IO_SIZE ((MBUS_PCI_MAX_PORTS * 64) << 10) #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define MBUS_SPI_BASE 0xD4000000 #define MBUS_SPI_SIZE (64 << 20) #else #define MBUS_SPI_BASE 0xF4000000 #define MBUS_SPI_SIZE (8 << 20) #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define MBUS_DFX_BASE 0xF6000000 #define MBUS_DFX_SIZE (1 << 20) #endif #define MBUS_BOOTROM_BASE 0xF8000000 -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define MBUS_BOOTROM_SIZE (128 << 20) #else #define MBUS_BOOTROM_SIZE (8 << 20) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index dc68d406f99..495530d8452 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -36,7 +36,7 @@ /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700) +#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARMADA_3700) /* * The SPL U-Boot version still runs with the default * address for the internal registers, configured by diff --git a/arch/arm/mach-mvebu/serdes/a38x/Makefile b/arch/arm/mach-mvebu/serdes/a38x/Makefile index 5a70b375966..c33e272217d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/Makefile +++ b/arch/arm/mach-mvebu/serdes/a38x/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec-38x.o -obj-$(CONFIG_SPL_BUILD) += seq_exec.o -obj-$(CONFIG_SPL_BUILD) += sys_env_lib.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec-38x.o +obj-$(CONFIG_XPL_BUILD) += seq_exec.o +obj-$(CONFIG_XPL_BUILD) += sys_env_lib.o diff --git a/arch/arm/mach-mvebu/serdes/axp/Makefile b/arch/arm/mach-mvebu/serdes/axp/Makefile index 897afb703ad..7d48f8da9ed 100644 --- a/arch/arm/mach-mvebu/serdes/axp/Makefile +++ b/arch/arm/mach-mvebu/serdes/axp/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o +obj-$(CONFIG_XPL_BUILD) = high_speed_env_lib.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec.o diff --git a/arch/arm/mach-nexell/include/mach/display.h b/arch/arm/mach-nexell/include/mach/display.h index b0ee9126057..3a4e2c47f5e 100644 --- a/arch/arm/mach-nexell/include/mach/display.h +++ b/arch/arm/mach-nexell/include/mach/display.h @@ -265,7 +265,7 @@ int dp_plane_set_enable(int module, int layer, int on); int dp_plane_set_address(int module, int layer, unsigned int address); int dp_plane_wait_vsync(int module, int layer, int fps); -#if defined CONFIG_SPL_BUILD || \ +#if defined CONFIG_XPL_BUILD || \ (!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)) int nx_display_probe(struct nx_display_plat *plat); #endif diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d683c64566a..fb5ea97e56e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -11,7 +11,7 @@ obj-y += reset.o ifeq ($(CONFIG_TIMER),) obj-y += timer.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += timer.o endif endif @@ -26,7 +26,7 @@ obj-y += vc.o obj-y += abb.o endif -ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),) +ifeq ($(CONFIG_$(PHASE_)SYS_DCACHE_OFF),) obj-y += omap-cache.o endif diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 3f1af7f1633..6f3587f01d0 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -11,7 +11,7 @@ endif obj-y += sys_info.o obj-y += ddr.o -ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) obj-y += emif4.o endif obj-y += board.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index abdc1e40335..4e9ad8935e3 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -209,7 +209,7 @@ int cpu_mmc_init(struct bd_info *bis) /* AM33XX has two MUSB controllers which can be host or gadget */ #if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ - defined(CONFIG_SPL_BUILD) + defined(CONFIG_XPL_BUILD) static struct musb_hdrc_config musb_config = { .multipoint = 1, @@ -282,7 +282,7 @@ int arch_misc_init(void) #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) + (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) static void rtc32k_unlock(struct davinci_rtc *rtc) { /* @@ -295,7 +295,7 @@ static void rtc32k_unlock(struct davinci_rtc *rtc) } #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) /* * Write contents of the RTC_SCRATCH1 register based on board type * Two things are passed @@ -331,7 +331,7 @@ int board_early_init_f(void) { set_mux_conf_regs(); prcm_init(); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) update_rtc_magic(); #endif return 0; @@ -379,7 +379,7 @@ static void watchdog_disable(void) ; } -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) /* * Check if we are executing rtc-only + DDR mode, and resume from it if needed */ @@ -455,7 +455,7 @@ am43xx_wait: void s_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) rtc_only(); #endif } @@ -474,7 +474,7 @@ void early_system_init(void) set_uart_mux_conf(); setup_early_clocks(); uart_soft_reset(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, @@ -483,7 +483,7 @@ void early_system_init(void) save_omap_boot_params(); #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD spl_early_init(); #endif @@ -497,7 +497,7 @@ void early_system_init(void) #endif } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { hw_data_init(); @@ -526,7 +526,7 @@ EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init); #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { - if (u_boot_first_phase()) { + if (xpl_is_first_phase()) { hw_data_init(); set_uart_mux_conf(); setup_early_clocks(); diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 649bc07047a..ddd7eeaf052 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -173,7 +173,7 @@ void save_omap_boot_params(void) #endif } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 spl_boot_device(void) { return gd->arch.omap_boot_device; @@ -208,7 +208,7 @@ void spl_boot_ipu(void) int ret, size; u32 loadaddr = IPU1_LOAD_ADDR; - if (!IS_ENABLED(CONFIG_SPL_BUILD) || + if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) return; @@ -286,7 +286,7 @@ void spl_soc_init(void) #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) hw_watchdog_init(); #endif - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) spl_boot_ipu(); } diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 18d099145c5..f05b16797ec 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -24,7 +24,7 @@ #include <asm/omap_gpio.h> #include <asm/emif.h> -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * printing to console doesn't work unless * this code is executed from SPL diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk index 30d8fb1b1d9..02b26733ee6 100644 --- a/arch/arm/mach-omap2/config.mk +++ b/arch/arm/mach-omap2/config.mk @@ -5,7 +5,7 @@ include $(srctree)/arch/arm/mach-omap2/config_secure.mk -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifeq ($(CONFIG_TI_SECURE_DEVICE),y) # Refer to README.ti-secure for more info # On DRA7xx/AM57xx: # diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index 40db1aec142..62ac27dfa90 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -4,7 +4,7 @@ quiet_cmd_mkomapsecimg = SECURE $@ ifneq ($(TI_SECURE_DEV_PKG),) ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),) -ifneq ($(CONFIG_SPL_BUILD),) +ifneq ($(CONFIG_XPL_BUILD),) cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_SPL_TEXT_BASE) \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index bb67e50fd56..b1e486a99d9 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -113,7 +113,7 @@ static void omap_rev_string(void) puts("\n"); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_display_print(void) { omap_rev_string(); @@ -175,7 +175,7 @@ void __weak init_package_revision(void) */ int early_system_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) int ret; int rescan; #endif @@ -183,19 +183,19 @@ int early_system_init(void) hw_data_init(); init_package_revision(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD if (warm_reset()) force_emif_self_refresh(); #endif watchdog_init(); set_mux_conf_regs(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD srcomp_enable(); do_io_settings(); #endif setup_early_clocks(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, @@ -206,7 +206,7 @@ int early_system_init(void) #endif do_board_detect(); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) /* * Board detection has been done. * Let us see if another dtb wouldn't be a better match @@ -228,7 +228,7 @@ int early_system_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { early_system_init(); diff --git a/arch/arm/mach-omap2/omap3/Makefile b/arch/arm/mach-omap2/omap3/Makefile index 151bdf6ebc9..159633e7f6d 100644 --- a/arch/arm/mach-omap2/omap3/Makefile +++ b/arch/arm/mach-omap2/omap3/Makefile @@ -15,7 +15,7 @@ obj-y += clock.o obj-y += sys_info.o obj-y += prcm-regs.o obj-y += hw_data.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o endif diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 1de343ff48e..4b6ce6940a9 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -211,7 +211,7 @@ void s_init(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { early_system_init(); @@ -280,7 +280,7 @@ void abort(void) { } -#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_XPL_BUILD) /****************************************************************************** * OMAP3 specific command to switch between NAND HW and SW ecc *****************************************************************************/ @@ -331,7 +331,7 @@ U_BOOT_CMD( "nandecc sw - Switch to NAND software ecc algorithm." ); -#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ +#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_XPL_BUILD */ #ifdef CONFIG_DISPLAY_BOARDINFO /** diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 404333689f6..24fae484369 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -146,7 +146,7 @@ static void do_sdrc_init(u32 cs, u32 early) * then set cs_cfg to the appropriate value then try and * setup CS1. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* set/modify board-specific timings */ get_board_mem_timings(&timings); #endif @@ -166,7 +166,7 @@ static void do_sdrc_init(u32 cs, u32 early) writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD write_sdrc_timings(CS0, sdrc_actim_base0, &timings); make_cs1_contiguous(); write_sdrc_timings(CS1, sdrc_actim_base1, &timings); diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 7f41e85c4a6..42f9c63fe12 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -50,7 +50,7 @@ void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) writel(pad->val, base + pad->offset); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* LPDDR2 specific IO settings */ static void io_settings_lpddr2(void) { diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 16bbc93f4a3..b1d11a4d1a4 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -178,7 +178,7 @@ auth_exit: * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index a8b87f6d710..3c381dedaf8 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -11,13 +11,13 @@ obj-y = cpu.o obj-y += dram.o obj-y += timer.o -ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT +ifndef CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index 58ee67eca50..4eba69a6909 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -235,7 +235,7 @@ int arch_cpu_init(void) /* Enable and invalidate L2 cache in write through mode */ invalidate_l2_cache(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD orion5x_config_adr_windows(); #endif diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index aa3fcf7c301..358d2a49fbb 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -69,7 +69,7 @@ lowlevel_init: -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Use 'r2 as the base for internal register accesses */ ldr r2, =ORION5X_REGS_PHY_BASE @@ -280,7 +280,7 @@ lowlevel_init: ldr r0, =0x7fff0001 str r0, [r3, #0x504] -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* Return to U-Boot via saved link register */ mov pc, lr diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index 1d8c3eea99c..fe88a2e0373 100644 --- a/arch/arm/mach-renesas/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h @@ -9,7 +9,7 @@ _start: ARM_VECTORS -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .word 0x0badc0d3; .word 0x0badc0d3; .word 0x0badc0d3; diff --git a/arch/arm/mach-renesas/lowlevel_init_ca15.S b/arch/arm/mach-renesas/lowlevel_init_ca15.S index 059cd738785..ecefa3d5c43 100644 --- a/arch/arm/mach-renesas/lowlevel_init_ca15.S +++ b/arch/arm/mach-renesas/lowlevel_init_ca15.S @@ -11,7 +11,7 @@ #include <system-constants.h> ENTRY(lowlevel_init) -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD mrc p15, 0, r4, c0, c0, 5 /* mpidr */ orr r4, r4, r4, lsr #6 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 3b13891ec24..5e7edc99cdc 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -15,7 +15,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) # Always include boot_mode.o, as we bypass it (i.e. turn it off) # inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way, @@ -29,7 +29,7 @@ ifeq ($(CONFIG_TPL_BUILD),) obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o endif -obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o +obj-$(CONFIG_$(PHASE_)RAM) += sdram.o obj-$(CONFIG_ROCKCHIP_PX30) += px30/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ @@ -51,5 +51,5 @@ obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/ obj-spl-$(CONFIG_TPL_BUILD) = # Now add SPL/TPL objects back into the main build -obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y) +obj-$(CONFIG_XPL_BUILD) += $(obj-spl-y) obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y) diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8b1509e55f2..8ce9ac561f0 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -244,7 +244,7 @@ int arch_cpu_init(void) static struct px30_cru * const cru = (void *)CRU_BASE; u32 __maybe_unused val; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* We do some SoC one time setting here. */ /* Disable the ddr secure region setting to make it non-secure */ writel(0x0, DDR_FW_BASE + FW_DDR_CON); diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 299fc50635d..038180c275c 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -6,7 +6,7 @@ obj-y += clk_rk3036.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += syscon_rk3036.o endif diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 70b55ca8abf..b8c177a4d0d 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -27,7 +27,7 @@ void board_debug_uart_init(void) void spl_board_init(void) { - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) return; if (IS_ENABLED(CONFIG_SPL_DM_MMC)) { diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 53b2eaa2d53..7cce1112fbd 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -51,7 +51,7 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int arch_cpu_init(void) { struct rk3188_grf *grf; @@ -106,7 +106,7 @@ int rk_board_late_init(void) return rk3188_board_late_init(); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static int setup_led(void) { #ifdef CONFIG_SPL_LED diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index 712c0524266..e35ca7778e7 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -51,7 +51,7 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SGRF_BASE 0x10150000 static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE; diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index d1170f7e23d..62dd9da6578 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -31,7 +31,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void configure_l2ctlr(void) { u32 l2ctlr; @@ -72,7 +72,7 @@ int rk3288_qos_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD configure_l2ctlr(); #else /* We do some SoC one time setting here. */ diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 6f88638d156..c6b1a35f47e 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -185,7 +185,7 @@ __weak void board_debug_uart_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) int arch_cpu_init(void) { static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE; diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index c86d11943d6..12ad17d9e8b 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -62,7 +62,7 @@ struct mm_region *mem_map = rk3328_mem_map; int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 reg; /* We do some SoC one time setting here. */ diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index f589bf67328..97b9500da25 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -93,7 +93,7 @@ int arch_early_init_r(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * The SPL (and also the full U-Boot stage on the RK3368) will run in * secure mode (i.e. EL3) and an ATF will eventually be booted before diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 2d7d0f82a2f..edccb2a3980 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -51,7 +51,7 @@ static struct mm_region rk3399_mem_map[] = { struct mm_region *mem_map = rk3399_mem_map; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define TIMER_END_COUNT_L 0x00 #define TIMER_END_COUNT_H 0x04 @@ -83,7 +83,7 @@ void rockchip_stimer_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct rk3399_pmusgrf_regs *sgrf; struct rk3399_grf_regs *grf; @@ -136,7 +136,7 @@ void board_debug_uart_init(void) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { rk_setreg(&grf->io_vsel, 1 << 0); @@ -169,7 +169,7 @@ void board_debug_uart_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) static void rk3399_force_power_on_reset(void) { ofnode node; diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 1b3e40074e3..768a3739329 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -105,7 +105,7 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * When perform idle operation, corresponding clock can * be opened or gated automatically. diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index d3162d3447e..e2dac2a5b80 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -111,7 +111,7 @@ void board_debug_uart_init(void) GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void rockchip_stimer_init(void) { /* If Timer already enabled, don't re-init it */ @@ -130,7 +130,7 @@ void rockchip_stimer_init(void) #ifndef CONFIG_TPL_BUILD int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE; #endif diff --git a/arch/arm/mach-rockchip/rv1108/Makefile b/arch/arm/mach-rockchip/rv1108/Makefile index 9035a1a8923..283fc966e7b 100644 --- a/arch/arm/mach-rockchip/rv1108/Makefile +++ b/arch/arm/mach-rockchip/rv1108/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += syscon_rv1108.o endif obj-y += rv1108.o diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index 1c10e9b9f23..27ed5dc19e1 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -66,7 +66,7 @@ int arch_cpu_init(void) * since they are unsecure. * (Note: only secure-world can access this register) */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG); return 0; diff --git a/arch/arm/mach-sc5xx/Makefile b/arch/arm/mach-sc5xx/Makefile index cac768ba565..47b28200a03 100644 --- a/arch/arm/mach-sc5xx/Makefile +++ b/arch/arm/mach-sc5xx/Makefile @@ -19,5 +19,5 @@ obj-$(CONFIG_SC59X) += sc59x-spl.o obj-$(CONFIG_SC59X_64) += sc59x_64.o obj-$(CONFIG_SC59X_64) += sc59x_64-spl.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_SYSCON) += rcu.o diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk index 580964e559c..e7e4c9a1181 100644 --- a/arch/arm/mach-sc5xx/config.mk +++ b/arch/arm/mach-sc5xx/config.mk @@ -8,7 +8,7 @@ # Contact: Greg Malysa <greg.malysa@timesys.com> # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD INPUTS-y += $(obj)/u-boot-spl.ldr endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec5..5fc61b4a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -80,7 +80,7 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o obj-y += freeze_controller.o diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index feaf5ce4596..24a15f7903f 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -102,7 +102,7 @@ u8 socfpga_get_board_id(void) u32 jtag_usercode; int err; -#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) +#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) err = smc_get_usercode(&jtag_usercode); #else u32 resp_len = 1; @@ -130,7 +130,7 @@ u8 socfpga_get_board_id(void) return board_id; } -#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) int board_fit_config_name_match(const char *name) { char board_name[10]; @@ -154,7 +154,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, } #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT) +#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_FIT) void board_prep_linux(struct bootm_headers *images) { bool use_fit = false; diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 160f6e73ca9..134eaf08e0a 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -99,7 +99,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 58b9321131a..5674194f4d1 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -12,7 +12,7 @@ #include <asm/arch/clock_manager.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void sdelay(unsigned long loops); u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h index c78def5066e..2676d6c8283 100644 --- a/arch/arm/mach-socfpga/include/mach/boot0.h +++ b/arch/arm/mach-socfpga/include/mach/boot0.h @@ -9,7 +9,7 @@ _start: ARM_VECTORS -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .balignl 64,0xf33db33f; .word 0x1337c0d3; /* SoCFPGA preloader validation word */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h index 553ebe660de..80d5047b469 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -62,7 +62,7 @@ #define CLKMGR_INTER CLKMGR_A10_INTER #define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int cm_basic_init(const void *blob); #endif diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 875927cc4d9..8926c2d1d9c 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -13,7 +13,7 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 4c86f1e9917..2b4f26040fe 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -400,7 +400,7 @@ error: int mbox_reset_cold(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) psci_system_reset(); #else int ret; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 495ba2a0d41..46f9c82bbb2 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -180,7 +180,7 @@ int arch_cpu_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 34c21317894..c442af02888 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -58,7 +58,7 @@ static Altera_desc altera_fpga[] = { }, }; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) static struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index b898b6f8f22..b136691c685 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -213,7 +213,7 @@ int arch_early_init_r(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index dd0383c7c76..a634c11a028 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -58,7 +58,7 @@ void socfpga_per_reset_all(void) void socfpga_bridges_reset(int enable) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) u64 arg = enable; int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index 4347bf6e792..e931f1043b3 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -120,7 +120,7 @@ int socfpga_vendor_authentication(void **p_image, size_t *p_size) debug("mbox_relocate_data_addr = 0x%p\n", mbox_relocate_data_addr); do { - if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { /* Invoke SMC call to ATF to send the VAB certificate to SDM */ ret = smc_send_mailbox(MBOX_VAB_SRC_CERT, mbox_data_sz, (u32 *)mbox_relocate_data_addr, 0, &resp_len, diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 80933586319..1a4e7c0e7e2 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -14,7 +14,7 @@ */ int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int enable = 0x3; /* timer enable + output signal masked */ int loadval = ~0; @@ -56,4 +56,4 @@ __always_inline void __udelay(unsigned long usec) while (__get_time_stamp() < tmp + 1) /* loop till event */ ; -}
\ No newline at end of file +} diff --git a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c index f13581033e6..60ba557d390 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c @@ -11,7 +11,7 @@ const struct cm_config * const cm_get_default_config(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct cm_config *cm_handoff_cfg = (struct cm_config *) (SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA); u32 *conversion = (u32 *)cm_handoff_cfg; @@ -32,7 +32,7 @@ const struct cm_config * const cm_get_default_config(void) const unsigned int cm_get_osc_clk_hz(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC); @@ -50,7 +50,7 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA); writel(clock, diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index ee8a5428feb..db7ed19bd91 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_STM32MP13X) += stm32mp1/ obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cmd_stm32prog/ obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o obj-$(CONFIG_TFABOOT) += boot_params.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 9ba7a6c9a89..9cbe6a52623 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -409,7 +409,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) u32 tmp_data = 0; int ret; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_OTP, otp, 0, val); @@ -440,7 +440,7 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_SHADOW, otp, 0, val); @@ -469,7 +469,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_PROG_OTP, otp, val); @@ -484,7 +484,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRITE_SHADOW, otp, val); @@ -504,7 +504,7 @@ static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) return 0; /* nothing to do */ } - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRLOCK_OTP, otp, 0); @@ -762,7 +762,7 @@ static int stm32mp_bsec_probe(struct udevice *dev) * update unlocked shadow for OTP cleared by the rom code * only executed in SPL, it is done in TF-A for TFABOOT */ - if (IS_ENABLED(CONFIG_SPL_BUILD) && !data->ta) { + if (IS_ENABLED(CONFIG_XPL_BUILD) && !data->ta) { plat = dev_get_plat(dev); /* here 57 is the value for STM32MP15x ROM code, only MPU with SPL support*/ diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index ebae50f66c9..db160c24cbc 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -8,12 +8,12 @@ obj-y += cpu.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += tzc400.o else obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_$(XPL_)STM32MP15_PWR) += pwr_regulator.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 64480da9f8d..26c073f06a0 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -57,7 +57,7 @@ void dram_bank_mmu_setup(int bank) bool use_lmb = false; enum dcache_option option; - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* STM32_SYSRAM_BASE exist only when SPL is supported */ #ifdef CONFIG_SPL start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); @@ -133,7 +133,7 @@ int mach_cpu_init(void) if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; - else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) + else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD)) debug_uart_init(); return 0; @@ -339,7 +339,7 @@ uintptr_t get_stm32mp_bl2_dtb(void) return nt_fw_dtb; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index ca202bec8ee..4f1d783649b 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -214,13 +214,13 @@ static void update_bootmode(void) /* weak function: STM32MP15x mach init for boot without TFA */ void stm32mp_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { security_init(); update_bootmode(); } /* reset copro state in SPL, when used, or in U-Boot */ - if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_XPL_BUILD)) { /* Reset Coprocessor state unless it wakes up from Standby power mode */ if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 17666814c52..8065161e61e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -108,6 +108,23 @@ config DRAM_SUN50I_H616_TPR12 default 0x0 help TPR12 value from vendor DRAM settings. + +choice + prompt "H616 PHY pin mapping selection" + default DRAM_SUN50I_H616_PHY_ADDR_MAP_0 + +config DRAM_SUN50I_H616_PHY_ADDR_MAP_0 + bool "H313/H616/H618" + help + The pin mapping selection used by the H313, H616, H618, and + possibly other dies which use the H616 DRAM controller. + +config DRAM_SUN50I_H616_PHY_ADDR_MAP_1 + bool "H700" + help + The pin mapping selection used by the H700 and possibly other + dies which use the H616 DRAM controller. +endchoice endif config SUN6I_PRCM @@ -437,6 +454,7 @@ config MACH_SUN50I_H616 select ARM64 select DRAM_SUN50I_H616 select SUN50I_GEN_H6 + imply OF_UPSTREAM endchoice diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 3f83c0280ef..eb6a49119a1 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -29,7 +29,7 @@ ifndef CONFIG_ARM64 obj-y += timer.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += clock.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 2b64ddc0dc7..701899ee4b2 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -74,7 +74,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) } #endif /* CONFIG_ARM64 */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static int gpio_init(void) { __maybe_unused uint val; @@ -209,7 +209,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image, return 0; } SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define SUNXI_INVALID_BOOT_SOURCE -1 @@ -258,7 +258,7 @@ static int sunxi_get_boot_source(void) * proper, just return MMC0 as a placeholder, for now. */ if (IS_ENABLED(CONFIG_MACH_SUNIV) && - !IS_ENABLED(CONFIG_SPL_BUILD)) + !IS_ENABLED(CONFIG_XPL_BUILD)) return SUNXI_BOOTED_FROM_MMC0; if (IS_ENABLED(CONFIG_MACH_SUNIV)) @@ -314,7 +314,7 @@ uint32_t sunxi_get_boot_device(void) return -1; /* Never reached */ } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD uint32_t sunxi_get_spl_size(void) { struct boot_file_head *egon_head = (void *)SPL_ADDR; @@ -478,7 +478,7 @@ void board_init_f(ulong dummy) #endif sunxi_board_init(); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 6458d066f7e..1367b439b83 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -13,7 +13,7 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -175,7 +175,7 @@ void clock_set_pll1(unsigned int hz) &ccm->cpu_ahb_apb0_cfg); sdelay(20); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index cc2ee336416..b424a7893ea 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -3,7 +3,7 @@ #include <asm/arch/clock.h> #include <asm/arch/prcm.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = @@ -131,7 +131,7 @@ int clock_twi_onoff(int port, int state) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* PLL_PERIPH0 clock, used by the MMC driver */ unsigned int clock_get_pll6(void) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 59f7e15ffe8..657736c7ac2 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -16,7 +16,7 @@ #include <linux/bitops.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -169,7 +169,7 @@ void clock_set_pll1(unsigned int clk) &ccm->cpu_axi_cfg); } } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index c00d16a918d..f593749028c 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -15,7 +15,7 @@ #include <asm/arch/sys_proto.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -100,7 +100,7 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ void clock_set_pll5(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index abdab405445..5f99071f21b 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -14,7 +14,7 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void clock_set_pll2(unsigned int clk) { @@ -188,7 +188,7 @@ int clock_twi_onoff(int port, int state) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* PLL_PERIPH0 clock (used by the MMC driver) */ unsigned int clock_get_pll4_periph0(void) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 37c139e0eea..863c4f1d7a8 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -55,8 +55,8 @@ static void mbus_configure_port(u8 port, writel_relaxed(cfg1, &mctl_com->master[port].cfg1); } -#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \ - mbus_configure_port(port, bwlimit, false, \ +#define MBUS_CONF(port, priority, qos, acs, bwl0, bwl1, bwl2) \ + mbus_configure_port(port, true, priority, \ MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2) static void mctl_set_master_priority(void) @@ -68,24 +68,25 @@ static void mctl_set_master_priority(void) writel(399, &mctl_com->tmr); writel(BIT(16), &mctl_com->bwcr); - MBUS_CONF( 0, true, HIGHEST, 0, 256, 128, 100); - MBUS_CONF( 1, true, HIGH, 0, 1536, 1400, 256); - MBUS_CONF( 2, true, HIGHEST, 0, 512, 256, 96); - MBUS_CONF( 3, true, HIGH, 0, 256, 100, 80); - MBUS_CONF( 4, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF( 5, true, HIGH, 2, 100, 64, 32); - MBUS_CONF( 6, true, HIGH, 2, 100, 64, 32); - MBUS_CONF( 8, true, HIGH, 0, 256, 128, 64); - MBUS_CONF(11, true, HIGH, 0, 256, 128, 100); - MBUS_CONF(14, true, HIGH, 0, 1024, 256, 64); - MBUS_CONF(16, true, HIGHEST, 6, 8192, 2800, 2400); - MBUS_CONF(21, true, HIGHEST, 6, 2048, 768, 512); - MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32); - MBUS_CONF(26, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF(37, true, HIGH, 0, 256, 128, 64); - MBUS_CONF(38, true, HIGH, 2, 100, 64, 32); - MBUS_CONF(39, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF(40, true, HIGH, 2, 100, 64, 32); + MBUS_CONF(0, false, HIGHEST, 0, 256, 128, 100); + MBUS_CONF(1, false, HIGH, 0, 1536, 1400, 256); + MBUS_CONF(2, false, HIGHEST, 0, 512, 256, 96); + MBUS_CONF(3, false, HIGH, 0, 256, 100, 80); + MBUS_CONF(4, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(5, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(6, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(8, false, HIGH, 0, 256, 128, 64); + MBUS_CONF(11, false, HIGH, 0, 256, 128, 100); + MBUS_CONF(14, false, HIGH, 0, 1024, 256, 64); + MBUS_CONF(16, false, HIGHEST, 6, 8192, 2800, 2400); + MBUS_CONF(21, false, HIGHEST, 6, 2048, 768, 512); + MBUS_CONF(22, false, HIGH, 0, 256, 128, 100); + MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32); + MBUS_CONF(26, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(37, false, HIGH, 0, 256, 128, 64); + MBUS_CONF(38, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(39, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(40, false, HIGH, 2, 100, 64, 32); dmb(); } @@ -225,6 +226,26 @@ static void mctl_set_addrmap(const struct dram_config *config) mctl_ctl->addrmap[8] = 0x3F3F; } +#ifdef CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1 +static const u8 phy_init[] = { +#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 + 0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b, + 0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a, + 0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19, + 0x06, 0x09, 0x0f +#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3) + 0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19, + 0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07, + 0x08, 0x01, 0x1a +#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4) + 0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01, + 0x18, 0x04, 0x1a +#endif +}; +#else /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */ static const u8 phy_init[] = { #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19, @@ -243,7 +264,7 @@ static const u8 phy_init[] = { 0x18, 0x03, 0x1a #endif }; - +#endif /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */ #define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f) static void mctl_phy_configure_odt(const struct dram_para *para) { @@ -293,14 +314,22 @@ static void mctl_phy_configure_odt(const struct dram_para *para) dmb(); } -static bool mctl_phy_write_leveling(const struct dram_config *config) +static bool mctl_phy_write_leveling(const struct dram_para *para, + const struct dram_config *config) { bool result = true; u32 val; clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0, 0x80); - writel(4, SUNXI_DRAM_PHY0_BASE + 0xc); - writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + /* MR2 value */ + writel(0x1b, SUNXI_DRAM_PHY0_BASE + 0xc); + writel(0, SUNXI_DRAM_PHY0_BASE + 0x10); + } else { + writel(4, SUNXI_DRAM_PHY0_BASE + 0xc); + writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10); + } setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4); @@ -859,9 +888,9 @@ static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para, } break; case SUNXI_DRAM_TYPE_LPDDR4: - if (para->tpr2 & 1) { - writel(val, SUNXI_DRAM_PHY0_BASE + 0x788); - } else { + writel(val, SUNXI_DRAM_PHY0_BASE + 0x788); + if (config->ranks == 2) { + val = (para->tpr10 >> 11) & 0x1e; writel(val, SUNXI_DRAM_PHY0_BASE + 0x794); }; break; @@ -986,12 +1015,16 @@ static bool mctl_phy_init(const struct dram_para *para, clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0, 0x20); } + clrbits_le32(&mctl_com->unk_0x500, 0x200); + udelay(1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8); mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4); + udelay(1000); + writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58); - clrbits_le32(&mctl_com->unk_0x500, 0x200); writel(0, &mctl_ctl->swctl); setbits_le32(&mctl_ctl->dfimisc, 1); @@ -1010,6 +1043,8 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->swstat, 1, 1); mctl_await_completion(&mctl_ctl->statr, 3, 1); + udelay(200); + writel(0, &mctl_ctl->swctl); clrbits_le32(&mctl_ctl->dfimisc, 1); @@ -1080,19 +1115,27 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xb04, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xc72, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xe09, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0x1624, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); break; case SUNXI_DRAM_TYPE_DDR4: @@ -1108,7 +1151,7 @@ static bool mctl_phy_init(const struct dram_para *para, if (para->tpr10 & TPR10_WRITE_LEVELING) { for (i = 0; i < 5; i++) - if (mctl_phy_write_leveling(config)) + if (mctl_phy_write_leveling(para, config)) break; if (i == 5) { debug("write leveling failed!\n"); @@ -1234,9 +1277,6 @@ static bool mctl_ctrl_init(const struct dram_para *para, setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30)); setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30)); - if (para->type == SUNXI_DRAM_TYPE_LPDDR4) - setbits_le32(&mctl_ctl->dbictl, 0x1); - setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); @@ -1248,8 +1288,10 @@ static bool mctl_ctrl_init(const struct dram_para *para, setbits_le32(&mctl_ctl->clken, BIT(8)); clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x300); + udelay(1); /* this write seems to enable PHY MMIO region */ setbits_le32(&mctl_com->unk_0x500, BIT(24)); + udelay(1); if (!mctl_phy_init(para, config)) return false; @@ -1321,28 +1363,33 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para, static void mctl_auto_detect_dram_size(const struct dram_para *para, struct dram_config *config) { - /* detect row address bits */ - config->cols = 8; - config->rows = 18; + unsigned int shift; + + /* max. config for columns, but not rows */ + config->cols = 11; + config->rows = 13; mctl_core_init(para, config); - for (config->rows = 13; config->rows < 18; config->rows++) { - /* 8 banks, 8 bit per byte and 16/32 bit width */ - if (mctl_mem_matches((1 << (config->rows + config->cols + - 4 + config->bus_full_width)))) + shift = config->bus_full_width + 1; + + /* detect column address bits */ + for (config->cols = 8; config->cols < 11; config->cols++) { + if (mctl_mem_matches(1ULL << (config->cols + shift))) break; } + debug("detected %u columns\n", config->cols); - /* detect column address bits */ - config->cols = 11; + /* reconfigure to make sure that all active rows are accessible */ + config->rows = 18; mctl_core_init(para, config); - for (config->cols = 8; config->cols < 11; config->cols++) { - /* 8 bits per byte and 16/32 bit width */ - if (mctl_mem_matches(1 << (config->cols + 1 + - config->bus_full_width))) + /* detect row address bits */ + shift = config->bus_full_width + 4 + config->cols; + for (config->rows = 13; config->rows < 18; config->rows++) { + if (mctl_mem_matches(1ULL << (config->rows + shift))) break; } + debug("detected %u rows\n", config->rows); } static unsigned long mctl_calc_size(const struct dram_config *config) diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c index e6446b9180d..6f5c4acbd62 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c @@ -23,7 +23,7 @@ void mctl_set_timing_params(const struct dram_para *para) u8 trcd = max(ns_to_t(18), 2); u8 trc = ns_to_t(65); u8 txp = max(ns_to_t(8), 2); - u8 trtp = max(ns_to_t(8), 4); + u8 trtp = 4; u8 trp = ns_to_t(21); u8 tras = ns_to_t(42); u16 trefi = ns_to_t(3904) / 32; diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c index a058fea6bef..aa93defb25e 100644 --- a/arch/arm/mach-sunxi/gtbus_sun9i.c +++ b/arch/arm/mach-sunxi/gtbus_sun9i.c @@ -11,7 +11,7 @@ #include <asm/arch/gtbus_sun9i.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void gtbus_init(void) { diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 1d22dc3942f..ebac3473a1f 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -5,7 +5,7 @@ # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += cpu.o else @@ -16,7 +16,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o -obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o +obj-$(CONFIG_$(XPL_)TEGRA_CRYPTO) += crypto.o obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o @@ -25,7 +25,7 @@ obj-y += dt-setup.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_IVC) += ivc.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 1ea620e4ab5..f35bdba4d48 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -32,7 +32,7 @@ int tegra_get_chip(void) * Tegra30, 0x35 for T114, and 0x40 for Tegra124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - debug("%s: CHIPID is 0x%02X\n", __func__, rev); + debug("%s: CHIPID is 0x%02x\n", __func__, rev); return rev; } @@ -43,7 +43,7 @@ int tegra_get_sku_info(void) struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; sku_id = readl(&fuse->sku_info) & 0xff; - debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); + debug("%s: SKU info byte is 0x%02x\n", __func__, sku_id); return sku_id; } @@ -58,8 +58,9 @@ int tegra_get_chip_sku(void) switch (chip_id) { case CHIPID_TEGRA20: switch (sku_id) { - case SKU_ID_T20_7: + case SKU_ID_AP20: case SKU_ID_T20: + case SKU_ID_AP20H: return TEGRA_SOC_T20; case SKU_ID_T25SE: case SKU_ID_AP25: @@ -103,8 +104,8 @@ int tegra_get_chip_sku(void) } /* unknown chip/sku id */ - printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", - __func__, chip_id, sku_id); + printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02x/0x%02x)\n", + __func__, chip_id, sku_id); return TEGRA_SOC_UNKNOWN; } diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index c382e042860..7ca56a3b081 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -47,7 +47,7 @@ enum { static bool from_spl __section(".data"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, unsigned long r3) { @@ -181,7 +181,7 @@ static int uart_configs[] = { -1, -1, -1, - -1, + FUNCMUX_UART5_SDMMC1, /* UARTE */ #elif defined(CONFIG_TEGRA114) -1, -1, diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 5c5838629b2..6e9ef68caf9 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -6,6 +6,7 @@ #include <config.h> #include <dm.h> +#include <dm/root.h> #include <env.h> #include <errno.h> #include <init.h> @@ -46,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ U_BOOT_DRVINFO(tegra_gpios) = { "gpio_tegra" @@ -457,3 +458,18 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } + +#if IS_ENABLED(CONFIG_DTB_RESELECT) +int embedded_dtb_select(void) +{ + int ret, rescan; + + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(true); + } + + return 0; +} +#endif diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index 346d6cb5696..f1c1042b4e2 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -2,6 +2,6 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -obj-$(CONFIG_SPL_BUILD) += cpu.o +obj-$(CONFIG_XPL_BUILD) += cpu.o obj-y += clock.o diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index fb016aa46c9..84c8f86bad0 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -21,8 +21,8 @@ config TARGET_CEI_TK1_SOM bool "Colorado Engineering Inc Tegra124 TK1-som board" select ARCH_SUPPORT_PSCI select BOARD_LATE_INIT - select CPU_V7_HAS_NONSEC if !SPL_BUILD - select CPU_V7_HAS_VIRT if !SPL_BUILD + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT help The Colorado Engineering Tegra TK1-SOM is a very compact (51mmx58mm) board that is functionally almost the same as diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index 6ea511e7b25..dee790015a3 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -5,13 +5,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SPL_BUILD) += cpu.o +obj-$(CONFIG_XPL_BUILD) += cpu.o obj-y += clock.o obj-y += pmc.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_NONSEC) += psci.o endif diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index c2ae98eb376..32c1866b099 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -2,8 +2,8 @@ # # (C) Copyright 2010,2011 Nvidia Corporation. -obj-$(CONFIG_SPL_BUILD) += cpu.o -obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o +obj-$(CONFIG_XPL_BUILD) += cpu.o +obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index ee0e6f5b948..b36657a432f 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -2,7 +2,7 @@ # # Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -obj-$(CONFIG_SPL_BUILD) += cpu.o -obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o +obj-$(CONFIG_XPL_BUILD) += cpu.o +obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o obj-y += clock.o diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5172efac0c4..d1ec8195dcb 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += boards.o obj-y += spl_board_init.o diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile index b41aba7e29a..c8ce67ac05a 100644 --- a/arch/arm/mach-uniphier/arm32/Makefile +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += lowlevel_init.o obj-$(CONFIG_DEBUG_LL) += debug_ll.o else diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 1e6bc8433f7..9d0fe5c8583 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -214,7 +214,7 @@ int uniphier_boot_from_backend(void) return !!(readl(sg_base + SG_PINMON0) & BIT(27)); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_pinmon(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -267,4 +267,4 @@ U_BOOT_CMD( "" ); -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index c49e44754c0..0e47beb5f22 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile b/arch/arm/mach-uniphier/debug-uart/Makefile index 81e9314a50d..4202cb3503b 100644 --- a/arch/arm/mach-uniphier/debug-uart/Makefile +++ b/arch/arm/mach-uniphier/debug-uart/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index 1ba012ca45d..6836eb63bfa 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -26,7 +26,7 @@ static void _debug_uart_putc(int c) writel(c, base + UNIPHIER_UART_TX); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void sg_set_pinsel(unsigned int pin, unsigned int muxval, unsigned int mux_bits, unsigned int reg_stride) { @@ -56,7 +56,7 @@ void sg_set_iectrl(unsigned int pin) void _debug_uart_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); unsigned int divisor; diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 7d11315d07f..36188c38cf9 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \ ddrphy-training.o ddrphy-ld4.o diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index d9b2b999e10..8545331c54a 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -12,4 +12,4 @@ obj-y += slcr.o obj-y += clk.o obj-y += lowlevel_init.o AFLAGS_lowlevel_init.o := -mfpu=neon -obj-$(CONFIG_SPL_BUILD) += spl.o ps7_spl_init.o +obj-$(CONFIG_XPL_BUILD) += spl.o ps7_spl_init.o diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 5b6d765099d..74dddc25988 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -52,7 +52,7 @@ static const struct { int arch_cpu_init(void) { zynq_slcr_unlock(); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 38be1627eeb..ff426044797 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -5,10 +5,10 @@ obj-y += aes.o clk.o cpu.o obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o +obj-$(CONFIG_XPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o -obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o +obj-$(CONFIG_$(XPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o -endif # !CONFIG_SPL_BUILD +endif # !CONFIG_XPL_BUILD diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 07668c94689..24fd5751216 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -187,7 +187,7 @@ int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) { - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) return zynqmp_mmio_rawwrite(address, mask, value); #if defined(CONFIG_ZYNQMP_FIRMWARE) else @@ -205,7 +205,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value) if (!value) return ret; - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { ret = zynqmp_mmio_rawread(address, value); } #if defined(CONFIG_ZYNQMP_FIRMWARE) |