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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/tegra20-lg-star.dts538
-rw-r--r--arch/arm/include/asm/arch-tegra/dc.h48
-rw-r--r--arch/arm/mach-tegra/Kconfig17
-rw-r--r--arch/arm/mach-tegra/board2.c25
-rw-r--r--arch/arm/mach-tegra/tegra20/Kconfig5
6 files changed, 609 insertions, 25 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c197e3b7a8e..32b698a7f41 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
tegra20-asus-tf101.dtb \
tegra20-asus-tf101g.dtb \
tegra20-harmony.dtb \
+ tegra20-lg-star.dtb \
tegra20-medcom-wide.dtb \
tegra20-motorola-daytona.dtb \
tegra20-motorola-olympus.dtb \
diff --git a/arch/arm/dts/tegra20-lg-star.dts b/arch/arm/dts/tegra20-lg-star.dts
new file mode 100644
index 00000000000..3045bc3135f
--- /dev/null
+++ b/arch/arm/dts/tegra20-lg-star.dts
@@ -0,0 +1,538 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+
+#include "tegra20.dtsi"
+
+/ {
+ model = "LG Optimus 2X (P990)";
+ compatible = "lg,star", "nvidia,tegra20";
+
+ chosen {
+ stdout-path = &uartb;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+ i2c5 = &dcdc_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* uSD slot */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = &micro_usb;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>; /* 512 MB */
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ port {
+ dpi_output: endpoint {
+ remote-endpoint = <&bridge_input>;
+ bus-width = <24>;
+ };
+ };
+ };
+ };
+ };
+
+ pinmux@70000014 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ crt {
+ nvidia,pins = "crtp";
+ nvidia,function = "crt";
+ };
+
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+
+ displaya {
+ nvidia,pins = "lcsn", "ld0", "ld1", "ld10",
+ "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ld2",
+ "ld3", "ld4", "ld5", "ld6",
+ "ld7", "ld8", "ld9", "ldc",
+ "ldi", "lhp0", "lhp1", "lhp2",
+ "lhs", "lm0", "lm1", "lpp",
+ "lpw0", "lpw1", "lpw2", "lsc0",
+ "lsc1", "lsck", "lsda", "lsdi",
+ "lspi", "lvp0", "lvp1", "lvs";
+ nvidia,function = "displaya";
+ };
+
+ gmi {
+ nvidia,pins = "ata", "atc", "atd", "ate",
+ "gmb", "irrx", "irtx";
+ nvidia,function = "gmi";
+ };
+
+ hdmi {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+
+ i2c {
+ nvidia,pins = "i2cp", "rm";
+ nvidia,function = "i2c";
+ };
+
+ i2c2 {
+ nvidia,pins = "pta";
+ nvidia,function = "i2c2";
+ };
+
+ i2c3 {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+
+ kbc {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbce",
+ "kbcf";
+ nvidia,function = "kbc";
+ };
+
+ owr {
+ nvidia,pins = "owc";
+ nvidia,function = "owr";
+ };
+
+ plla-out {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+
+ pllp-out4 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+
+ pwm {
+ nvidia,pins = "gpu";
+ nvidia,function = "pwm";
+ };
+
+ pwr-on {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+
+ rtck {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+
+ sdio2 {
+ nvidia,pins = "kbcd";
+ nvidia,function = "sdio2";
+ };
+
+ sdio3 {
+ nvidia,pins = "sdb", "sdc", "sdd", "slxa",
+ "slxd", "slxk", "slxc";
+ nvidia,function = "sdio3";
+ };
+
+ sdio4 {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+
+ spi1 {
+ nvidia,pins = "uda";
+ nvidia,function = "spi1";
+ };
+
+ spi2 {
+ nvidia,pins = "spia", "spib", "spic";
+ nvidia,function = "spi2";
+ };
+
+ spi2-alt {
+ nvidia,pins = "spid", "spie", "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+
+ uarta {
+ nvidia,pins = "uaa", "uab";
+ nvidia,function = "uarta";
+ };
+
+ uartc {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+
+ uartd {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+
+ vi {
+ nvidia,pins = "dtc", "dtd";
+ nvidia,function = "vi";
+ };
+
+ vi-sensor-clk {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+
+ conf-lsda {
+ nvidia,pins = "lsda", "owc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+
+ conf-ata {
+ nvidia,pins = "ata", "dtf", "gmb", "gmc",
+ "i2cp", "irrx", "kbca", "kbcc",
+ "kbcd", "kbce", "kbcf", "lcsn",
+ "ldc", "pta", "rm", "sdc",
+ "sdd", "spie", "spif", "spig",
+ "spih", "uaa", "uad", "uca",
+ "ucb", "pmce";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf-crtp {
+ nvidia,pins = "crtp", "gpv", "hdint", "lhs",
+ "lm0", "lpw0", "lpw1", "lpw2",
+ "lsc1", "lsck", "lspi", "lvs",
+ "slxa", "slxd", "spdi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+
+ conf-atb {
+ nvidia,pins = "atb", "atc", "atd", "ate",
+ "cdev1", "cdev2", "csus", "dap1",
+ "dap2", "dap3", "dap4", "ddc",
+ "dta", "dtb", "dte", "gma",
+ "gmd", "gme", "gpu", "gpu7",
+ "irtx", "kbcb", "lm1", "lsc0",
+ "lsdi", "lvp0", "pmc", "sdb",
+ "sdio1", "slxc", "spdo", "spia",
+ "spib", "spic", "uab", "uac",
+ "uda", "ck32", "ddrc", "pmca",
+ "pmcb", "pmcc", "pmcd", "xm2c",
+ "xm2d";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ conf-dtc {
+ nvidia,pins = "dtc", "dtd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+
+ conf-ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+ "ld4", "ld5", "ld6", "ld7",
+ "ld8", "ld9", "ld10", "ld11",
+ "ld12", "ld13", "ld14", "ld15",
+ "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lpp", "lvp1",
+ "slxk", "spid";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ drive-sdio1 {
+ nvidia,pins = "drive_sdio1", "drive_vi1";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+
+ drive-i2c {
+ nvidia,pins = "drive_dbg", "drive_ddc", "drive_at1",
+ "drive_vi2", "drive_ao1";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive-dap {
+ nvidia,pins = "drive_dap2", "drive_dap3";
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <46>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+ };
+
+ uartb: serial@70006040 {
+ clocks = <&tegra_car 7>;
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pmic: max8907@3c {
+ compatible = "maxim,max8907";
+ reg = <0x3c>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ maxim,system-power-controller;
+
+ regulators {
+ vdd_1v8_vio: sd3 {
+ regulator-name = "vcc_1v8_io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ iovcc_1v8_lcd: ldo3 {
+ regulator-name = "vcc_1v8_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ avdd_3v3_usb: ldo4 {
+ regulator-name = "avdd_3v3_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: ldo5 {
+ regulator-name = "vcc_2v8_emmc";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-boot-on;
+ };
+
+ vdd_usd: ldo12 {
+ regulator-name = "vcc_2v8_sdio";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-boot-on;
+ };
+
+ vcc_2v8_lcd: ldo14 {
+ regulator-name = "vcc_2v8_lcd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+ dcdc_i2c: i2c-5 {
+ compatible = "i2c-gpio";
+
+ sda-gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_HIGH>;
+
+ i2c-gpio,delay-us = <5>;
+ i2c-gpio,timeout-ms = <100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ aat2870: led-controller@60 {
+ compatible = "skyworks,aat2870";
+ reg = <0x60>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+
+ backlight {
+ current-max-microamp = <27900000>;
+ };
+ };
+ };
+
+ micro_usb: usb@c5000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ vbus-supply = <&avdd_3v3_usb>;
+ };
+
+ sdmmc3: sdhci@c8000400 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vdd_usd>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ sdmmc4: sdhci@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8_vio>;
+ };
+
+ /* 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k-in {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ref-oscillator";
+ };
+
+ bridge: cpu-bridge {
+ compatible = "nvidia,tegra-8bit-cpu";
+
+ dc-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
+ rw-gpios = <&gpio TEGRA_GPIO(B, 3) GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+
+ data-gpios = <&gpio TEGRA_GPIO(E, 0) GPIO_ACTIVE_HIGH>,
+ <&gpio TEGRA_GPIO(E, 1) GPIO_ACTIVE_HIGH>,
+ <&gpio TEGRA_GPIO(E, 2) GPIO_ACTIVE_HIGH>,
+ <&gpio TEGRA_GPIO(E, 3) GPIO_ACTIVE_HIGH>,
+ <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>,
+ <&gpio TEGRA_GPIO(E, 5) GPIO_ACTIVE_HIGH>,
+ <&gpio TEGRA_GPIO(E, 6) GPIO_ACTIVE_HIGH>,
+ <&gpio TEGRA_GPIO(E, 7) GPIO_ACTIVE_HIGH>;
+
+ nvidia,init-sequence = <0x0000002c 0x0 0x0 0x00005000>;
+
+ panel {
+ /*
+ * There are 2 rev of P990. One has Hitachi TX10D07VM0BAA
+ * panel and other has LG LH400WV3-SD04 panel. We are using
+ * Hitachi here but it is dynamically adjusted for the
+ * correct compatible.
+ */
+ compatible = "hit,tx10d07vm0baa";
+
+ reset-gpios = <&gpio TEGRA_GPIO(V, 7) GPIO_ACTIVE_LOW>;
+
+ avci-supply = <&vcc_2v8_lcd>;
+ iovcc-supply = <&iovcc_1v8_lcd>;
+
+ backlight = <&aat2870>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&bridge_output>;
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_input: endpoint {
+ remote-endpoint = <&dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(G, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(G, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+ };
+
+ vdd_3v3_vbat: regulator-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_vbat";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index 2fd07403bdf..ab12cc9c7d0 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -448,10 +448,19 @@ enum win_color_depth_id {
#define LVS_OUTPUT_POLARITY_LOW BIT(28)
#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
+/* DC_COM_PIN_OUTPUT_SELECT6 0x31a */
+#define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) /* 100b */
+
/* DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 */
#define H_PULSE0_ENABLE BIT(8)
#define H_PULSE1_ENABLE BIT(10)
#define H_PULSE2_ENABLE BIT(12)
+#define V_PULSE0_ENABLE BIT(16)
+#define V_PULSE1_ENABLE BIT(18)
+#define V_PULSE2_ENABLE BIT(19)
+#define V_PULSE3_ENABLE BIT(20)
+#define M0_ENABLE BIT(24)
+#define M1_ENABLE BIT(26)
/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
#define CURSOR_ENABLE BIT(16)
@@ -525,6 +534,28 @@ enum {
BASE_COLOR_SIZE_888,
};
+/* DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 */
+#define SC0_H_QUALIFIER_SHIFT 0
+#define SC1_H_QUALIFIER_SHIFT 16
+enum {
+ SC_H_QUALIFIER_DISABLE,
+ SC_H_QUALIFIER_NONE,
+ SC_H_QUALIFIER_HACTIVE,
+ SC_H_QUALIFIER_EXT_HACTIVE,
+ SC_H_QUALIFIER_HPULSE,
+ SC_H_QUALIFIER_EXT_HPULSE,
+};
+#define SC0_V_QUALIFIER_SHIFT 3
+#define SC1_V_QUALIFIER_SHIFT 19
+enum {
+ SC_V_QUALIFIER_NONE,
+ SC_V_QUALIFIER_RSVD,
+ SC_V_QUALIFIER_VACTIVE,
+ SC_V_QUALIFIER_EXT_VACTIVE,
+ SC_V_QUALIFIER_VPULSE,
+ SC_V_QUALIFIER_EXT_VPULSE,
+};
+
/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
#define DE_SELECT_SHIFT 0
#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
@@ -541,6 +572,23 @@ enum {
DE_CONTROL_ACTIVE_BLANK,
};
+/* DC_DISP_INIT_SEQ_CONTROL 0x442 */
+#define SEND_INIT_SEQUENCE BIT(0)
+#define INIT_SEQUENCE_MODE_SPI BIT(1)
+#define INIT_SEQUENCE_MODE_PLCD 0x0
+#define INIT_SEQ_DC_SIGNAL_SHIFT 4
+#define INIT_SEQ_DC_SIGNAL_MASK (0x7 << INIT_SEQ_DC_SIGNAL_SHIFT)
+enum {
+ NO_DC_SIGNAL,
+ DC_SIGNAL_VSYNC,
+ DC_SIGNAL_VPULSE0,
+ DC_SIGNAL_VPULSE1,
+ DC_SIGNAL_VPULSE2,
+ DC_SIGNAL_VPULSE3,
+};
+#define INIT_SEQ_DC_CONTROL_SHIFT 7
+#define FRAME_INIT_SEQ_CYCLES_SHIFT 8
+
/* DC_WIN_WIN_OPTIONS 0x700 */
#define H_DIRECTION BIT(0)
enum {
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 4690dcb3ea6..c3c352eceb1 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -198,6 +198,23 @@ source "arch/arm/mach-tegra/tegra124/Kconfig"
source "arch/arm/mach-tegra/tegra210/Kconfig"
source "arch/arm/mach-tegra/tegra186/Kconfig"
+config SYS_CONFIG_NAME
+ default "tegra"
+
+config TEGRA_PRAM
+ select TEGRA_SUPPORT_NON_SECURE if TEGRA114 || TEGRA124
+ bool "Support reservation of the protected RAM"
+ help
+ This option indicates the presence of a region of protected RAM.
+
+config TEGRA_PRAM_SIZE
+ hex "Size of pRAM region"
+ depends on TEGRA_PRAM
+ default 0x1000
+ help
+ Size in kB of carevout which will be reserved as protected RAM starting
+ from the top of the RAM.
+
config TEGRA_SPI
def_bool y
depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 68534dcbb22..396851c5bd8 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -227,31 +227,6 @@ int board_early_init_f(void)
arch_timer_init();
#endif
-#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
- /*
- * Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
- * We do this because earlier bootloaders have enabled power to
- * SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
- * results in power being back-driven into the SD-card and SDMMC1
- * HW, which is 'bad' as per the HW team.
- *
- * From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
- * nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
- * table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
- * the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
- * voltage turns off. Since the SDCard voltage is no longer there, the
- * SDMMC CLK/DAT lines are backdriving into what essentially is a
- * powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
- *
- * Note that this can probably be removed when we change over to storing
- * all BL components on QSPI on Nano, and U-Boot then becomes the first
- * one to turn on SDMMC1 power. Another fix would be to have CBoot
- * disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
- */
- reset_set_enable(PERIPH_ID_SDMMC1, 1);
- clock_set_enable(PERIPH_ID_SDMMC1, 0);
-#endif /* CONFIG_DISABLE_SDMMC1_EARLY */
-
pinmux_init();
board_init_uart_f();
diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig
index a79fdc25650..bedbedade7b 100644
--- a/arch/arm/mach-tegra/tegra20/Kconfig
+++ b/arch/arm/mach-tegra/tegra20/Kconfig
@@ -54,6 +54,10 @@ config TARGET_SEABOARD
select TEGRA_LP0
select TEGRA_PMU
+config TARGET_STAR
+ bool "LG Tegra20 Star board"
+ select BOARD_LATE_INIT
+
config TARGET_TEC
bool "Avionic Design Tamonten Evaluation Carrier"
select BOARD_LATE_INIT
@@ -88,6 +92,7 @@ source "board/compal/paz00/Kconfig"
source "board/acer/picasso/Kconfig"
source "board/avionic-design/plutux/Kconfig"
source "board/nvidia/seaboard/Kconfig"
+source "board/lg/star/Kconfig"
source "board/avionic-design/tec/Kconfig"
source "board/asus/transformer-t20/Kconfig"
source "board/compulab/trimslice/Kconfig"
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 09:52:21 +0000