diff options
Diffstat (limited to 'arch/i386/include/asm')
| -rw-r--r-- | arch/i386/include/asm/global_data.h | 21 | ||||
| -rw-r--r-- | arch/i386/include/asm/ic/sc520.h | 93 | ||||
| -rw-r--r-- | arch/i386/include/asm/processor-flags.h | 100 | ||||
| -rw-r--r-- | arch/i386/include/asm/processor.h | 9 | ||||
| -rw-r--r-- | arch/i386/include/asm/u-boot-i386.h | 3 |
5 files changed, 210 insertions, 16 deletions
diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index e3f8a25efb6..f8a16d646fd 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -35,7 +35,7 @@ #ifndef __ASSEMBLY__ -typedef struct { +typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long baudrate; @@ -46,6 +46,8 @@ typedef struct { unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; + unsigned long relocaddr; /* Start address of U-Boot in RAM */ + unsigned long start_addr_sp; /* start_addr_stackpointer */ phys_size_t ram_size; /* RAM size */ unsigned long reset_status; /* reset status register at boot */ void **jt; /* jump table */ @@ -67,11 +69,13 @@ extern gd_t *gd; #define GD_ENV_VALID 7 #define GD_CPU_CLK 8 #define GD_BUS_CLK 9 -#define GD_RAM_SIZE 10 -#define GD_RESET_STATUS 11 -#define GD_JT 12 +#define GD_RELOC_ADDR 10 +#define GD_START_ADDR_SP 11 +#define GD_RAM_SIZE 12 +#define GD_RESET_STATUS 13 +#define GD_JT 14 -#define GD_SIZE 13 +#define GD_SIZE 15 /* * Global Data Flags @@ -87,7 +91,12 @@ extern gd_t *gd; #define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ #define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */ - +#if 0 #define DECLARE_GLOBAL_DATA_PTR +#else +#define XTRN_DECLARE_GLOBAL_DATA_PTR extern +#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ +gd_t *gd +#endif #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/i386/include/asm/ic/sc520.h b/arch/i386/include/asm/ic/sc520.h index 053d9c6773a..956c1c26360 100644 --- a/arch/i386/include/asm/ic/sc520.h +++ b/arch/i386/include/asm/ic/sc520.h @@ -252,16 +252,68 @@ typedef struct sc520_mmcr { u8 pad_0xdc0[0x0240]; } sc520_mmcr_t; -extern volatile sc520_mmcr_t *sc520_mmcr; +extern sc520_mmcr_t *sc520_mmcr; #endif -/* MMCR Offsets (required for assembler code */ -#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ -#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ -#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ -#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ -#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ +/* Memory Mapped Control Registers (MMCR) Base Address */ +#define SC520_MMCR_BASE 0xfffef000 + +/* MMCR Addresses (required for assembler code) */ +#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010) +#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012) +#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014) +#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018) +#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020) +#define SC520_DBCTL (SC520_MMCR_BASE + 0x040) +#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18) + +#define SC520_PAR0 (SC520_MMCR_BASE + 0x088) +#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1)) +#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2)) +#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3)) +#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4)) +#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5)) +#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6)) +#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7)) +#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8)) +#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9)) +#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10)) +#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11)) +#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12)) +#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13)) +#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14)) +#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15)) + +/* + * PARs for maximum allowable 256MB of SDRAM @ 0x00000000 + * Two PARs are required due to maximum PAR size of 128MB + * These are used in the SDRAM sizing code to disable caching + * + * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000 + * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800 + * \ / | | | | \----+----/ \-----+------/ + * | | | | | | +---------- Start at 0x00000000 + * | | | | | | 0x08000000 + * | | | | | +----------------------- 128MB Region Size + * | | | | | ((2047 + 1) * 64kB) + * | | | | +------------------------------ 64kB Page Size + * | | | +-------------------------------- Writes Enabled + * | | +---------------------------------- Caching Enabled + * | +------------------------------------ Execution Enabled + * +--------------------------------------- SDRAM + */ +#define SC520_SDRAM1_PAR 0xe3ffc000 +#define SC520_SDRAM2_PAR 0xe3ffc800 + +#define SC520_PAR_WRITE_DIS 0x04000000 +#define SC520_PAR_CACHE_DIS 0x08000000 +#define SC520_PAR_EXEC_DIS 0x10000000 + +/* + * Programmable Address Regions to cover 256MB SDRAM (Maximum supported) + * required for DRAM sizing code + */ /* MMCR Register bits (not all of them :) ) */ @@ -293,6 +345,33 @@ extern volatile sc520_mmcr_t *sc520_mmcr; #define UART2_DIS 0x02 /* UART2 Disable */ #define UART1_DIS 0x01 /* UART1 Disable */ +/* + * Defines used for SDRAM Sizing (number of columns and rows) + * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the + * Elan SC520 Microcontroller User's Manual (Order #22004B) + */ +#define CACHELINESZ 0x00000010 + +#define COL11_ADR 0x0e001e00 +#define COL10_ADR 0x0e000e00 +#define COL09_ADR 0x0e000600 +#define COL08_ADR 0x0e000200 +#define COL11_DATA 0x0b0b0b0b +#define COL10_DATA 0x0a0a0a0a +#define COL09_DATA 0x09090909 +#define COL08_DATA 0x08080808 + +#define ROW14_ADR 0x0f000000 +#define ROW13_ADR 0x07000000 +#define ROW12_ADR 0x03000000 +#define ROW11_ADR 0x01000000 +#define ROW10_ADR 0x00000000 +#define ROW14_DATA 0x3f3f3f3f +#define ROW13_DATA 0x1f1f1f1f +#define ROW12_DATA 0x0f0f0f0f +#define ROW11_DATA 0x07070707 +#define ROW10_DATA 0xaaaaaaaa + /* 0x28000000 - 0x3fffffff is used by the flash banks */ /* 0x40000000 - 0xffffffff is not adressable by the SC520 */ diff --git a/arch/i386/include/asm/processor-flags.h b/arch/i386/include/asm/processor-flags.h new file mode 100644 index 00000000000..7a3e836eb2a --- /dev/null +++ b/arch/i386/include/asm/processor-flags.h @@ -0,0 +1,100 @@ +#ifndef _ASM_X86_PROCESSOR_FLAGS_H +#define _ASM_X86_PROCESSOR_FLAGS_H +/* Various flags defined: can be included from assembler. */ + +/* + * EFLAGS bits + */ +#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ +#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ +#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ +#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ +#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ +#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ +#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ +#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ +#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ +#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ +#define X86_EFLAGS_NT 0x00004000 /* Nested Task */ +#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ +#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ +#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ +#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ +#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ +#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ + +/* + * Basic CPU control in CR0 + */ +#define X86_CR0_PE 0x00000001 /* Protection Enable */ +#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ +#define X86_CR0_EM 0x00000004 /* Emulation */ +#define X86_CR0_TS 0x00000008 /* Task Switched */ +#define X86_CR0_ET 0x00000010 /* Extension Type */ +#define X86_CR0_NE 0x00000020 /* Numeric Error */ +#define X86_CR0_WP 0x00010000 /* Write Protect */ +#define X86_CR0_AM 0x00040000 /* Alignment Mask */ +#define X86_CR0_NW 0x20000000 /* Not Write-through */ +#define X86_CR0_CD 0x40000000 /* Cache Disable */ +#define X86_CR0_PG 0x80000000 /* Paging */ + +/* + * Paging options in CR3 + */ +#define X86_CR3_PWT 0x00000008 /* Page Write Through */ +#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ + +/* + * Intel CPU features in CR4 + */ +#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ +#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ +#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ +#define X86_CR4_DE 0x00000008 /* enable debugging extensions */ +#define X86_CR4_PSE 0x00000010 /* enable page size extensions */ +#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ +#define X86_CR4_MCE 0x00000040 /* Machine check enable */ +#define X86_CR4_PGE 0x00000080 /* enable global pages */ +#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ +#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ +#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ +#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ +#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ + +/* + * x86-64 Task Priority Register, CR8 + */ +#define X86_CR8_TPR 0x0000000F /* task priority register */ + +/* + * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> + */ + +/* + * NSC/Cyrix CPU configuration register indexes + */ +#define CX86_PCR0 0x20 +#define CX86_GCR 0xb8 +#define CX86_CCR0 0xc0 +#define CX86_CCR1 0xc1 +#define CX86_CCR2 0xc2 +#define CX86_CCR3 0xc3 +#define CX86_CCR4 0xe8 +#define CX86_CCR5 0xe9 +#define CX86_CCR6 0xea +#define CX86_CCR7 0xeb +#define CX86_PCR1 0xf0 +#define CX86_DIR0 0xfe +#define CX86_DIR1 0xff +#define CX86_ARR_BASE 0xc4 +#define CX86_RCR_BASE 0xdc + +#ifdef __KERNEL__ +#ifdef CONFIG_VM86 +#define X86_VM_MASK X86_EFLAGS_VM +#else +#define X86_VM_MASK 0 /* No VM86 support */ +#endif +#endif + +#endif /* _ASM_X86_PROCESSOR_FLAGS_H */ diff --git a/arch/i386/include/asm/processor.h b/arch/i386/include/asm/processor.h index 5dedba82ca7..22a129813cd 100644 --- a/arch/i386/include/asm/processor.h +++ b/arch/i386/include/asm/processor.h @@ -23,7 +23,10 @@ #ifndef __ASM_PROCESSOR_H_ #define __ASM_PROCESSOR_H_ 1 -/* Currently this header is unused in the i386 port - * but some generic files #include <asm/processor.h> - * so this file is a placeholder. */ + +#define GDT_ENTRY_32BIT_CS 2 +#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1) +#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1) +#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1) + #endif diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h index ce097a3bfa6..7b39bd2ae01 100644 --- a/arch/i386/include/asm/u-boot-i386.h +++ b/arch/i386/include/asm/u-boot-i386.h @@ -25,7 +25,9 @@ #define _U_BOOT_I386_H_ 1 /* cpu/.../cpu.c */ +int x86_cpu_init_r(void); int cpu_init_r(void); +int x86_cpu_init_f(void); int cpu_init_f(void); /* cpu/.../timer.c */ @@ -35,6 +37,7 @@ int register_timer_isr (timer_fnc_t *isr_func); /* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */ int timer_init(void); +int dram_init_f(void); /* cpu/.../interrupts.c */ int cpu_init_interrupts(void); |