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-rw-r--r--arch/m68k/cpu/mcf523x/cpu.c2
-rw-r--r--arch/m68k/cpu/mcf523x/cpu_init.c38
-rw-r--r--arch/m68k/cpu/mcf523x/speed.c2
-rw-r--r--arch/m68k/cpu/mcf523x/start.S6
-rw-r--r--arch/m68k/cpu/mcf52x2/cpu.c16
-rw-r--r--arch/m68k/cpu/mcf52x2/cpu_init.c110
-rw-r--r--arch/m68k/cpu/mcf52x2/speed.c14
-rw-r--r--arch/m68k/cpu/mcf52x2/start.S48
-rw-r--r--arch/m68k/cpu/mcf530x/cpu.c2
-rw-r--r--arch/m68k/cpu/mcf530x/cpu_init.c48
-rw-r--r--arch/m68k/cpu/mcf530x/speed.c4
-rw-r--r--arch/m68k/cpu/mcf530x/start.S10
-rw-r--r--arch/m68k/cpu/mcf532x/cpu.c2
-rw-r--r--arch/m68k/cpu/mcf532x/cpu_init.c86
-rw-r--r--arch/m68k/cpu/mcf532x/speed.c4
-rw-r--r--arch/m68k/cpu/mcf532x/start.S6
-rw-r--r--arch/m68k/cpu/mcf5445x/cpu_init.c38
-rw-r--r--arch/m68k/cpu/mcf5445x/start.S46
18 files changed, 241 insertions, 241 deletions
diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c
index e44656db5f2..ba2c2289119 100644
--- a/arch/m68k/cpu/mcf523x/cpu.c
+++ b/arch/m68k/cpu/mcf523x/cpu.c
@@ -92,7 +92,7 @@ int watchdog_init(void)
u32 wdog_module = 0;
/* set timeout and enable watchdog */
- wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT_MSECS);
wdog_module |= (wdog_module / 8192);
out_be16(&wdp->mr, wdog_module);
diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c
index 87effa71dc3..10be73822fa 100644
--- a/arch/m68k/cpu/mcf523x/cpu_init.c
+++ b/arch/m68k/cpu/mcf523x/cpu_init.c
@@ -47,36 +47,36 @@ void cpu_init_f(void)
out_be16(&wdog->cr, 0);
#endif
- out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+ out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
out_8(&gpio->par_cs, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+ out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
- out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
- out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
- out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@@ -108,8 +108,8 @@ void cpu_init_f(void)
#endif
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
icache_enable();
diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c
index f41f977d7f5..6b08a12af0b 100644
--- a/arch/m68k/cpu/mcf523x/speed.c
+++ b/arch/m68k/cpu/mcf523x/speed.c
@@ -29,7 +29,7 @@ int get_clocks(void)
while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
;
- gd->bus_clk = CONFIG_SYS_CLK;
+ gd->bus_clk = CFG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_SYS_I2C_FSL
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index 4c9c96d7831..d2a21c3279b 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -91,10 +91,10 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
@@ -116,7 +116,7 @@ _start:
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 8f72ef567fe..d7cbf11e255 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -87,7 +87,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
out_be16(&wdt->mr,
- (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+ (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
/* reset watchdog counter */
out_be16(&wdt->sr, 0x5555);
@@ -132,11 +132,11 @@ int print_cpuinfo(void)
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
- cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
+ cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
- pin, prn, strmhz(buf, CONFIG_SYS_CLK));
+ pin, prn, strmhz(buf, CFG_SYS_CLK));
return 0;
}
@@ -253,7 +253,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
out_be16(&wdt->wdog_wrrr,
- (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+ (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
/* reset watchdog counter */
out_be16(&wdt->wdog_wcr, 0);
@@ -284,7 +284,7 @@ int print_cpuinfo(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
return 0;
};
#endif /* CONFIG_DISPLAY_CPUINFO */
@@ -323,7 +323,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
out_be16(&wdt->wmr,
- (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+ (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
/* reset watchdog counter */
out_be16(&wdt->wsr, 0x5555);
@@ -370,7 +370,7 @@ int print_cpuinfo(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
@@ -394,7 +394,7 @@ int print_cpuinfo(void)
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CLK));
+ strmhz(buf, CFG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",
diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c
index 9d4a10f028d..99eb61f1675 100644
--- a/arch/m68k/cpu/mcf52x2/cpu_init.c
+++ b/arch/m68k/cpu/mcf52x2/cpu_init.c
@@ -36,31 +36,31 @@ void init_fbcs(void)
{
fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
@@ -214,9 +214,9 @@ void cpu_init_f(void)
init_fbcs();
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG =
- CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG =
+ CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
@@ -335,21 +335,21 @@ void cpu_init_f(void)
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+ sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR);
gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
- out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
+ out_be16(&sysctrl->sc_scr, CFG_SYS_SCR);
+ out_be16(&sysctrl->sc_spr, CFG_SYS_SPR);
/* Setup Ports: */
- out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
- out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
- out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
- out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
- out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
- out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
- out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
+ out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT);
+ out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR);
+ out_be16(&gpio->gpio_padat, CFG_SYS_PADAT);
+ out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT);
+ out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR);
+ out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT);
+ out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT);
/* Memory Controller: */
out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
@@ -472,8 +472,8 @@ void cpu_init_f(void)
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_SYS_I2C_FSL
- CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
- CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+ CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
+ CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
@@ -560,8 +560,8 @@ void cpu_init_f(void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
- MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
- MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
+ MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) |
+ MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
@@ -573,17 +573,17 @@ void cpu_init_f(void)
#ifdef CONFIG_SYS_PFPAR
MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
-#ifdef CONFIG_SYS_PJPAR
- MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
+#ifdef CFG_SYS_PJPAR
+ MCFGPIO_PJPAR = CFG_SYS_PJPAR;
#endif
#ifdef CONFIG_SYS_PSDPAR
MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
-#ifdef CONFIG_SYS_PASPAR
- MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
+#ifdef CFG_SYS_PASPAR
+ MCFGPIO_PASPAR = CFG_SYS_PASPAR;
#endif
-#ifdef CONFIG_SYS_PEHLPAR
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+#ifdef CFG_SYS_PEHLPAR
+ MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
#endif
#ifdef CONFIG_SYS_PQSPAR
MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
@@ -600,15 +600,15 @@ void cpu_init_f(void)
#ifdef CONFIG_SYS_PTDPAR
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
-#ifdef CONFIG_SYS_PUAPAR
- MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
+#ifdef CFG_SYS_PUAPAR
+ MCFGPIO_PUAPAR = CFG_SYS_PUAPAR;
#endif
#if defined(CONFIG_SYS_DDRD)
MCFGPIO_DDRD = CONFIG_SYS_DDRD;
#endif
-#ifdef CONFIG_SYS_DDRUA
- MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
+#ifdef CFG_SYS_DDRUA
+ MCFGPIO_DDRUA = CFG_SYS_DDRUA;
#endif
/* FlexBus Chipselect */
@@ -652,10 +652,10 @@ int fecpin_setclear(fec_info_t *info, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
- MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+ MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
- MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+ MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR;
}
return 0;
}
@@ -678,12 +678,12 @@ void cpu_init_f(void)
* which is their primary function.
* ~Jeremy
*/
- mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
- mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
- mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
- mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
- mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
- mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
+ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN);
+ mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN);
+ mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT);
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c
index 045908a13d4..6c7628252b5 100644
--- a/arch/m68k/cpu/mcf52x2/speed.c
+++ b/arch/m68k/cpu/mcf52x2/speed.c
@@ -23,19 +23,19 @@ int get_clocks(void)
#if defined(CONFIG_M5208)
pll_t *pll = (pll_t *) MMAP_PLL;
- out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
- out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
+ out_8(&pll->odr, CFG_SYS_PLL_ODR);
+ out_8(&pll->fdr, CFG_SYS_PLL_FDR);
#endif
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
-#ifndef CONFIG_SYS_PLL_BYPASS
+#ifndef CFG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
-#ifdef CONFIG_SYS_FAST_CLK
+#ifdef CFG_SYS_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
@@ -43,7 +43,7 @@ int get_clocks(void)
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
- pllcr = CONFIG_SYS_PLLCR;
+ pllcr = CFG_SYS_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -52,7 +52,7 @@ int get_clocks(void)
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
+#endif /* #ifndef CFG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@@ -68,7 +68,7 @@ int get_clocks(void)
;
#endif
- gd->cpu_clk = CONFIG_SYS_CLK;
+ gd->cpu_clk = CFG_SYS_CLK;
#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
defined(CONFIG_M5271) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index 6dddbe76f3a..d48d0192eea 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -35,7 +35,7 @@
*/
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long _start - CONFIG_TEXT_BASE
#else
.long _START
@@ -81,9 +81,9 @@ _vectors:
.text
-#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
+#if defined(CFG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
@@ -100,53 +100,53 @@ _start:
#if defined(CONFIG_M5208)
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/
-#ifdef CONFIG_SYS_MBAR2
+#ifdef CFG_SYS_MBAR2
/* Get MBAR2 address */
- move.l #(CONFIG_SYS_MBAR2 + 1), %d0
+ move.l #(CFG_SYS_MBAR2 + 1), %d0
/* Set MBAR2 */
movec %d0, #0xc0e
#endif
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
-#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
/*
* Setup code in SRAM to initialize FLASHBAR,
* if start from internal Flash
*/
- move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
- move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
+ move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
+ move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1
+ move.l #(CFG_SYS_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
- jmp CONFIG_SYS_INIT_RAM_ADDR
+ jmp CFG_SYS_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
- move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+ move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
@@ -154,9 +154,9 @@ _flashbar_setup_end:
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
- move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
+ move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
-#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
+#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
#endif
#endif
@@ -165,22 +165,22 @@ _after_flashbar_copy:
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
- move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
+#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
+ move.l #CFG_SYS_INT_FLASH_BASE, %d0
#else
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif
#ifdef CONFIG_M5275
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
@@ -195,7 +195,7 @@ _after_flashbar_copy:
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c
index 0659bf65581..53a25d8362c 100644
--- a/arch/m68k/cpu/mcf530x/cpu.c
+++ b/arch/m68k/cpu/mcf530x/cpu.c
@@ -33,7 +33,7 @@ int print_cpuinfo(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n",
- strmhz(buf, CONFIG_SYS_CPU_CLK));
+ strmhz(buf, CFG_SYS_CPU_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c
index 83529408eb3..dad47d87ab3 100644
--- a/arch/m68k/cpu/mcf530x/cpu_init.c
+++ b/arch/m68k/cpu/mcf530x/cpu_init.c
@@ -40,35 +40,35 @@ void init_csm(void)
{
csm_t *csm = (csm_t *)(MMAP_CSM);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \
- defined(CONFIG_SYS_CS0_CTRL))
- out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK);
- out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \
+ defined(CFG_SYS_CS0_CTRL))
+ out_be16(&csm->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&csm->csmr0, CFG_SYS_CS0_MASK);
+ out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \
- defined(CONFIG_SYS_CS1_CTRL))
- out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK);
- out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1);
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \
+ defined(CFG_SYS_CS1_CTRL))
+ out_be16(&csm->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&csm->csmr1, CFG_SYS_CS1_MASK);
+ out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \
- defined(CONFIG_SYS_CS2_CTRL))
- out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK);
- out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \
+ defined(CFG_SYS_CS2_CTRL))
+ out_be16(&csm->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&csm->csmr2, CFG_SYS_CS2_MASK);
+ out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \
- defined(CONFIG_SYS_CS3_CTRL))
- out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK);
- out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL);
- MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \
+ defined(CFG_SYS_CS3_CTRL))
+ out_be16(&csm->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&csm->csmr3, CFG_SYS_CS3_MASK);
+ out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL);
+ MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \
defined(CONFIG_SYS_CS4_CTRL))
diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c
index 03d9abeb182..c8d079016f2 100644
--- a/arch/m68k/cpu/mcf530x/speed.c
+++ b/arch/m68k/cpu/mcf530x/speed.c
@@ -16,8 +16,8 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
#if defined(CONFIG_M5307)
- gd->bus_clk = CONFIG_SYS_CLK;
- gd->cpu_clk = CONFIG_SYS_CPU_CLK;
+ gd->bus_clk = CFG_SYS_CLK;
+ gd->cpu_clk = CFG_SYS_CPU_CLK;
#endif
return 0;
diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S
index 644c372bdd2..dbe2b54e410 100644
--- a/arch/m68k/cpu/mcf530x/start.S
+++ b/arch/m68k/cpu/mcf530x/start.S
@@ -39,7 +39,7 @@ _vectors:
/* Flash offset is 0 until we setup CS0 */
.long 0x00000000
#if defined(CONFIG_M5307) && \
- (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+ (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long _start - CONFIG_TEXT_BASE
#else
.long _START
@@ -92,10 +92,10 @@ _start:
move.w #0x2700,%sr
/* set MBAR address + valid flag */
- move.l #(CONFIG_SYS_MBAR + 1), %d0
+ move.l #(CFG_SYS_MBAR + 1), %d0
move.c %d0, %MBAR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
move.c %d0, %RAMBAR
/* DS 4.8.2 (Cache Organization) invalidate and disable cache */
@@ -110,7 +110,7 @@ _start:
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
#endif
@@ -125,7 +125,7 @@ _start:
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c
index 1dadffd4ca3..548cbca36aa 100644
--- a/arch/m68k/cpu/mcf532x/cpu.c
+++ b/arch/m68k/cpu/mcf532x/cpu.c
@@ -131,7 +131,7 @@ int watchdog_init(void)
u32 wdog_module = 0;
/* set timeout and enable watchdog */
- wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
+ wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT_MSECS);
#ifdef CONFIG_M5329
out_be16(&wdp->mr, wdog_module / 8192);
#else
diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c
index 1311f3967c9..844d2cd7600 100644
--- a/arch/m68k/cpu/mcf532x/cpu_init.c
+++ b/arch/m68k/cpu/mcf532x/cpu_init.c
@@ -37,34 +37,34 @@ void cpu_init_f(void)
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
@@ -102,8 +102,8 @@ int cpu_init_r(void)
rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
- out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
- out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
+ out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT);
+ out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP);
#endif
#ifdef CONFIG_MCFFEC
@@ -236,36 +236,36 @@ void cpu_init_f(void)
/* Port configuration */
out_8(&gpio->par_cs, 0);
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
- && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
+ && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
- && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
+ && defined(CFG_SYS_CS1_CTRL))
/* Latch chipselect */
setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
- && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
+ && defined(CFG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
- && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
+ && defined(CFG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
@@ -327,7 +327,7 @@ void uart_port_conf(int port)
clrbits_8(&gpio->par_feci2c, 0x00ff);
setbits_8(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
-#elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
+#elif defined(CFG_SYS_UART2_ALT3_GPIO)
clrbits_be16(&gpio->par_ssi, 0x0f00);
setbits_be16(&gpio->par_ssi,
GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c
index e2985792d96..32ffac08135 100644
--- a/arch/m68k/cpu/mcf532x/speed.c
+++ b/arch/m68k/cpu/mcf532x/speed.c
@@ -239,7 +239,7 @@ int clock_pll(int fsys, int flags)
* software workaround for SDRAM opeartion after exiting LIMP
* mode errata
*/
- out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
+ out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE);
#endif
/* wait for DQS logic to relock */
@@ -252,7 +252,7 @@ int clock_pll(int fsys, int flags)
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
- gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
+ gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000;
gd->cpu_clk = (gd->bus_clk * 3);
#ifdef CONFIG_SYS_I2C_FSL
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index 26728919160..72a2f99b7dd 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -98,11 +98,11 @@ _start:
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
#endif
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
@@ -131,7 +131,7 @@ _start:
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 9b3f9f0fe13..1ce244872f1 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -29,30 +29,30 @@ void init_fbcs(void)
fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
#if !defined(CONFIG_SERIAL_BOOT)
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
- out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
- out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
- out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
+#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
+ out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
+ out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
+ out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
/* Latch chipselect */
- out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
- out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
- out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
+ out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
+ out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
+ out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
- out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
- out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
- out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
+#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
+ out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
+ out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
+ out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
- out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
- out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
- out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
+#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
+ out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
+ out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
+ out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@@ -208,14 +208,14 @@ void cpu_init_f(void)
/* FlexBus Chipselect */
init_fbcs();
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
* also move to the new location.
*/
- if (CONFIG_SYS_CS0_BASE != 0)
- setvbr(CONFIG_SYS_CS0_BASE);
+ if (CFG_SYS_CS0_BASE != 0)
+ setvbr(CFG_SYS_CS0_BASE);
#endif
icache_enable();
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index aea8f3090fe..a083c3d45d2 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -27,10 +27,10 @@
#if defined(CONFIG_SERIAL_BOOT)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \
- CONFIG_SYS_INIT_RAM_ADDR)
+ CFG_SYS_INIT_RAM_ADDR)
#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \
- CONFIG_SYS_INIT_RAM_ADDR)
+ CFG_SYS_INIT_RAM_ADDR)
#endif
.text
@@ -123,18 +123,18 @@ asm_dram_init:
#ifdef CONFIG_SYS_NAND_BOOT
/* for assembly stack */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
#endif
#ifdef CONFIG_CF_SBF
- move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
+ move.l #CFG_SYS_INIT_RAM_ADDR, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
@@ -145,7 +145,7 @@ asm_dram_init:
move.l %d0, (%a2)
/* invalidate and disable cache */
- move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+ move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
@@ -153,17 +153,17 @@ asm_dram_init:
movec %d0, %ACR2
movec %d0, %ACR3
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/* Must disable global address */
move.l #0xFC008000, %a1
- move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #(CFG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
- move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #(CFG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
- move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+ move.l #(CFG_SYS_CS0_MASK), (%a1)
#endif
#endif /* CONFIG_CF_SBF */
@@ -216,8 +216,8 @@ asm_dspi_init:
move.l (%a1)+, %d5
move.l (%a1), %a4
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
- move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0
+ move.l #(CFG_SYS_SBFHDR_SIZE), %d4
move.l #0xFC05C02C, %a1 /* dspi status */
@@ -334,14 +334,14 @@ asm_nand_init:
movec %d0, %ACR2
movec %d0, %ACR3
-#ifdef CONFIG_SYS_CS0_BASE
+#ifdef CFG_SYS_CS0_BASE
/* Must disable global address */
move.l #0xFC008000, %a1
- move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #(CFG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
- move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #(CFG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
- move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+ move.l #(CFG_SYS_CS0_MASK), (%a1)
#endif
/* NAND port configuration */
@@ -442,10 +442,10 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
- move.l #CONFIG_SYS_FLASH_BASE, %d0
+ move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* initialize general use internal ram */
@@ -456,7 +456,7 @@ _start:
move.l %d0, (%a2)
/* invalidate and disable cache */
- move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
+ move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
@@ -464,7 +464,7 @@ _start:
movec %d0, %ACR2
movec %d0, %ACR3
#else
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
@@ -472,7 +472,7 @@ _start:
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
- move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
+ move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 17:50:52 +0000