diff options
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 3db3965fcff..d02b1e50bdf 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -125,7 +125,6 @@ */ #define CP0_TX39_CACHE $7 - /* Generic EntryLo bit definitions */ #define ENTRYLO_G (_ULCAST_(1) << 0) #define ENTRYLO_V (_ULCAST_(1) << 1) @@ -987,7 +986,6 @@ #define CP1_FENR $28 #define CP1_STATUS $31 - /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ @@ -1102,7 +1100,6 @@ #define FPU_CSR_RU 0x2 /* towards +Infinity */ #define FPU_CSR_RD 0x3 /* towards -Infinity */ - #ifndef __ASSEMBLY__ /* @@ -1261,7 +1258,6 @@ static inline void tlbinvf(void) ".set pop"); } - /* * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit @@ -1307,7 +1303,6 @@ do { \ : "r" (val), "i" (counter)); \ } while (0) - /* * Macros to access the system control coprocessor */ @@ -2403,7 +2398,6 @@ do { \ mfhi3; \ }) - #define mtlo0(x) \ ({ \ __asm__( \ |