diff options
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/global_data.h | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/processor.h | 16 | ||||
| -rw-r--r-- | arch/mips/lib/spl.c | 2 | ||||
| -rw-r--r-- | arch/mips/mach-jz47xx/jz4780/pll.c | 2 |
4 files changed, 3 insertions, 19 deletions
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index 147a95ecea8..265dd2a3ec4 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -44,6 +44,6 @@ struct arch_global_data { #include <asm-generic/global_data.h> -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("k0") #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 39a4f435a84..4c6322ed1c7 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -118,20 +118,4 @@ struct task_struct; */ #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) -#ifdef CONFIG_CPU_HAS_PREFETCH - -#define ARCH_HAS_PREFETCH - -static inline void prefetch(const void *addr) -{ - __asm__ __volatile__( - " .set mips4 \n" - " pref %0, (%1) \n" - " .set mips0 \n" - : - : "i" (Pref_Load), "r" (addr)); -} - -#endif - #endif /* _ASM_PROCESSOR_H */ diff --git a/arch/mips/lib/spl.c b/arch/mips/lib/spl.c index b4087546dd1..4949b17bd59 100644 --- a/arch/mips/lib/spl.c +++ b/arch/mips/lib/spl.c @@ -7,7 +7,7 @@ #include <log.h> #include <spl.h> -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); image_entry_noargs_t image_entry = diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c index 8ef00f99a10..0ff717b4595 100644 --- a/arch/mips/mach-jz47xx/jz4780/pll.c +++ b/arch/mips/mach-jz47xx/jz4780/pll.c @@ -327,7 +327,7 @@ /* BCH clock divider register */ #define CPM_BCHCDR_BPCS_BIT 30 #define CPM_BCHCDR_BPCS_MASK (0x3 << CPM_BCHCDR_BPCS_BIT) -#define CPM_BCHCDR_BPCS_STOP (0X0 << CPM_BCHCDR_BPCS_BIT) +#define CPM_BCHCDR_BPCS_STOP (0x0 << CPM_BCHCDR_BPCS_BIT) #define CPM_BCHCDR_BPCS_SRC_CLK (0x1 << CPM_BCHCDR_BPCS_BIT) #define CPM_BCHCDR_BPCS_MPLL (0x2 << CPM_BCHCDR_BPCS_BIT) #define CPM_BCHCDR_BPCS_EPLL (0x3 << CPM_BCHCDR_BPCS_BIT) |