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-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig189
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile6
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c5
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c58
-rw-r--r--arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c74
-rw-r--r--arch/powerpc/cpu/mpc85xx/pci.c23
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c10
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_serdes.c202
10 files changed, 14 insertions, 558 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 206ee76a50b..395423582a8 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -16,10 +16,6 @@ choice
prompt "Target select"
optional
-config TARGET_SBC8548
- bool "Support sbc8548"
- select ARCH_MPC8548
-
config TARGET_SOCRATES
bool "Support socrates"
select ARCH_MPC8544
@@ -48,25 +44,11 @@ config TARGET_P5040DS
imply CMD_SATA
imply PANIC_HANG
-config TARGET_MPC8541CDS
- bool "Support MPC8541CDS"
- select ARCH_MPC8541
- select FSL_VIA
-
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
select FSL_VIA
-config TARGET_MPC8555CDS
- bool "Support MPC8555CDS"
- select ARCH_MPC8555
- select FSL_VIA
-
-config TARGET_MPC8568MDS
- bool "Support MPC8568MDS"
- select ARCH_MPC8568
-
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
select ARCH_P1010
@@ -127,16 +109,6 @@ config TARGET_QEMU_PPCE500
select ARCH_QEMU_E500
select PHYS_64BIT
-config TARGET_T1023RDB
- bool "Support T1023RDB"
- select ARCH_T1023
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- select FSL_DDR_INTERACTIVE
- imply CMD_EEPROM
- imply PANIC_HANG
-
config TARGET_T1024RDB
bool "Support T1024RDB"
select ARCH_T1024
@@ -147,22 +119,6 @@ config TARGET_T1024RDB
imply CMD_EEPROM
imply PANIC_HANG
-config TARGET_T1040RDB
- bool "Support T1040RDB"
- select ARCH_T1040
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- imply PANIC_HANG
-
-config TARGET_T1040D4RDB
- bool "Support T1040D4RDB"
- select ARCH_T1040
- select BOARD_LATE_INIT if CHAIN_OF_TRUST
- select SUPPORT_SPL
- select PHYS_64BIT
- imply PANIC_HANG
-
config TARGET_T1042RDB
bool "Support T1042RDB"
select ARCH_T1042
@@ -205,13 +161,6 @@ config TARGET_T2080RDB
imply CMD_SATA
imply PANIC_HANG
-config TARGET_T4160RDB
- bool "Support T4160RDB"
- select ARCH_T4160
- select SUPPORT_SPL
- select PHYS_64BIT
- imply PANIC_HANG
-
config TARGET_T4240RDB
bool "Support T4240RDB"
select ARCH_T4240
@@ -229,20 +178,6 @@ config TARGET_KMCENT2
bool "Support kmcent2"
select VENDOR_KM
-config TARGET_XPEDITE520X
- bool "Support xpedite520x"
- select ARCH_MPC8548
-
-config TARGET_XPEDITE537X
- bool "Support xpedite537x"
- select ARCH_MPC8572
-# Use DDR3 controller with DDR2 DIMMs on this board
- select SYS_FSL_DDRC_GEN3
-
-config TARGET_XPEDITE550X
- bool "Support xpedite550x"
- select ARCH_P2020
-
config TARGET_UCP1020
bool "Support uCP1020"
select ARCH_P1020
@@ -384,14 +319,6 @@ config ARCH_MPC8540
select FSL_LAW
select SYS_FSL_HAS_DDR1
-config ARCH_MPC8541
- bool
- select FSL_LAW
- select SYS_FSL_HAS_DDR1
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
-
config ARCH_MPC8544
bool
select FSL_LAW
@@ -421,45 +348,11 @@ config ARCH_MPC8548
select SYS_PPC_E500_USE_DEBUG_TLB
imply CMD_REGINFO
-config ARCH_MPC8555
- bool
- select FSL_LAW
- select SYS_FSL_HAS_DDR1
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
-
config ARCH_MPC8560
bool
select FSL_LAW
select SYS_FSL_HAS_DDR1
-config ARCH_MPC8568
- bool
- select FSL_LAW
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR2
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
-
-config ARCH_MPC8572
- bool
- select FSL_LAW
- select SYS_FSL_ERRATUM_A004508
- select SYS_FSL_ERRATUM_A005125
- select SYS_FSL_ERRATUM_DDR_115
- select SYS_FSL_ERRATUM_DDR111_DDR134
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR2
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
- select SYS_PPC_E500_USE_DEBUG_TLB
- select FSL_ELBC
- imply CMD_NAND
-
config ARCH_P1010
bool
select FSL_LAW
@@ -738,27 +631,6 @@ config ARCH_P5040
config ARCH_QEMU_E500
bool
-config ARCH_T1023
- bool
- select E500MC
- select FSL_LAW
- select SYS_FSL_DDR_VER_50
- select SYS_FSL_ERRATUM_A008378
- select SYS_FSL_ERRATUM_A008109
- select SYS_FSL_ERRATUM_A009663
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_ERRATUM_ESDHC111
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_DDR4
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS2
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_5
- select FSL_IFC
- imply CMD_EEPROM
- imply CMD_NAND
- imply CMD_REGINFO
-
config ARCH_T1024
bool
select E500MC
@@ -853,29 +725,6 @@ config ARCH_T2080
imply CMD_REGINFO
imply FSL_SATA
-config ARCH_T4160
- bool
- select E500MC
- select E6500
- select FSL_LAW
- select SYS_FSL_DDR_VER_47
- select SYS_FSL_ERRATUM_A004468
- select SYS_FSL_ERRATUM_A005871
- select SYS_FSL_ERRATUM_A006379
- select SYS_FSL_ERRATUM_A006593
- select SYS_FSL_ERRATUM_A007186
- select SYS_FSL_ERRATUM_A007798
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_QORIQ_CHASSIS2
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_4
- select SYS_PPC64
- select FSL_IFC
- imply CMD_NAND
- imply CMD_REGINFO
-
config ARCH_T4240
bool
select E500MC
@@ -944,8 +793,7 @@ config NXP_ESBC
config MAX_CPUS
int "Maximum number of CPUs permitted for MPC85xx"
default 12 if ARCH_T4240
- default 8 if ARCH_P4080 || \
- ARCH_T4160
+ default 8 if ARCH_P4080
default 4 if ARCH_B4860 || \
ARCH_P2041 || \
ARCH_P3041 || \
@@ -955,14 +803,12 @@ config MAX_CPUS
ARCH_T2080
default 2 if ARCH_B4420 || \
ARCH_BSC9132 || \
- ARCH_MPC8572 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1023 || \
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020 || \
- ARCH_T1023 || \
ARCH_T1024
default 1
help
@@ -979,13 +825,9 @@ config SYS_CCSRBAR_DEFAULT
ARCH_C29X || \
ARCH_MPC8536 || \
ARCH_MPC8540 || \
- ARCH_MPC8541 || \
ARCH_MPC8544 || \
ARCH_MPC8548 || \
- ARCH_MPC8555 || \
ARCH_MPC8560 || \
- ARCH_MPC8568 || \
- ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
ARCH_P1020 || \
@@ -1000,12 +842,10 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5040 || \
- ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T2080 || \
- ARCH_T4160 || \
ARCH_T4240
default 0xe0000000 if ARCH_QEMU_E500
help
@@ -1190,17 +1030,14 @@ config SYS_FSL_NUM_LAWS
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_T2080 || \
- ARCH_T4160 || \
ARCH_T4240
- default 16 if ARCH_T1023 || \
- ARCH_T1024 || \
+ default 16 if ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042
default 12 if ARCH_BSC9131 || \
ARCH_BSC9132 || \
ARCH_C29X || \
ARCH_MPC8536 || \
- ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
ARCH_P1020 || \
@@ -1210,11 +1047,8 @@ config SYS_FSL_NUM_LAWS
ARCH_P1025 || \
ARCH_P2020
default 10 if ARCH_MPC8544 || \
- ARCH_MPC8548 || \
- ARCH_MPC8568
+ ARCH_MPC8548
default 8 if ARCH_MPC8540 || \
- ARCH_MPC8541 || \
- ARCH_MPC8555 || \
ARCH_MPC8560
help
Number of local access windows. This is fixed per SoC.
@@ -1250,8 +1084,7 @@ config SYS_PPC_E500_DEBUG_TLB
depends on SYS_PPC_E500_USE_DEBUG_TLB
default 0 if ARCH_MPC8544 || ARCH_MPC8548
default 1 if ARCH_MPC8536
- default 2 if ARCH_MPC8572 || \
- ARCH_P1011 || \
+ default 2 if ARCH_P1011 || \
ARCH_P1020 || \
ARCH_P1021 || \
ARCH_P1024 || \
@@ -1274,10 +1107,8 @@ config SYS_FSL_IFC_CLK_DIV
default 2 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_T1024 || \
- ARCH_T1023 || \
ARCH_T1040 || \
ARCH_T1042 || \
- ARCH_T4160 || \
ARCH_T4240
default 1
help
@@ -1287,9 +1118,8 @@ config SYS_FSL_IFC_CLK_DIV
config SYS_FSL_LBC_CLK_DIV
int "Divider of platform clock"
depends on FSL_ELBC || ARCH_MPC8540 || \
- ARCH_MPC8548 || ARCH_MPC8541 || \
- ARCH_MPC8555 || ARCH_MPC8560 || \
- ARCH_MPC8568
+ ARCH_MPC8548 || \
+ ARCH_MPC8560
default 2 if ARCH_P2041 || \
ARCH_P3041 || \
@@ -1306,10 +1136,7 @@ config FSL_VIA
source "board/emulation/qemu-ppce500/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
-source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
-source "board/freescale/mpc8555cds/Kconfig"
-source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
@@ -1319,11 +1146,7 @@ source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/keymile/Kconfig"
-source "board/sbc8548/Kconfig"
source "board/socrates/Kconfig"
-source "board/xes/xpedite520x/Kconfig"
-source "board/xes/xpedite537x/Kconfig"
-source "board/xes/xpedite550x/Kconfig"
source "board/Arcturus/ucp1020/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index b9d87ddb655..993e4873184 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -42,12 +42,10 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
-obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
-obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
@@ -62,8 +60,6 @@ obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
-obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
-obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
@@ -77,13 +73,11 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
-obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
-obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index fc25bb28ad1..610a8ec43f5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -301,8 +301,7 @@ int checkcpu (void)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
- defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
unsigned long val, msr;
/*
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7d168e3c9a0..3f2fc062b2b 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -527,8 +527,7 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
-#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
- defined(CONFIG_ARCH_T4160)
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240)
void fdt_fixup_dma3(void *blob)
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
@@ -545,7 +544,7 @@ void fdt_fixup_dma3(void *blob)
case 0x29:
case 0x2d:
case 0x2e:
-#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#elif defined(CONFIG_ARCH_T4240)
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index ee5015ec8f3..5bf0047930f 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -392,7 +392,7 @@ const char *serdes_clock_to_string(u32 clock)
case SRDS_PLLCR0_RFCK_SEL_161_13:
return "161.1328123";
default:
-#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS)
+#if defined(CONFIG_TARGET_T4240QDS)
return "???";
#else
return "122.88";
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
deleted file mode 100644
index 81b66c3fa6a..00000000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
+++ /dev/null
@@ -1,58 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 8
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
deleted file mode 100644
index 1b4e6149184..00000000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 8
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
- [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
- [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
- [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
- [0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
- [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
- serdes1_prtcl_map |= (1 << SGMII_TSEC1);
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
- serdes1_prtcl_map |= (1 << SGMII_TSEC2);
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- serdes1_prtcl_map |= (1 << SGMII_TSEC3);
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
- serdes1_prtcl_map |= (1 << SGMII_TSEC4);
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index 9a6fc13b73f..b7835c0fee5 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -120,29 +120,6 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pci_register_hose(hose);
-#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
- /*
- * This is a SW workaround for an apparent HW problem
- * in the PCI controller on the MPC85555/41 CDS boards.
- * The first config cycle must be to a valid, known
- * device on the PCI bus in order to trick the PCI
- * controller state machine into a known valid state.
- * Without this, the first config cycle has the chance
- * of hanging the controller permanently, just leaving
- * it in a semi-working state, or leaving it working.
- *
- * Pick on the Tundra, Device 17, to get it right.
- */
- {
- u8 header_type;
-
- pci_hose_read_config_byte(hose,
- PCI_BDF(0,BRIDGE_ID,0),
- PCI_HEADER_TYPE,
- &header_type);
- }
-#endif
-
hose->last_busno = pci_hose_scan(hose);
#ifdef CONFIG_MPC85XX_PCI2
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 864c53ce2ec..e229a5c5a7e 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -126,8 +126,7 @@ void get_sys_info(sys_info_t *sys_info)
* it uses 6.
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
-#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
- defined(CONFIG_ARCH_T2080)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T2080)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
@@ -201,7 +200,7 @@ void get_sys_info(sys_info_t *sys_info)
defined(CONFIG_ARCH_T2080)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
-#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#elif defined(CONFIG_ARCH_T1024)
#define FM1_CLK_SEL 0x00000007
#define FM1_CLK_SHIFT 0
#else
@@ -211,7 +210,7 @@ void get_sys_info(sys_info_t *sys_info)
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
-#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#if defined(CONFIG_ARCH_T1024)
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
#else
rcw_tmp = in_be32(&gur->rcwsr[7]);
@@ -607,8 +606,7 @@ int get_clocks(void)
* for that SOC. This information is taken from application note
* AN2919.
*/
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
- defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_ARCH_MPC8544)
/*
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index a8c0c47f4af..61402e84ef6 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -262,208 +262,6 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_ARCH_T4160)
-static const struct serdes_config serdes1_cfg_tbl[] = {
- /* SerDes 1 */
- {1, {NONE, NONE, NONE, NONE,
- XAUI_FM1_MAC10, XAUI_FM1_MAC10,
- XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
- {2, {NONE, NONE, NONE, NONE,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {4, {NONE, NONE, NONE, NONE,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {27, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {28, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {35, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {36, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {37, {NONE, NONE, NONE, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE} },
- {38, {NONE, NONE, NONE, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE} },
- {}
-};
-static const struct serdes_config serdes2_cfg_tbl[] = {
- /* SerDes 2 */
- {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- NONE, NONE} },
- {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {37, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {38, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {55, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {56, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {57, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- NONE, NONE} },
- {}
-};
-static const struct serdes_config serdes3_cfg_tbl[] = {
- /* SerDes 3 */
- {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
- {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
- {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
- {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
- {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {11, {NONE, NONE, NONE, NONE,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {12, {NONE, NONE, NONE, NONE,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {15, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {16, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {17, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {}
-};
-static const struct serdes_config serdes4_cfg_tbl[] = {
- /* SerDes 4 */
- {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
- {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
- {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
- {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
- {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
- {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
- {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
- {}
-}
-;
#else
#error "Need to define SerDes protocol"
#endif
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-23 12:02:53 +0000