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-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig8
-rw-r--r--arch/powerpc/cpu/mpc83xx/Makefile2
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu_init.c11
-rw-r--r--arch/powerpc/cpu/mpc83xx/qe_io.c98
4 files changed, 86 insertions, 33 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 18808da37dd..2bae08e2786 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -101,34 +101,42 @@ config TARGET_IDS8313
config TARGET_KMETER1
bool "Support kmeter1"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMCOGE5NE
bool "Support kmcoge5ne"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMTEGR1
bool "Support kmtegr1"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TUXX1
bool "Support tuxx1"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMSUPX5
bool "Support kmsupx5"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TUGE1
bool "Support tuge1"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMOPTI2
bool "Support kmopti2"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMTEPR2
bool "Support kmtepr2"
select VENDOR_KM
+ select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TQM834X
bool "Support TQM834x"
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index 304029977e5..aeb42b109d0 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -27,7 +27,9 @@ obj-y += cpu_init.o
obj-y += speed.o
obj-y += interrupts.o
obj-y += ecc.o
+ifndef CONFIG_PINCTRL
obj-$(CONFIG_QE) += qe_io.o
+endif
obj-$(CONFIG_FSL_SERDES) += serdes.o
ifndef CONFIG_ARCH_MPC8308
obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 438b14b162e..840f907acb8 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -9,10 +9,14 @@
#include <ioports.h>
#include <asm/io.h>
#include <asm/processor.h>
+#include <fsl_qe.h>
#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-ci.h>
#endif
#include <linux/delay.h>
+#ifdef CONFIG_QE
+#include <fsl_qe.h>
+#endif
#include "lblaw/lblaw.h"
#include "elbc/elbc.h"
@@ -26,9 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
-extern void qe_init(uint qe_base);
-extern void qe_reset(void);
+#if !defined(CONFIG_PINCTRL)
static void config_qe_ioports(void)
{
u8 port, pin;
@@ -45,6 +48,7 @@ static void config_qe_ioports(void)
}
}
#endif
+#endif
/*
* Breathe some life into the CPU...
@@ -191,10 +195,13 @@ void cpu_init_f (volatile immap_t * im)
__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
#endif
+#if !defined(CONFIG_PINCTRL)
#ifdef CONFIG_QE
/* Config QE ioports */
config_qe_ioports();
#endif
+#endif
+
/* Set up preliminary BR/OR regs */
init_early_memctl_regs();
diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c
index 88aa6895511..52360703a7d 100644
--- a/arch/powerpc/cpu/mpc83xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc83xx/qe_io.c
@@ -12,57 +12,93 @@
#include <asm/immap_83xx.h>
#define NUM_OF_PINS 32
-void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+
+/** qe_cfg_iopin configure one io pin setting
+ *
+ * @par_io: pointer to parallel I/O base
+ * @port: io pin port
+ * @pin: io pin number which get configured
+ * @dir: direction of io pin 2 bits valid
+ * 00 = pin disabled
+ * 01 = output
+ * 10 = input
+ * 11 = pin is I/O
+ * @open_drain: is pin open drain
+ * @assign: pin assignment registers select the function of the pin
+ */
+static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
+ int open_drain, int assign)
{
- u32 pin_2bit_mask;
- u32 pin_2bit_dir;
- u32 pin_2bit_assign;
- u32 pin_1bit_mask;
- u32 tmp_val;
- volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
+ u32 dbit_mask;
+ u32 dbit_dir;
+ u32 dbit_asgn;
+ u32 bit_mask;
+ u32 tmp_val;
+ int offset;
+
+ offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
/* Calculate pin location and 2bit mask and dir */
- pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
- pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+ dbit_mask = (u32)(0x3 << offset);
+ dbit_dir = (u32)(dir << offset);
/* Setup the direction */
- tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
+ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
in_be32(&par_io->ioport[port].dir2) :
in_be32(&par_io->ioport[port].dir1);
- if (pin > (NUM_OF_PINS/2) -1) {
- out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val);
- out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val);
+ if (pin > (NUM_OF_PINS / 2) - 1) {
+ out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
+ out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
} else {
- out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val);
- out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val);
+ out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
+ out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
}
/* Calculate pin location for 1bit mask */
- pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
+ bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
/* Setup the open drain */
tmp_val = in_be32(&par_io->ioport[port].podr);
- if (open_drain) {
- out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val);
- } else {
- out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val);
- }
+ if (open_drain)
+ out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
+ else
+ out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
/* Setup the assignment */
- tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
- in_be32(&par_io->ioport[port].ppar2):
+ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+ in_be32(&par_io->ioport[port].ppar2) :
in_be32(&par_io->ioport[port].ppar1);
- pin_2bit_assign = (u32)(assign
- << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
+ dbit_asgn = (u32)(assign << offset);
/* Clear and set 2 bits mask */
- if (pin > (NUM_OF_PINS/2) - 1) {
- out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val);
- out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val);
+ if (pin > (NUM_OF_PINS / 2) - 1) {
+ out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
+ out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
} else {
- out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val);
- out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val);
+ out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
+ out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
}
}
+
+#if !defined(CONFIG_PINCTRL)
+/** qe_config_iopin configure one io pin setting
+ *
+ * @port: io pin port
+ * @pin: io pin number which get configured
+ * @dir: direction of io pin 2 bits valid
+ * 00 = pin disabled
+ * 01 = output
+ * 10 = input
+ * 11 = pin is I/O
+ * @open_drain: is pin open drain
+ * @assign: pin assignment registers select the function of the pin
+ */
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
+
+ qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
+}
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-23 08:45:55 +0000