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-rw-r--r--arch/powerpc/cpu/mpc83xx/initreg/initreg.h8
-rw-r--r--arch/powerpc/cpu/mpc83xx/interrupts.c3
-rw-r--r--arch/powerpc/cpu/mpc83xx/start.S72
-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S24
5 files changed, 55 insertions, 54 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
index 63aa5c94669..ea1176e7fe1 100644
--- a/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
+++ b/arch/powerpc/cpu/mpc83xx/initreg/initreg.h
@@ -13,7 +13,7 @@
#define SPCR_TSECBDP_MASK 0x00000C00
#define SPCR_TSECEP_MASK 0x00000300
- const __be32 spcr_mask =
+ static const __be32 spcr_mask =
#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
SPCR_OPT_MASK |
#endif
@@ -27,7 +27,7 @@
SPCR_TSEC2EP_MASK |
#endif
0;
- const __be32 spcr_val =
+ static const __be32 spcr_val =
#if defined(CONFIG_SPCR_OPT) && !defined(CONFIG_SPCR_OPT_UNSET)
CONFIG_SPCR_OPT |
#endif
@@ -42,7 +42,7 @@
#endif
0;
- const __be32 lcrr_mask =
+ static const __be32 lcrr_mask =
#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
LCRR_DBYP |
#endif
@@ -60,7 +60,7 @@
#endif
0;
- const __be32 lcrr_val =
+ static const __be32 lcrr_val =
#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
CONFIG_LCRR_DBYP |
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/interrupts.c b/arch/powerpc/cpu/mpc83xx/interrupts.c
index af517213f17..bb37a1332c8 100644
--- a/arch/powerpc/cpu/mpc83xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc83xx/interrupts.c
@@ -12,6 +12,7 @@
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
+#include "initreg/initreg.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -29,7 +30,7 @@ void interrupt_init_cpu (unsigned *decrementer_count)
/* Enable e300 time base */
- immr->sysconf.spcr |= 0x00400000;
+ immr->sysconf.spcr |= SPCR_TBEN_MASK;
}
/*
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 78762f000df..0d8bc464117 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -550,133 +550,133 @@ init_e300_core: /* time t 10 */
/* setup_bats - set them up to some initial state */
.globl setup_bats
setup_bats:
- addis r0, r0, 0x0000
+ addis r0, 0, 0x0000
/* IBAT 0 */
- addis r4, r0, CFG_SYS_IBAT0L@h
+ addis r4, 0, CFG_SYS_IBAT0L@h
ori r4, r4, CFG_SYS_IBAT0L@l
- addis r3, r0, CFG_SYS_IBAT0U@h
+ addis r3, 0, CFG_SYS_IBAT0U@h
ori r3, r3, CFG_SYS_IBAT0U@l
mtspr IBAT0L, r4
mtspr IBAT0U, r3
/* DBAT 0 */
- addis r4, r0, CFG_SYS_DBAT0L@h
+ addis r4, 0, CFG_SYS_DBAT0L@h
ori r4, r4, CFG_SYS_DBAT0L@l
- addis r3, r0, CFG_SYS_DBAT0U@h
+ addis r3, 0, CFG_SYS_DBAT0U@h
ori r3, r3, CFG_SYS_DBAT0U@l
mtspr DBAT0L, r4
mtspr DBAT0U, r3
/* IBAT 1 */
- addis r4, r0, CFG_SYS_IBAT1L@h
+ addis r4, 0, CFG_SYS_IBAT1L@h
ori r4, r4, CFG_SYS_IBAT1L@l
- addis r3, r0, CFG_SYS_IBAT1U@h
+ addis r3, 0, CFG_SYS_IBAT1U@h
ori r3, r3, CFG_SYS_IBAT1U@l
mtspr IBAT1L, r4
mtspr IBAT1U, r3
/* DBAT 1 */
- addis r4, r0, CFG_SYS_DBAT1L@h
+ addis r4, 0, CFG_SYS_DBAT1L@h
ori r4, r4, CFG_SYS_DBAT1L@l
- addis r3, r0, CFG_SYS_DBAT1U@h
+ addis r3, 0, CFG_SYS_DBAT1U@h
ori r3, r3, CFG_SYS_DBAT1U@l
mtspr DBAT1L, r4
mtspr DBAT1U, r3
/* IBAT 2 */
- addis r4, r0, CFG_SYS_IBAT2L@h
+ addis r4, 0, CFG_SYS_IBAT2L@h
ori r4, r4, CFG_SYS_IBAT2L@l
- addis r3, r0, CFG_SYS_IBAT2U@h
+ addis r3, 0, CFG_SYS_IBAT2U@h
ori r3, r3, CFG_SYS_IBAT2U@l
mtspr IBAT2L, r4
mtspr IBAT2U, r3
/* DBAT 2 */
- addis r4, r0, CFG_SYS_DBAT2L@h
+ addis r4, 0, CFG_SYS_DBAT2L@h
ori r4, r4, CFG_SYS_DBAT2L@l
- addis r3, r0, CFG_SYS_DBAT2U@h
+ addis r3, 0, CFG_SYS_DBAT2U@h
ori r3, r3, CFG_SYS_DBAT2U@l
mtspr DBAT2L, r4
mtspr DBAT2U, r3
/* IBAT 3 */
- addis r4, r0, CFG_SYS_IBAT3L@h
+ addis r4, 0, CFG_SYS_IBAT3L@h
ori r4, r4, CFG_SYS_IBAT3L@l
- addis r3, r0, CFG_SYS_IBAT3U@h
+ addis r3, 0, CFG_SYS_IBAT3U@h
ori r3, r3, CFG_SYS_IBAT3U@l
mtspr IBAT3L, r4
mtspr IBAT3U, r3
/* DBAT 3 */
- addis r4, r0, CFG_SYS_DBAT3L@h
+ addis r4, 0, CFG_SYS_DBAT3L@h
ori r4, r4, CFG_SYS_DBAT3L@l
- addis r3, r0, CFG_SYS_DBAT3U@h
+ addis r3, 0, CFG_SYS_DBAT3U@h
ori r3, r3, CFG_SYS_DBAT3U@l
mtspr DBAT3L, r4
mtspr DBAT3U, r3
#ifdef CONFIG_HIGH_BATS
/* IBAT 4 */
- addis r4, r0, CFG_SYS_IBAT4L@h
+ addis r4, 0, CFG_SYS_IBAT4L@h
ori r4, r4, CFG_SYS_IBAT4L@l
- addis r3, r0, CFG_SYS_IBAT4U@h
+ addis r3, 0, CFG_SYS_IBAT4U@h
ori r3, r3, CFG_SYS_IBAT4U@l
mtspr IBAT4L, r4
mtspr IBAT4U, r3
/* DBAT 4 */
- addis r4, r0, CFG_SYS_DBAT4L@h
+ addis r4, 0, CFG_SYS_DBAT4L@h
ori r4, r4, CFG_SYS_DBAT4L@l
- addis r3, r0, CFG_SYS_DBAT4U@h
+ addis r3, 0, CFG_SYS_DBAT4U@h
ori r3, r3, CFG_SYS_DBAT4U@l
mtspr DBAT4L, r4
mtspr DBAT4U, r3
/* IBAT 5 */
- addis r4, r0, CFG_SYS_IBAT5L@h
+ addis r4, 0, CFG_SYS_IBAT5L@h
ori r4, r4, CFG_SYS_IBAT5L@l
- addis r3, r0, CFG_SYS_IBAT5U@h
+ addis r3, 0, CFG_SYS_IBAT5U@h
ori r3, r3, CFG_SYS_IBAT5U@l
mtspr IBAT5L, r4
mtspr IBAT5U, r3
/* DBAT 5 */
- addis r4, r0, CFG_SYS_DBAT5L@h
+ addis r4, 0, CFG_SYS_DBAT5L@h
ori r4, r4, CFG_SYS_DBAT5L@l
- addis r3, r0, CFG_SYS_DBAT5U@h
+ addis r3, 0, CFG_SYS_DBAT5U@h
ori r3, r3, CFG_SYS_DBAT5U@l
mtspr DBAT5L, r4
mtspr DBAT5U, r3
/* IBAT 6 */
- addis r4, r0, CFG_SYS_IBAT6L@h
+ addis r4, 0, CFG_SYS_IBAT6L@h
ori r4, r4, CFG_SYS_IBAT6L@l
- addis r3, r0, CFG_SYS_IBAT6U@h
+ addis r3, 0, CFG_SYS_IBAT6U@h
ori r3, r3, CFG_SYS_IBAT6U@l
mtspr IBAT6L, r4
mtspr IBAT6U, r3
/* DBAT 6 */
- addis r4, r0, CFG_SYS_DBAT6L@h
+ addis r4, 0, CFG_SYS_DBAT6L@h
ori r4, r4, CFG_SYS_DBAT6L@l
- addis r3, r0, CFG_SYS_DBAT6U@h
+ addis r3, 0, CFG_SYS_DBAT6U@h
ori r3, r3, CFG_SYS_DBAT6U@l
mtspr DBAT6L, r4
mtspr DBAT6U, r3
/* IBAT 7 */
- addis r4, r0, CFG_SYS_IBAT7L@h
+ addis r4, 0, CFG_SYS_IBAT7L@h
ori r4, r4, CFG_SYS_IBAT7L@l
- addis r3, r0, CFG_SYS_IBAT7U@h
+ addis r3, 0, CFG_SYS_IBAT7U@h
ori r3, r3, CFG_SYS_IBAT7U@l
mtspr IBAT7L, r4
mtspr IBAT7U, r3
/* DBAT 7 */
- addis r4, r0, CFG_SYS_DBAT7L@h
+ addis r4, 0, CFG_SYS_DBAT7L@h
ori r4, r4, CFG_SYS_DBAT7L@l
- addis r3, r0, CFG_SYS_DBAT7U@h
+ addis r3, 0, CFG_SYS_DBAT7U@h
ori r3, r3, CFG_SYS_DBAT7U@l
mtspr DBAT7L, r4
mtspr DBAT7U, r3
@@ -1057,7 +1057,7 @@ lock_ram_in_cache:
(CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
- dcbz r0, r3
+ dcbz 0, r3
addi r3, r3, 32
bdnz 1b
@@ -1078,8 +1078,8 @@ unlock_ram_in_cache:
li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \
(CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
-1: icbi r0, r3
- dcbi r0, r3
+1: icbi 0, r3
+ dcbi 0, r3
addi r3, r3, 32
bdnz 1b
sync /* Wait for all icbi to complete on bus */
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index bed465cb2cb..8918a401fac 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -412,7 +412,7 @@ void cpu_mp_lmb_reserve(void)
{
u32 bootpg = determine_mp_bootpg(NULL);
- lmb_reserve(bootpg, 4096);
+ lmb_reserve(bootpg, 4096, LMB_NONE);
}
void setup_mp(void)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 89bce5bed69..5234e42dc28 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1203,12 +1203,12 @@ switch_as:
mtctr r2
li r0,0
1:
- dcbz r0,r3
+ dcbz 0,r3
#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
- dcbtls 2, r0, r3
- dcbtls 0, r0, r3
+ dcbtls 2, 0, r3
+ dcbtls 0, 0, r3
#else
- dcbtls 0, r0, r3
+ dcbtls 0, 0, r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
@@ -1514,7 +1514,7 @@ out16:
/*------------------------------------------------------------------------------- */
.globl out16r
out16r:
- sthbrx r4,r0,r3
+ sthbrx r4,0,r3
sync
blr
@@ -1534,7 +1534,7 @@ out32:
/*------------------------------------------------------------------------------- */
.globl out32r
out32r:
- stwbrx r4,r0,r3
+ stwbrx r4,0,r3
sync
blr
@@ -1553,7 +1553,7 @@ in16:
/*------------------------------------------------------------------------------- */
.globl in16r
in16r:
- lhbrx r3,r0,r3
+ lhbrx r3,0,r3
blr
/*------------------------------------------------------------------------------- */
@@ -1571,7 +1571,7 @@ in32:
/*------------------------------------------------------------------------------- */
.globl in32r
in32r:
- lwbrx r3,r0,r3
+ lwbrx r3,0,r3
blr
#endif /* !MINIMAL_SPL */
@@ -1832,12 +1832,12 @@ unlock_ram_in_cache:
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
-1: dcbi r0,r3
+1: dcbi 0,r3
#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
- dcblc 2, r0, r3
- dcblc 0, r0, r3
+ dcblc 2, 0, r3
+ dcblc 0, 0, r3
#else
- dcblc r0,r3
+ dcblc 0,r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 21:13:19 +0000