summaryrefslogtreecommitdiff
path: root/arch/powerpc/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/cpu')
-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig6
-rw-r--r--arch/powerpc/cpu/mpc83xx/Makefile2
-rw-r--r--arch/powerpc/cpu/mpc83xx/ecc.c2
-rw-r--r--arch/powerpc/cpu/mpc83xx/spd_sdram.c10
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig15
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c8
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c9
-rw-r--r--arch/powerpc/cpu/mpc8xx/Kconfig2
8 files changed, 34 insertions, 20 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 083febe5bb3..7c922b23096 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -131,6 +131,7 @@ config MPC83XX_LDP_PIN
config ARCH_MPC830X
bool
select MPC83XX_SDHC_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8308
bool
@@ -154,6 +155,7 @@ config ARCH_MPC831X
select MPC83XX_PCI_SUPPORT
select MPC83XX_TSEC1_SUPPORT
select MPC83XX_TSEC2_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8313
bool
@@ -165,9 +167,11 @@ config ARCH_MPC832X
bool
select MPC83XX_QUICC_ENGINE
select MPC83XX_PCI_SUPPORT
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC834X
bool
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC8349
bool
@@ -184,6 +188,7 @@ config ARCH_MPC8360
select MPC83XX_PCI_SUPPORT
select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C
+ select SYS_CACHE_SHIFT_5
config ARCH_MPC837X
bool
@@ -196,6 +201,7 @@ config ARCH_MPC837X
select MPC83XX_SATA_SUPPORT
select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C
+ select SYS_CACHE_SHIFT_5
select FSL_ELBC
config SYS_IMMR
diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile
index aeb42b109d0..7c4ef7657e5 100644
--- a/arch/powerpc/cpu/mpc83xx/Makefile
+++ b/arch/powerpc/cpu/mpc83xx/Makefile
@@ -26,7 +26,7 @@ obj-y += cpu.o
obj-y += cpu_init.o
obj-y += speed.o
obj-y += interrupts.o
-obj-y += ecc.o
+obj-$(CONFIG_DDR_ECC_CMD) += ecc.o
ifndef CONFIG_PINCTRL
obj-$(CONFIG_QE) += qe_io.o
endif
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 7a8ec7f42f1..3e24752e2f6 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -11,7 +11,6 @@
#include <mpc83xx.h>
#include <command.h>
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
void ecc_print_status(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
@@ -386,4 +385,3 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc,
" - writes pattern injecting errors with word access\n"
" - writes pattern with word access, generates error\n"
" - disables injects\n" " - re-inits memory");
-#endif
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index a861e8dd2dd..e12043b2609 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -834,12 +834,6 @@ long int spd_sdram()
#endif
debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
-#if defined(CONFIG_DDR_2T_TIMING)
- /*
- * Enable 2T timing by setting sdram_cfg[16].
- */
- sdram_cfg |= SDRAM_CFG_2T_EN;
-#endif
/* Enable controller, and GO! */
ddr->sdram_cfg = sdram_cfg;
sync();
@@ -914,16 +908,12 @@ void ddr_enable_ecc(unsigned int dram_size)
pattern[0] = 0xdeadbeef;
pattern[1] = 0xdeadbeef;
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
- dma_meminit(pattern[0], dram_size);
-#else
debug("ddr init: CPU FP write method\n");
size = dram_size;
for (p = 0; p < (u64*)(size); p++) {
ppcDWstore((u32*)p, pattern);
}
sync();
-#endif
t_end = get_tbms();
icache_disable();
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index cbc8ba8d5af..cc2e4ff6472 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -48,6 +48,7 @@ config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
select FSL_VIA
+ select SYS_CACHE_SHIFT_5
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
@@ -322,6 +323,7 @@ config ARCH_MPC8540
config ARCH_MPC8544
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2
@@ -356,6 +358,7 @@ config ARCH_MPC8560
config ARCH_P1010
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
@@ -401,6 +404,7 @@ config ARCH_P1011
config ARCH_P1020
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001
@@ -496,6 +500,7 @@ config ARCH_P1025
config ARCH_P2020
bool
select FSL_LAW
+ select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
@@ -516,6 +521,7 @@ config ARCH_P2041
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
select SYS_FSL_ERRATUM_A005275
@@ -540,6 +546,7 @@ config ARCH_P3041
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
@@ -569,6 +576,7 @@ config ARCH_P4080
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004580
@@ -607,6 +615,7 @@ config ARCH_P5040
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004699
@@ -630,11 +639,13 @@ config ARCH_P5040
config ARCH_QEMU_E500
bool
+ select SYS_CACHE_SHIFT_5
config ARCH_T1024
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
@@ -657,6 +668,7 @@ config ARCH_T1040
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
@@ -679,6 +691,7 @@ config ARCH_T1042
bool
select E500MC
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
@@ -702,6 +715,7 @@ config ARCH_T2080
select E500MC
select E6500
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
@@ -731,6 +745,7 @@ config ARCH_T4240
select E500MC
select E6500
select FSL_LAW
+ select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 610a8ec43f5..cd32290410f 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -11,6 +11,7 @@
#include <config.h>
#include <common.h>
#include <cpu_func.h>
+#include <clock_legacy.h>
#include <init.h>
#include <irq_func.h>
#include <log.h>
@@ -52,7 +53,8 @@ int checkcpu (void)
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
+ defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
@@ -70,12 +72,12 @@ int checkcpu (void)
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#else /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
-#endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
#endif /* CONFIG_FSL_CORENET */
unsigned int i, core, nr_cores = cpu_numcores();
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e229a5c5a7e..1fe914a4e43 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <cpu_func.h>
+#include <clock_legacy.h>
#include <ppc_asm.tmpl>
#include <asm/global_data.h>
#include <linux/compiler.h>
@@ -104,8 +105,8 @@ void get_sys_info(sys_info_t *sys_info)
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
else
#endif
-#ifdef CONFIG_DDR_CLK_FREQ
- sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
+ sys_info->freq_ddrbus = get_board_ddr_clk();
#else
sys_info->freq_ddrbus = sysclk;
#endif
@@ -538,12 +539,12 @@ void get_sys_info(sys_info_t *sys_info)
/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
sys_info->freq_ddrbus = sys_info->freq_systembus;
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
{
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
if (ddr_ratio != 0x7)
- sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk();
}
#endif
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index f1123173765..936cbda11bc 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -19,9 +19,11 @@ choice
config MPC866
bool "MPC866"
+ select SYS_CACHE_SHIFT_4
config MPC885
bool "MPC885"
+ select SYS_CACHE_SHIFT_4
endchoice
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-21 13:51:56 +0000