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-rw-r--r--arch/powerpc/include/asm/cache.h7
-rw-r--r--arch/powerpc/include/asm/config.h9
2 files changed, 0 insertions, 16 deletions
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index ac8eeb4caa5..f753ddf799e 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -25,13 +25,6 @@
*/
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-/*
- * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
- */
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
-#endif
-
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 2c96378efef..a97b72de1b8 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -26,15 +26,6 @@
#endif
#endif
-/* Check if boards need to enable FSL DMA engine for SDRAM init */
-#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
-#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
- ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
- !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-#define CONFIG_FSL_DMA
-#endif
-#endif
-
/*
* Provide a default boot page translation virtual address that lines up with
* Freescale's default e500 reset page.