diff options
Diffstat (limited to 'arch/powerpc')
26 files changed, 481 insertions, 592 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 2bae08e2786..ff85834c460 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -28,11 +28,6 @@ config TARGET_CADDY2 bool "Support caddy2" select ARCH_MPC8349 -config TARGET_MPC8308RDB - bool "Support MPC8308RDB" - select ARCH_MPC8308 - select SYS_FSL_ERRATUM_ESDHC111 - config TARGET_MPC8313ERDB_NOR bool "Support MPC8313ERDB_NOR" select ARCH_MPC8313 @@ -75,18 +70,6 @@ config TARGET_MPC8349EMDS_SDRAM select SYS_FSL_DDR_BE select SYS_FSL_HAS_DDR2 -config TARGET_MPC8349ITX - bool "Support MPC8349ITX" - select ARCH_MPC8349 - imply CMD_IRQ - -config TARGET_MPC837XEMDS - bool "Support MPC837XEMDS" - select ARCH_MPC837X - select BOARD_EARLY_INIT_F - imply CMD_SATA - imply FSL_SATA - config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X @@ -142,16 +125,6 @@ config TARGET_TQM834X bool "Support TQM834x" select ARCH_MPC8349 -config TARGET_HRCON - bool "Support hrcon" - select ARCH_MPC8308 - select SYS_FSL_ERRATUM_ESDHC111 - -config TARGET_STRIDER - bool "Support strider" - select ARCH_MPC8308 - select SYS_FSL_ERRATUM_ESDHC111 - imply CMD_PCA953X config TARGET_GAZERBEAM bool "Support gazerbeam" @@ -330,14 +303,11 @@ config FSL_ELBC bool source "board/esd/vme8349/Kconfig" -source "board/freescale/mpc8308rdb/Kconfig" source "board/freescale/mpc8313erdb/Kconfig" source "board/freescale/mpc8315erdb/Kconfig" source "board/freescale/mpc8323erdb/Kconfig" source "board/freescale/mpc832xemds/Kconfig" source "board/freescale/mpc8349emds/Kconfig" -source "board/freescale/mpc8349itx/Kconfig" -source "board/freescale/mpc837xemds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 124c22f58a5..06a20c881d3 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -210,14 +210,6 @@ config TARGET_T2080RDB imply CMD_SATA imply PANIC_HANG -config TARGET_T2081QDS - bool "Support T2081QDS" - select ARCH_T2081 - select SUPPORT_SPL - select PHYS_64BIT - select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - select FSL_DDR_INTERACTIVE - config TARGET_T4160RDB bool "Support T4160RDB" select ARCH_T4160 @@ -234,10 +226,6 @@ config TARGET_T4240RDB imply CMD_SATA imply PANIC_HANG -config TARGET_CONTROLCENTERD - bool "Support controlcenterd" - select ARCH_P1022 - config TARGET_KMP204X bool "Support kmp204x" select VENDOR_KM @@ -266,18 +254,6 @@ config TARGET_UCP1020 imply CMD_SATA imply PANIC_HANG -config TARGET_CYRUS_P5020 - bool "Support Varisys Cyrus P5020" - select ARCH_P5020 - select PHYS_64BIT - imply PANIC_HANG - -config TARGET_CYRUS_P5040 - bool "Support Varisys Cyrus P5040" - select ARCH_P5040 - select PHYS_64BIT - imply PANIC_HANG - endchoice config ARCH_B4420 @@ -576,23 +552,6 @@ config ARCH_P1021 imply CMD_REGINFO imply SATA_SIL -config ARCH_P1022 - bool - select FSL_LAW - select SYS_FSL_ERRATUM_A004477 - select SYS_FSL_ERRATUM_A004508 - select SYS_FSL_ERRATUM_A005125 - select SYS_FSL_ERRATUM_ELBC_A001 - select SYS_FSL_ERRATUM_ESDHC111 - select SYS_FSL_ERRATUM_SATA_A001 - select FSL_PCIE_RESET - select SYS_FSL_HAS_DDR3 - select SYS_FSL_HAS_SEC - select SYS_FSL_SEC_BE - select SYS_FSL_SEC_COMPAT_2 - select SYS_PPC_E500_USE_DEBUG_TLB - select FSL_ELBC - config ARCH_P1023 bool select FSL_LAW @@ -756,31 +715,6 @@ config ARCH_P4080 imply CMD_REGINFO imply SATA_SIL -config ARCH_P5020 - bool - select E500MC - select FSL_LAW - select SYS_FSL_DDR_VER_44 - select SYS_FSL_ERRATUM_A004510 - select SYS_FSL_ERRATUM_A005275 - select SYS_FSL_ERRATUM_A006261 - select SYS_FSL_ERRATUM_DDR_A003 - select SYS_FSL_ERRATUM_DDR_A003474 - select SYS_FSL_ERRATUM_ESDHC111 - select SYS_FSL_ERRATUM_I2C_A004447 - select SYS_FSL_ERRATUM_SRIO_A004034 - select SYS_FSL_ERRATUM_USB14 - select SYS_FSL_HAS_DDR3 - select SYS_FSL_HAS_SEC - select SYS_FSL_QORIQ_CHASSIS1 - select SYS_FSL_SEC_BE - select SYS_FSL_SEC_COMPAT_4 - select SYS_PPC64 - select FSL_ELBC - imply CMD_SATA - imply CMD_REGINFO - imply FSL_SATA - config ARCH_P5040 bool select E500MC @@ -928,29 +862,6 @@ config ARCH_T2080 imply CMD_REGINFO imply FSL_SATA -config ARCH_T2081 - bool - select E500MC - select E6500 - select FSL_LAW - select SYS_FSL_DDR_VER_47 - select SYS_FSL_ERRATUM_A006379 - select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 - select SYS_FSL_ERRATUM_A007212 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_ERRATUM_ESDHC111 - select FSL_PCIE_RESET - select SYS_FSL_HAS_DDR3 - select SYS_FSL_HAS_SEC - select SYS_FSL_QORIQ_CHASSIS2 - select SYS_FSL_SEC_BE - select SYS_FSL_SEC_COMPAT_4 - select SYS_PPC64 - select FSL_IFC - imply CMD_NAND - imply CMD_REGINFO - config ARCH_T4160 bool select E500MC @@ -1052,19 +963,16 @@ config MAX_CPUS ARCH_P5040 || \ ARCH_T1040 || \ ARCH_T1042 || \ - ARCH_T2080 || \ - ARCH_T2081 + ARCH_T2080 default 2 if ARCH_B4420 || \ ARCH_BSC9132 || \ ARCH_MPC8572 || \ ARCH_P1020 || \ ARCH_P1021 || \ - ARCH_P1022 || \ ARCH_P1023 || \ ARCH_P1024 || \ ARCH_P1025 || \ ARCH_P2020 || \ - ARCH_P5020 || \ ARCH_T1023 || \ ARCH_T1024 default 1 @@ -1093,7 +1001,6 @@ config SYS_CCSRBAR_DEFAULT ARCH_P1011 || \ ARCH_P1020 || \ ARCH_P1021 || \ - ARCH_P1022 || \ ARCH_P1024 || \ ARCH_P1025 || \ ARCH_P2020 @@ -1103,14 +1010,12 @@ config SYS_CCSRBAR_DEFAULT ARCH_P2041 || \ ARCH_P3041 || \ ARCH_P4080 || \ - ARCH_P5020 || \ ARCH_P5040 || \ ARCH_T1023 || \ ARCH_T1024 || \ ARCH_T1040 || \ ARCH_T1042 || \ ARCH_T2080 || \ - ARCH_T2081 || \ ARCH_T4160 || \ ARCH_T4240 default 0xe0000000 if ARCH_QEMU_E500 @@ -1224,7 +1129,7 @@ config SYS_FSL_A004447_SVR_REV default 0x00 if ARCH_MPC8548 default 0x10 if ARCH_P1010 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 - default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 + default 0x20 if ARCH_P3041 || ARCH_P4080 config SYS_FSL_ERRATUM_IFC_A002769 bool @@ -1294,10 +1199,8 @@ config SYS_FSL_NUM_LAWS ARCH_P2041 || \ ARCH_P3041 || \ ARCH_P4080 || \ - ARCH_P5020 || \ ARCH_P5040 || \ ARCH_T2080 || \ - ARCH_T2081 || \ ARCH_T4160 || \ ARCH_T4240 default 16 if ARCH_T1023 || \ @@ -1313,7 +1216,6 @@ config SYS_FSL_NUM_LAWS ARCH_P1011 || \ ARCH_P1020 || \ ARCH_P1021 || \ - ARCH_P1022 || \ ARCH_P1023 || \ ARCH_P1024 || \ ARCH_P1025 || \ @@ -1363,7 +1265,6 @@ config SYS_PPC_E500_DEBUG_TLB ARCH_P1011 || \ ARCH_P1020 || \ ARCH_P1021 || \ - ARCH_P1022 || \ ARCH_P1024 || \ ARCH_P1025 || \ ARCH_P2020 @@ -1404,7 +1305,6 @@ config SYS_FSL_LBC_CLK_DIV default 2 if ARCH_P2041 || \ ARCH_P3041 || \ ARCH_P4080 || \ - ARCH_P5020 || \ ARCH_P5040 default 1 @@ -1429,11 +1329,9 @@ source "board/freescale/t104xrdb/Kconfig" source "board/freescale/t208xqds/Kconfig" source "board/freescale/t208xrdb/Kconfig" source "board/freescale/t4rdb/Kconfig" -source "board/gdsys/p1022/Kconfig" source "board/keymile/Kconfig" source "board/sbc8548/Kconfig" source "board/socrates/Kconfig" -source "board/varisys/cyrus/Kconfig" source "board/xes/xpedite520x/Kconfig" source "board/xes/xpedite537x/Kconfig" source "board/xes/xpedite550x/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 14e46626f33..b9d87ddb655 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -40,7 +40,6 @@ obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o obj-$(CONFIG_ARCH_P2041) += p2041_ids.o obj-$(CONFIG_ARCH_P3041) += p3041_ids.o obj-$(CONFIG_ARCH_P4080) += p4080_ids.o -obj-$(CONFIG_ARCH_P5020) += p5020_ids.o obj-$(CONFIG_ARCH_P5040) += p5040_ids.o obj-$(CONFIG_ARCH_T4240) += t4240_ids.o obj-$(CONFIG_ARCH_T4160) += t4240_ids.o @@ -51,7 +50,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_ids.o obj-$(CONFIG_ARCH_T1023) += t1024_ids.o obj-$(CONFIG_ARCH_T1024) += t1024_ids.o obj-$(CONFIG_ARCH_T2080) += t2080_ids.o -obj-$(CONFIG_ARCH_T2081) += t2080_ids.o obj-$(CONFIG_QE) += qe_io.o @@ -70,7 +68,6 @@ obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o -obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o @@ -78,7 +75,6 @@ obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o -obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o @@ -90,7 +86,6 @@ obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o -obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o obj-y += cpu.o obj-y += cpu_init.o diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c deleted file mode 100644 index 719cb4f3d4e..00000000000 --- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Author: Timur Tabi <timur@freescale.com> - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_serdes.h> - -#define SRDS1_MAX_LANES 4 -#define SRDS2_MAX_LANES 2 - -static u32 serdes1_prtcl_map, serdes2_prtcl_map; - -static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { - [0x00] = {NONE, NONE, NONE, NONE}, - [0x01] = {NONE, NONE, NONE, NONE}, - [0x02] = {NONE, NONE, NONE, NONE}, - [0x03] = {NONE, NONE, NONE, NONE}, - [0x04] = {NONE, NONE, NONE, NONE}, - [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, - [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, - [0x09] = {PCIE1, NONE, NONE, NONE}, - [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, - [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, - [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, - [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, - [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, - [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2}, - [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2}, - [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2}, - [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1}, - [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2}, - [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2}, -}; - -static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { - [0x00] = {PCIE3, PCIE3}, - [0x01] = {PCIE2, PCIE3}, - [0x02] = {SATA1, SATA2}, - [0x03] = {SGMII_TSEC1, SGMII_TSEC2}, - [0x04] = {NONE, NONE}, - [0x06] = {SATA1, SATA2}, - [0x07] = {NONE, NONE}, - [0x09] = {PCIE3, PCIE2}, - [0x0a] = {SATA1, SATA2}, - [0x0b] = {NONE, NONE}, - [0x0d] = {PCIE3, PCIE2}, - [0x0e] = {SATA1, SATA2}, - [0x0f] = {NONE, NONE}, - [0x15] = {SGMII_TSEC1, SGMII_TSEC2}, - [0x16] = {SATA1, SATA2}, - [0x17] = {NONE, NONE}, - [0x18] = {PCIE3, PCIE3}, - [0x19] = {SGMII_TSEC1, SGMII_TSEC2}, - [0x1a] = {SATA1, SATA2}, - [0x1b] = {NONE, NONE}, - [0x1c] = {PCIE3, PCIE3}, - [0x1d] = {SGMII_TSEC1, SGMII_TSEC2}, - [0x1e] = {SATA1, SATA2}, - [0x1f] = {NONE, NONE}, -}; - -int is_serdes_configured(enum srds_prtcl device) -{ - int ret; - - if (!(serdes1_prtcl_map & (1 << NONE))) - fsl_serdes_init(); - - ret = (1 << device) & serdes1_prtcl_map; - - if (ret) - return ret; - - if (!(serdes2_prtcl_map & (1 << NONE))) - fsl_serdes_init(); - - return (1 << device) & serdes2_prtcl_map; -} - -void fsl_serdes_init(void) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; - int lane; - - if (serdes1_prtcl_map & (1 << NONE) && - serdes2_prtcl_map & (1 << NONE)) - return; - - debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); - - if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); - return; - } - for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { - enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; - serdes1_prtcl_map |= (1 << lane_prtcl); - } - - /* Set the first bit to indicate serdes has been initialized */ - serdes1_prtcl_map |= (1 << NONE); - - if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); - return; - } - - for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { - enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; - serdes2_prtcl_map |= (1 << lane_prtcl); - } - - /* Set the first bit to indicate serdes has been initialized */ - serdes2_prtcl_map |= (1 << NONE); -} diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c deleted file mode 100644 index 575b604c211..00000000000 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> - -#ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { - /* dqrr liodn, frame data liodn, liodn off, sdest */ - SET_QP_INFO(1, 2, 1, 0), - SET_QP_INFO(3, 4, 2, 1), - SET_QP_INFO(5, 6, 3, 0), - SET_QP_INFO(7, 8, 4, 1), - SET_QP_INFO(9, 10, 5, 0), - SET_QP_INFO(11, 12, 6, 1), - SET_QP_INFO(13, 14, 7, 0), - SET_QP_INFO(15, 16, 8, 1), - SET_QP_INFO(17, 18, 9, 0), - SET_QP_INFO(19, 20, 10, 1), -}; -#endif - -struct srio_liodn_id_table srio_liodn_tbl[] = { - SET_SRIO_LIODN_2(1, 199, 200), - SET_SRIO_LIODN_2(2, 201, 202), -}; -int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); - -struct liodn_id_table liodn_tbl[] = { -#ifdef CONFIG_SYS_DPAA_QBMAN - SET_QMAN_LIODN(31), - SET_BMAN_LIODN(32), -#endif - - SET_SDHC_LIODN(1, 64), - - SET_PME_LIODN(117), - - SET_USB_LIODN(1, "fsl-usb2-mph", 125), - SET_USB_LIODN(2, "fsl-usb2-dr", 126), - - SET_SATA_LIODN(1, 127), - SET_SATA_LIODN(2, 128), - - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), - - SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), - SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), - - SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), - SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), -}; -int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); - -#ifdef CONFIG_SYS_DPAA_FMAN -struct fman_liodn_id_table fman1_liodn_tbl[] = { - SET_FMAN_RX_1G_LIODN(1, 0, 10), - SET_FMAN_RX_1G_LIODN(1, 1, 11), - SET_FMAN_RX_1G_LIODN(1, 2, 12), - SET_FMAN_RX_1G_LIODN(1, 3, 13), - SET_FMAN_RX_1G_LIODN(1, 4, 14), - SET_FMAN_RX_10G_LIODN(1, 0, 15), -}; -int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#endif - -struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 129, 130), - SET_SEC_JR_LIODN_ENTRY(1, 131, 132), - SET_SEC_JR_LIODN_ENTRY(2, 133, 134), - SET_SEC_JR_LIODN_ENTRY(3, 135, 136), - SET_SEC_RTIC_LIODN_ENTRY(a, 154), - SET_SEC_RTIC_LIODN_ENTRY(b, 155), - SET_SEC_RTIC_LIODN_ENTRY(c, 156), - SET_SEC_RTIC_LIODN_ENTRY(d, 157), - SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), - SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), -}; -int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); - -#ifdef CONFIG_SYS_FSL_RAID_ENGINE -struct liodn_id_table raide_liodn_tbl[] = { - SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), - SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), - SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), - SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), -}; -int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); -#endif - -#ifdef CONFIG_SYS_DPAA_RMAN -struct liodn_id_table rman_liodn_tbl[] = { - /* Set RMan block 0-3 liodn offset */ - SET_RMAN_LIODN(0, 6), - SET_RMAN_LIODN(1, 7), - SET_RMAN_LIODN(2, 8), - SET_RMAN_LIODN(3, 9), -}; -int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); -#endif - -struct liodn_id_table liodn_bases[] = { - [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), -#ifdef CONFIG_SYS_DPAA_FMAN - [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), -#endif -#ifdef CONFIG_SYS_DPAA_PME - [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), -#endif -#ifdef CONFIG_SYS_FSL_RAID_ENGINE - [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47), -#endif -#ifdef CONFIG_SYS_DPAA_RMAN - [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), -#endif -}; diff --git a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c deleted file mode 100644 index ec8234c1c1e..00000000000 --- a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <asm/fsl_serdes.h> -#include <asm/processor.h> -#include <asm/io.h> -#include "fsl_corenet_serdes.h" - -static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { - [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, - [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, - PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, - XAUI_FM1, XAUI_FM1, }, - [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, - SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, }, - [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, - SRIO1, }, - [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, - NONE, NONE, }, - [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, - SATA1, SATA2, }, - [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, - XAUI_FM1, XAUI_FM1, }, - [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, - SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, }, - [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, - NONE, NONE, }, - [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, - [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, - NONE, NONE, }, - [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, - XAUI_FM1, XAUI_FM1, }, - [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, - NONE, NONE, }, - [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, - AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, - NONE, NONE, SATA1, SATA2, }, - [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, - SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, - AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, - NONE, SATA1, SATA2, }, - [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, - XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, - [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, - SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, - AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, - NONE, SATA1, SATA2, }, - [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, - XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, -}; - -enum srds_prtcl serdes_get_prtcl(int cfg, int lane) -{ - if (!serdes_lane_enabled(lane)) - return NONE; - - return serdes_cfg_tbl[cfg][lane]; -} - -int is_serdes_prtcl_valid(u32 prtcl) { - int i; - - if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) - return 0; - - for (i = 0; i < SRDS_MAX_LANES; i++) { - if (serdes_cfg_tbl[prtcl][i] != NONE) - return 1; - } - - return 0; -} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 9c89ce5d70e..864c53ce2ec 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -127,7 +127,7 @@ void get_sys_info(sys_info_t *sys_info) * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ - defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) + defined(CONFIG_ARCH_T2080) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: @@ -198,7 +198,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \ - defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) + defined(CONFIG_ARCH_T2080) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) @@ -608,8 +608,7 @@ int get_clocks(void) * AN2919. */ #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \ - defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \ - defined(CONFIG_ARCH_P1022) + defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) gd->arch.i2c1_clk = sys_info.freq_systembus; #elif defined(CONFIG_ARCH_MPC8544) /* diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index 32cfcc0242b..5f34aab4531 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -160,7 +160,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = { {} }; -#ifndef CONFIG_ARCH_T2081 static const struct serdes_config serdes2_cfg_tbl[] = { /* SerDes 2 */ {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, @@ -176,13 +175,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = { {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, {} }; -#endif static const struct serdes_config *serdes_cfg_tbl[] = { serdes1_cfg_tbl, -#ifndef CONFIG_ARCH_T2081 serdes2_cfg_tbl, -#endif }; enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) diff --git a/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi b/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi index 889c8d450e0..65bb8a4b0b6 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi @@ -30,7 +30,7 @@ fman@500000 { pcsphy-handle = <&pcsphy14>; }; - mdio@f1000 { + mdio@5f1000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi index 2e456983372..eb39d29b39f 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi @@ -30,7 +30,7 @@ fman@500000 { pcsphy-handle = <&pcsphy15>; }; - mdio@f3000 { + mdio@5f3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi index b4ff19bf495..2f2209dbc9b 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy8>; }; - mdio@e1000 { + mdio@5e1000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi index 239c56ad1f6..11653c58b5f 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy9>; }; - mdio@e3000 { + mdio@5e3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi index 6e2bb009d9a..ae27c7bc6df 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy10>; }; - mdio@e5000 { + mdio@5e5000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi index 29dd94ba749..55ae5499176 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy11>; }; - mdio@e7000 { + mdio@5e7000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi index a5b49358270..833cf3e23d8 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy12>; }; - mdio@e9000 { + mdio@5e9000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi index 486c84bf981..81da55dfbe2 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy13>; }; - mdio@eb000 { + mdio@5eb000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1.dtsi index d8609c3ecfd..9efcf26c4ab 100644 --- a/arch/powerpc/dts/qoriq-fman3-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1.dtsi @@ -61,14 +61,14 @@ fman1: fman@500000 { reg = <0x87000 0x1000>; }; - mdio1: mdio@fc000 { + mdio1: mdio@5fc000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; reg = <0xfc000 0x1000>; }; - mdio@fd000 { + mdio@5fd000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts index 3584c06aa8d..5e9fab7a105 100644 --- a/arch/powerpc/dts/t1042d4rdb.dts +++ b/arch/powerpc/dts/t1042d4rdb.dts @@ -3,7 +3,7 @@ * T1042D4RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t104x.dtsi" @@ -20,6 +20,57 @@ }; }; +&soc { + fman0: fman@400000 { + ethernet@e0000 { + phy-handle = <&phy_sgmii_0>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&phy_sgmii_1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&phy_sgmii_2>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&phy_rgmii_0>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&phy_rgmii_1>; + phy-connection-type = "rgmii"; + }; + + mdio0: mdio@fc000 { + phy_sgmii_0: ethernet-phy@2 { + reg = <0x02>; + }; + + phy_sgmii_1: ethernet-phy@3 { + reg = <0x03>; + }; + + phy_sgmii_2: ethernet-phy@1 { + reg = <0x01>; + }; + + phy_rgmii_0: ethernet-phy@4 { + reg = <0x04>; + }; + + phy_rgmii_1: ethernet-phy@5 { + reg = <0x05>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -30,3 +81,5 @@ spi-max-frequency = <10000000>; /* input clock */ }; }; + +/include/ "t1042si-post.dtsi" diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi new file mode 100644 index 00000000000..5c60944e607 --- /dev/null +++ b/arch/powerpc/dts/t1042si-post.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T1042 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 - 2014 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3l-0.dtsi" +/include/ "qoriq-fman3-0-1g-0.dtsi" +/include/ "qoriq-fman3-0-1g-1.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-1g-4.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + mdio@fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@fd000 { + status = "disabled"; + }; + }; +}; diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts index 74bbb20e2a1..25f8c978c6d 100644 --- a/arch/powerpc/dts/t2080rdb.dts +++ b/arch/powerpc/dts/t2080rdb.dts @@ -3,7 +3,7 @@ * T2080RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t2080.dtsi" @@ -20,6 +20,71 @@ }; }; +&soc { + fman@400000 { + ethernet@e0000 { + phy-handle = <&xg_aq1202_phy3>; + phy-connection-type = "xgmii"; + }; + + ethernet@e2000 { + phy-handle = <&xg_aq1202_phy4>; + phy-connection-type = "xgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@f0000 { + phy-handle = <&xg_cs4315_phy2>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xg_cs4315_phy1>; + phy-connection-type = "xgmii"; + }; + + mdio@fc000 { + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + mdio@fd000 { + xg_cs4315_phy1: ethernet-phy@c { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0xc>; + }; + + xg_cs4315_phy2: ethernet-phy@d { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0xd>; + }; + + xg_aq1202_phy3: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + xg_aq1202_phy4: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -38,3 +103,5 @@ reg = <0x68>; }; }; + +/include/ "t2080si-post.dtsi" diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi new file mode 100644 index 00000000000..d8ef579cb7c --- /dev/null +++ b/arch/powerpc/dts/t2080si-post.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T2080 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { + +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3-0.dtsi" +/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi" +/include/ "qoriq-fman3-0-10g-1-best-effort.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-10g-0.dtsi" +/include/ "qoriq-fman3-0-10g-1.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet6: ethernet@f0000 { + }; + + enet7: ethernet@f2000 { + }; + + mdio@fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@fd000 { + interrupts = <101 1 0 0>; + }; + }; +}; diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts index 635065a0368..b3251e330de 100644 --- a/arch/powerpc/dts/t4240rdb.dts +++ b/arch/powerpc/dts/t4240rdb.dts @@ -3,7 +3,7 @@ * T4240RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t4240.dtsi" @@ -20,6 +20,144 @@ }; }; +&soc { + fman@400000 { + ethernet@e0000 { + phy-handle = <&sgmiiphy21>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmiiphy22>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&sgmiiphy23>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&sgmiiphy24>; + phy-connection-type = "sgmii"; + }; + + ethernet@e8000 { + status = "disabled"; + }; + + ethernet@ea000 { + status = "disabled"; + }; + + ethernet@f0000 { + phy-handle = <&xfiphy1>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xfiphy2>; + phy-connection-type = "xgmii"; + }; + }; + + fman@500000 { + ethernet@e0000 { + phy-handle = <&sgmiiphy41>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmiiphy42>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&sgmiiphy43>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&sgmiiphy44>; + phy-connection-type = "sgmii"; + }; + + ethernet@e8000 { + status = "disabled"; + }; + + ethernet@ea000 { + status = "disabled"; + }; + + ethernet@f0000 { + phy-handle = <&xfiphy3>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xfiphy4>; + phy-connection-type = "xgmii"; + }; + + mdio@5fc000 { + sgmiiphy21: ethernet-phy@0 { + reg = <0x0>; + }; + + sgmiiphy22: ethernet-phy@1 { + reg = <0x1>; + }; + + sgmiiphy23: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmiiphy24: ethernet-phy@3 { + reg = <0x3>; + }; + + sgmiiphy41: ethernet-phy@4 { + reg = <0x4>; + }; + + sgmiiphy42: ethernet-phy@5 { + reg = <0x5>; + }; + + sgmiiphy43: ethernet-phy@6 { + reg = <0x6>; + }; + + sgmiiphy44: ethernet-phy@7 { + reg = <0x7>; + }; + }; + + mdio@5fd000 { + xfiphy1: ethernet-phy@10 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x10>; + }; + + xfiphy2: ethernet-phy@11 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x11>; + }; + + xfiphy3: ethernet-phy@13 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x13>; + }; + + xfiphy4: ethernet-phy@12 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x12>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -30,3 +168,5 @@ spi-max-frequency = <10000000>; /* input clock */ }; }; + +/include/ "t4240si-post.dtsi" diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi new file mode 100644 index 00000000000..a596f48b54f --- /dev/null +++ b/arch/powerpc/dts/t4240si-post.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T4240 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3-0.dtsi" +/include/ "qoriq-fman3-0-1g-0.dtsi" +/include/ "qoriq-fman3-0-1g-1.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-1g-4.dtsi" +/include/ "qoriq-fman3-0-1g-5.dtsi" +/include/ "qoriq-fman3-0-10g-0.dtsi" +/include/ "qoriq-fman3-0-10g-1.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + enet5: ethernet@ea000 { + }; + + enet6: ethernet@f0000 { + }; + + enet7: ethernet@f2000 { + }; + + mdio@fc000 { + status = "disabled"; + }; + + mdio@fd000 { + status = "disabled"; + }; + }; + +/include/ "qoriq-fman3-1.dtsi" +/include/ "qoriq-fman3-1-1g-0.dtsi" +/include/ "qoriq-fman3-1-1g-1.dtsi" +/include/ "qoriq-fman3-1-1g-2.dtsi" +/include/ "qoriq-fman3-1-1g-3.dtsi" +/include/ "qoriq-fman3-1-1g-4.dtsi" +/include/ "qoriq-fman3-1-1g-5.dtsi" +/include/ "qoriq-fman3-1-10g-0.dtsi" +/include/ "qoriq-fman3-1-10g-1.dtsi" + fman@500000 { + enet8: ethernet@e0000 { + }; + + enet9: ethernet@e2000 { + }; + + enet10: ethernet@e4000 { + }; + + enet11: ethernet@e6000 { + }; + + enet12: ethernet@e8000 { + }; + + enet13: ethernet@ea000 { + }; + + enet14: ethernet@f0000 { + }; + + enet15: ethernet@f2000 { + }; + + mdio@5fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@5fd000 { + interrupts = <101 1 0 0>; + }; + }; +}; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4d70259f09b..20535487310 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -66,10 +66,6 @@ #define QE_NUM_OF_SNUM 28 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#elif defined(CONFIG_ARCH_P1022) -#define CONFIG_TSECV2 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - #elif defined(CONFIG_ARCH_P1023) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 @@ -157,24 +153,6 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 -#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ -#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE -#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 - #elif defined(CONFIG_ARCH_P5040) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 @@ -364,7 +342,7 @@ #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 -#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) +#elif defined(CONFIG_ARCH_T2080) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 @@ -381,9 +359,6 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 2 #endif #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 1 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 035bf124676..6499e10ef4f 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -25,7 +25,6 @@ defined(CONFIG_TARGET_T4240QDS) || \ defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ - defined(CONFIG_TARGET_T1040QDS) || \ defined(CONFIG_TARGET_T1040RDB) || \ defined(CONFIG_TARGET_T1040D4RDB) || \ defined(CONFIG_TARGET_T1042RDB) || \ @@ -58,7 +57,6 @@ #if defined(CONFIG_ARCH_P3041) || \ defined(CONFIG_ARCH_P4080) || \ - defined(CONFIG_ARCH_P5020) || \ defined(CONFIG_ARCH_P5040) || \ defined(CONFIG_ARCH_P2041) #define CONFIG_FSL_TRUST_ARCH_v1 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 905613fa312..59bc32fd172 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1808,7 +1808,7 @@ typedef struct ccsr_gur { #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 -#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) +#elif defined(CONFIG_ARCH_T2080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 @@ -1853,7 +1853,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 #endif #if defined(CONFIG_ARCH_P2041) || \ - defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020) + defined(CONFIG_ARCH_P3041) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 @@ -1880,7 +1880,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 #endif -#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081) +#if defined(CONFIG_ARCH_T2080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 @@ -2157,10 +2157,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 -#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 -#elif defined(CONFIG_ARCH_P1023) +#if defined(CONFIG_ARCH_P1023) #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else @@ -2278,12 +2275,6 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_QE11 0x00000010 #define MPC85xx_PMUXCR_QE12 0x00000008 #endif -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 -#define MPC85xx_PMUXCR_TDM 0x00014800 -#define MPC85xx_PMUXCR_SPI_MASK 0x00600000 -#define MPC85xx_PMUXCR_SPI 0x00000000 -#endif #if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 @@ -2363,10 +2354,6 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 #endif -#if defined(CONFIG_ARCH_P1022) -#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 -#define MPC85xx_PMUXCR2_USB 0x00150000 -#endif #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) #if defined(CONFIG_ARCH_BSC9131) #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 |