diff options
Diffstat (limited to 'arch/powerpc')
24 files changed, 317 insertions, 8 deletions
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 3195351c9c3..7eb005f4501 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb +dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb +dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts new file mode 100644 index 00000000000..c66c4923ac3 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pa.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB"; + compatible = "fsl,P1010RDB"; + + /include/ "p1010rdb_32b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts new file mode 100644 index 00000000000..b943de7cbb2 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB"; + compatible = "fsl,P1010RDB"; + + /include/ "p1010rdb_36b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb.dts b/arch/powerpc/dts/p1010rdb-pb.dts new file mode 100644 index 00000000000..9ca562534ff --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pb.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB-PB"; + compatible = "fsl,P1010RDB-PB"; + + /include/ "p1010rdb_32b.dtsi" +}; + +/include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb_36b.dts b/arch/powerpc/dts/p1010rdb-pb_36b.dts new file mode 100644 index 00000000000..eeff2a87044 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pb_36b.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB-PB"; + compatible = "fsl,P1010RDB-PB"; + + /include/ "p1010rdb_36b.dtsi" +}; + +/include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi new file mode 100644 index 00000000000..4f58ee24460 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ +&soc { + i2c@3000 { + rtc@68 { + compatible = "pericom,pt7c4338"; + reg = <0x68>; + }; + }; +}; diff --git a/arch/powerpc/dts/p1010rdb_32b.dtsi b/arch/powerpc/dts/p1010rdb_32b.dtsi new file mode 100644 index 00000000000..5da790da5e1 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb_32b.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; +}; + +pci1: pcie@ffe09000 { + reg = <0 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +}; + +pci0: pcie@ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +}; diff --git a/arch/powerpc/dts/p1010rdb_36b.dtsi b/arch/powerpc/dts/p1010rdb_36b.dtsi new file mode 100644 index 00000000000..54dd16e43b3 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb_36b.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +soc: soc@fffe00000 { + ranges = <0x0 0xf 0xffe00000 0x100000>; +}; + +pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +}; + +pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +}; diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi new file mode 100644 index 00000000000..02894413818 --- /dev/null +++ b/arch/powerpc/dts/p1010si-post.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2020 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1010-immr", "simple-bus"; + bus-frequency = <0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" +}; + +/* controller at 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* controller at 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p1010si-pre.dtsi b/arch/powerpc/dts/p1010si-pre.dtsi new file mode 100644 index 00000000000..9d7bb6c95d9 --- /dev/null +++ b/arch/powerpc/dts/p1010si-pre.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2020 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + compatible = "fsl,P1010"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,P1010@0 { + device_type = "cpu"; + reg = <0x0>; + }; + }; +}; diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1c77702f01e..1dce8e86e9a 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -44,6 +44,8 @@ clock-frequency = <0>; }; + /include/ "pq3-i2c-0.dtsi" + /include/ "pq3-i2c-1.dtsi" }; /* PCIe controller base address 0x9000 */ diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 5bbd5c54681..4ed093dad4e 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -37,6 +37,9 @@ /* Filled in by U-Boot */ clock-frequency = <0>; }; + + /include/ "pq3-i2c-0.dtsi" + /include/ "pq3-i2c-1.dtsi" }; /* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 0f5e7dbdc81..95931e299d8 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -3,7 +3,7 @@ * P2041 Silicon/SoC Device Tree Source (pre include) * * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -86,6 +86,9 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe200000 { diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi index 6736d000356..3152683b846 100644 --- a/arch/powerpc/dts/p3041.dtsi +++ b/arch/powerpc/dts/p3041.dtsi @@ -3,7 +3,7 @@ * P3041 Silicon/SoC Device Tree Source (pre include) * * Copyright 2010 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -86,6 +86,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe200000 { diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index 02f39fbfcb3..4a80561e188 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -3,7 +3,7 @@ * P4080/P4040 Silicon/SoC Device Tree Source (pre include) * * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -97,6 +97,8 @@ reg = <0x211000 0x1000>; phy_type = "ulpi"; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe200000 { diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi index 67a62a77253..45988574a2e 100644 --- a/arch/powerpc/dts/p5040.dtsi +++ b/arch/powerpc/dts/p5040.dtsi @@ -3,7 +3,7 @@ * P5040 Silicon/SoC Device Tree Source (pre include) * * Copyright 2012 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -85,6 +85,9 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe200000 { diff --git a/arch/powerpc/dts/pq3-i2c-0.dtsi b/arch/powerpc/dts/pq3-i2c-0.dtsi new file mode 100644 index 00000000000..86a91e63365 --- /dev/null +++ b/arch/powerpc/dts/pq3-i2c-0.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 I2C Device Tree stub + * + * Copyright 2020 NXP + */ +i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x3000 0x100>; + interrupts = <43 2 0 0>; +}; diff --git a/arch/powerpc/dts/pq3-i2c-1.dtsi b/arch/powerpc/dts/pq3-i2c-1.dtsi new file mode 100644 index 00000000000..5d79b1fb4c3 --- /dev/null +++ b/arch/powerpc/dts/pq3-i2c-1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 I2C Device Tree stub + * + * Copyright 2020 NXP + */ +i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x3100 0x100>; + interrupts = <43 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-i2c-0.dtsi b/arch/powerpc/dts/qoriq-i2c-0.dtsi new file mode 100644 index 00000000000..9d0ab886e72 --- /dev/null +++ b/arch/powerpc/dts/qoriq-i2c-0.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * QorIQ I2C Device Tree stub + * + * Copyright 2020 NXP + */ +i2c0: i2c@118000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x118000 0x100>; + interrupts = <38 2 0 0>; +}; + +i2c1: i2c@118100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x118100 0x100>; + interrupts = <38 2 0 0>; +}; diff --git a/arch/powerpc/dts/qoriq-i2c-1.dtsi b/arch/powerpc/dts/qoriq-i2c-1.dtsi new file mode 100644 index 00000000000..de0a22e3e01 --- /dev/null +++ b/arch/powerpc/dts/qoriq-i2c-1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * QorIQ I2C Device Tree stub + * + * Copyright 2020 NXP + */ +i2c2: i2c@119000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <2>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x119000 0x100>; + interrupts = <39 2 0 0>; +}; + +i2c3: i2c@119100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <3>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x119100 0x100>; + interrupts = <39 2 0 0>; +}; diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index a6b821a76af..521825d85a4 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -3,7 +3,7 @@ * T102X Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -75,6 +75,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe240000 { diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index 093aaab834b..0a08a69f31a 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -3,7 +3,7 @@ * T104X Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -85,6 +85,8 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe240000 { diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index 458019ae92f..a9e9b404f66 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -3,7 +3,7 @@ * T2080/T2081 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2018 NXP + * Copyright 2018,2020 NXP */ /dts-v1/; @@ -96,6 +96,8 @@ sata-number = <2>; sata-fpdma = <0>; }; + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe240000 { diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 43f98cd9e16..9b5902fe9e2 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -3,7 +3,7 @@ * T4240 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ /dts-v1/; @@ -125,6 +125,9 @@ reg = <0x114000 0x1000>; clock-frequency = <0>; }; + + /include/ "qoriq-i2c-0.dtsi" + /include/ "qoriq-i2c-1.dtsi" }; pcie@ffe240000 { |