22 files changed, 81 insertions, 192 deletions

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 0fc4ceda000..e0801c25941 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -68,4 +68,16 @@ source "arch/powerpc/cpu/mpc85xx/Kconfig"
 source "arch/powerpc/cpu/mpc8xx/Kconfig"
 source "arch/powerpc/lib/Kconfig"
 
+config USE_UBOOTPATH
+	bool "Set a default 'uboot' value in the environment"
+	help
+	  Many default environment scripts will check the "uboot" variable
+	  to determine the name of the file to load via tftp that will then
+	  be written to flash.
+
+config UBOOTPATH
+	string "Value of the default 'uboot' value in the environment"
+	depends on USE_UBOOTPATH
+	default "u-boot.bin"
+
 endmenu
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index 307ca65745c..725a4f48aad 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -3,7 +3,6 @@
 # (C) Copyright 2000-2010
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
 LDFLAGS_FINAL += --gc-sections
 LDFLAGS_FINAL += --bss-plt
 PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 563f52c5fdb..b695c7e4d81 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -200,6 +200,9 @@ config FSL_SERDES
 	bool "SerDes initialization"
 	depends on !MPC83XX_SERDES
 
+config NEVER_ASSERT_ODT_TO_CPU
+	bool "Never assert ODT to internal IOs"
+
 source "board/freescale/mpc837xerdb/Kconfig"
 source "board/gdsys/mpc8308/Kconfig"
 
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 8d531898bd8..a6c063556e8 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -180,24 +180,6 @@ void watchdog_reset (void)
 }
 #endif
 
-#ifndef CONFIG_DM_ETH
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_UEC_ETH)
-	uec_standard_init(bis);
-#endif
-
-#if defined(CONFIG_TSEC_ENET)
-	tsec_standard_init(bis);
-#endif
-	return 0;
-}
-#endif /* !CONFIG_DM_ETH */
-
 /*
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index f2361560e9a..6ab8a5249a4 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1,6 +1,19 @@
 menu "mpc85xx CPU"
 	depends on MPC85xx
 
+config PPC_SPINTABLE_COMPATIBLE
+	depends on MP
+	def_bool y
+	help
+	  To comply with ePAPR 1.1, the spin table has been moved to
+	  cache-enabled memory. Old OS may not work with this change. A patch
+	  is waiting to be accepted for Linux kernel. Other OS needs similar
+	  fix to spin table.  For OSes with old spin table code, we can enable
+	  this temporary fix by setting environmental variable
+	  "spin_table_compat". For new OSes, set "spin_table_compat=no". After
+	  Linux is fixed, we can remove this macro and related code. For now,
+	  it is enabled by default.
+
 config SYS_CPU
 	default "mpc85xx"
 
@@ -187,14 +200,6 @@ config TARGET_T1024RDB
 	imply CMD_EEPROM
 	imply PANIC_HANG
 
-config TARGET_T1042RDB
-	bool "Support T1042RDB"
-	select ARCH_T1042
-	select BOARD_LATE_INIT if CHAIN_OF_TRUST
-	select SUPPORT_SPL
-	select PHYS_64BIT
-	select SYS_L3_SIZE_256KB
-
 config TARGET_T1042D4RDB
 	bool "Support T1042D4RDB"
 	select ARCH_T1042
@@ -204,15 +209,6 @@ config TARGET_T1042D4RDB
 	select SYS_L3_SIZE_256KB
 	imply PANIC_HANG
 
-config TARGET_T1042RDB_PI
-	bool "Support T1042RDB_PI"
-	select ARCH_T1042
-	select BOARD_LATE_INIT if CHAIN_OF_TRUST
-	select SUPPORT_SPL
-	select PHYS_64BIT
-	select SYS_L3_SIZE_256KB
-	imply PANIC_HANG
-
 config TARGET_T2080QDS
 	bool "Support T2080QDS"
 	select ARCH_T2080
@@ -935,7 +931,7 @@ config ARCH_T4240
 	imply FSL_SATA
 
 config MPC85XX_HAVE_RESET_VECTOR
-	bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
+	bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc"
 	depends on MPC85xx
 
 config BTB
@@ -1297,6 +1293,9 @@ config SYS_NUM_TLBCAMS
 		Number of TLB CAM entries for Book-E chips. 64 for E500MC,
 		16 for other E500 SoCs.
 
+config L2_CACHE
+	bool "Enable L2 cache support"
+
 if HETROGENOUS_CLUSTERS
 
 config SYS_MAPLE
@@ -1324,6 +1323,11 @@ config SYS_ULB_CLK
 config SYS_ETVPE_CLK
 	int
 	default 1
+
+config MAX_DSP_CPUS
+	int
+	default 12 if ARCH_B4860
+	default 2 if ARCH_B4420
 endif
 
 config SYS_L2_SIZE_256KB
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index be85c54e480..e8a3e82765f 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -357,7 +357,7 @@ void
 init_85xx_watchdog(void)
 {
 	mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
-	      TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
+	      TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC));
 }
 
 void
@@ -616,12 +616,12 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
 /*
  * slide the testing window up to test another area
  * for 32_bit system, the maximum testable memory is limited to
- * CONFIG_MAX_MEM_MAPPED
+ * CFG_MAX_MEM_MAPPED
  */
 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 {
 	phys_addr_t test_cap, p_addr;
-	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+	phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
 
 #if !defined(CONFIG_PHYS_64BIT) || \
     !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
@@ -632,7 +632,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 #endif
 	p_addr = (*vstart) + (*size) + (*phys_offset);
 	if (p_addr < test_cap - 1) {
-		p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
+		p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED);
 		if (reset_tlb(p_addr, p_size, phys_offset) == -1)
 			return -1;
 		*vstart = CFG_SYS_DDR_SDRAM_BASE;
@@ -649,18 +649,18 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 /* initialization for testing area */
 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 {
-	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+	phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
 
 	*vstart = CFG_SYS_DDR_SDRAM_BASE;
-	*size = (u32) p_size;	/* CONFIG_MAX_MEM_MAPPED < 4G */
+	*size = (u32) p_size;	/* CFG_MAX_MEM_MAPPED < 4G */
 	*phys_offset = 0;
 
 #if !defined(CONFIG_PHYS_64BIT) || \
     !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
 	(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
-		if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+		if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
 			puts("Cannot test more than ");
-			print_size(CONFIG_MAX_MEM_MAPPED,
+			print_size(CFG_MAX_MEM_MAPPED,
 				" without proper 36BIT support.\n");
 		}
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index d5df02d39d8..18790921dd7 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -337,9 +337,6 @@ static void fdt_fixup_liodn_tbl_fman(void *blob,
 	for (i = 0; i < sz; i++) {
 		int off;
 
-		if (tbl[i].compat == NULL)
-			continue;
-
 		/* Try the new compatible first.
 		 * If the node is missing, try the old.
 		 */
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 44f8ed8a19a..7c47e415f05 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -193,8 +193,8 @@ u32 determine_mp_bootpg(unsigned int *pagesize)
 
 
 	/* use last 4K of mapped memory */
-	bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
-		CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
+	bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ?
+		CFG_MAX_MEM_MAPPED : gd->ram_size) +
 		CFG_SYS_SDRAM_BASE - 4096;
 	if (pagesize)
 		*pagesize = 4096;
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a6e352ceabb..9af40310b46 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -67,7 +67,7 @@ void get_sys_info(sys_info_t *sys_info)
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
 	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV)
 	uint rcw_tmp;
 #endif
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
@@ -206,7 +206,7 @@ void get_sys_info(sys_info_t *sys_info)
 #define FM1_CLK_SEL	0x1c000000
 #define FM1_CLK_SHIFT	26
 #endif
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV)
 #if defined(CONFIG_ARCH_T1024)
 	rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
 #else
@@ -215,7 +215,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_SYS_DPAA_PME
-#ifndef CONFIG_PME_PLAT_CLK_DIV
+#ifndef CFG_PME_PLAT_CLK_DIV
 	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK];
@@ -249,10 +249,10 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_SYS_DPAA_QBMAN
-#ifndef CONFIG_QBMAN_CLK_DIV
-#define CONFIG_QBMAN_CLK_DIV	2
+#ifndef CFG_QBMAN_CLK_DIV
+#define CFG_QBMAN_CLK_DIV	2
 #endif
-	sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
+	sys_info->freq_qman = sys_info->freq_systembus / CFG_QBMAN_CLK_DIV;
 #endif
 
 #if defined(CONFIG_SYS_MAPLE)
@@ -377,7 +377,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#ifndef CONFIG_FM_PLAT_CLK_DIV
+#ifndef CFG_FM_PLAT_CLK_DIV
 	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK];
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 5d21bef5878..2a78f0fe502 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -306,12 +306,12 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
 	u64 memsize = (u64)memsize_in_meg << 20;
 	u64 size;
 
-	size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
+	size = min(memsize, (u64)CFG_MAX_MEM_MAPPED);
 	size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
 
-	if (size || memsize > CONFIG_MAX_MEM_MAPPED) {
-		print_size(memsize > CONFIG_MAX_MEM_MAPPED ?
-			   memsize - CONFIG_MAX_MEM_MAPPED + size : size,
+	if (size || memsize > CFG_MAX_MEM_MAPPED) {
+		print_size(memsize > CFG_MAX_MEM_MAPPED ?
+			   memsize - CFG_MAX_MEM_MAPPED + size : size,
 			   " of DDR memory left unmapped in U-Boot\n");
 #ifndef CONFIG_SPL_BUILD
 		puts("       ");
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index fa3aa954cbb..3af0dfdf336 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -5,8 +5,8 @@
 
 #include "config.h"
 
-#ifdef CONFIG_RESET_VECTOR_ADDRESS
-#define RESET_VECTOR_ADDRESS	CONFIG_RESET_VECTOR_ADDRESS
+#ifdef CFG_RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS	CFG_RESET_VECTOR_ADDRESS
 #else
 #define RESET_VECTOR_ADDRESS	0xfffffffc
 #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 7f201909229..73d28f2a4e2 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -343,29 +343,3 @@ int fixup_cpu(void)
 #endif
 	return 0;
 }
-
-#ifndef CONFIG_DM_ETH
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(struct bd_info *bis)
-{
-#if defined(CONFIG_UEC_ETH)
-	uec_standard_init(bis);
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
-	tsec_standard_init(bis);
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-	fm_standard_init(bis);
-#endif
-
-#ifdef CONFIG_VSC9953
-	vsc9953_init(bis);
-#endif
-	return 0;
-}
-#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
index caad6670cc9..b906279226a 100644
--- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
@@ -17,7 +17,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
 
 	tbl->start_addr[i] =
 			(uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE);
-	tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
+	tbl->size[i] = (phys_size_t)(min(gd->ram_size, CFG_MAX_MEM_MAPPED));
 	tbl->end_addr[i] = tbl->start_addr[i] +  tbl->size[i] - 1;
 
 	i++;
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index dc1bc0db423..c0b4a1217d3 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -33,17 +33,17 @@
 	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
 #endif
 	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
-	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
+	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
 	#define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
 	#define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
 	#define _DEVDISR_RMU   MPC85xx_DEVDISR_RMSG
-	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
+	#define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC86xx)
 	#define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
 	#define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
 	#define _DEVDISR_RMU   MPC86xx_DEVDISR_RMSG
-	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
+	#define CFG_SYS_MPC8xxx_GUTS_ADDR \
 		(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
 #else
 #error "No defines for DEVDISR_SRIO"
@@ -230,7 +230,7 @@ host_ok:
 
 void srio_init(void)
 {
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
+	ccsr_gur_t *gur = (void *)CFG_SYS_MPC8xxx_GUTS_ADDR;
 	int srio1_used = 0, srio2_used = 0;
 	u32 *devdisr;
 
diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi
index 28f303b749e..d0277627644 100644
--- a/arch/powerpc/dts/kmcent2-u-boot.dtsi
+++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi
@@ -74,24 +74,6 @@
 		compatible = "fsl,pcie-t104x";
 		law_trgt_if = <0>;
 	};
-
-	binman {
-		filename = "u-boot.bin";
-		skip-at-start = <CONFIG_TEXT_BASE>;
-		sort-by-offset;
-		pad-byte = <0xff>;
-		size = <CONFIG_SYS_MONITOR_LEN>;
-
-		u-boot-with-ucode-ptr {
-			offset = <CONFIG_TEXT_BASE>;
-			optional-ucode;
-		};
-
-		u-boot-dtb-with-ucode {
-			align = <256>;
-		};
-		powerpc-mpc85xx-bootpg-resetvec {
-			offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
-		};
-	};
 };
+
+#include "u-boot.dtsi"
diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi
index b4b5257362e..6b7375cff21 100644
--- a/arch/powerpc/dts/u-boot.dtsi
+++ b/arch/powerpc/dts/u-boot.dtsi
@@ -23,11 +23,11 @@
 		u-boot-dtb-with-ucode {
 			align = <4>;
 		};
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#ifndef CFG_RESET_VECTOR_ADDRESS
+#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 		powerpc-mpc85xx-bootpg-resetvec {
-			offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+			offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>;
 		};
 	};
 };
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 983c6f70cfe..f0702cab143 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -14,13 +14,13 @@
   #define HWCONFIG_BUFFER_SIZE 256
 #endif
 
-#ifndef CONFIG_MAX_MEM_MAPPED
+#ifndef CFG_MAX_MEM_MAPPED
 #if	defined(CONFIG_E500)		|| \
 	defined(CONFIG_MPC86xx)		|| \
 	defined(CONFIG_E300)
-#define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
+#define CFG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 #else
-#define CONFIG_MAX_MEM_MAPPED	(256 << 20)
+#define CFG_MAX_MEM_MAPPED	(256 << 20)
 #endif
 #endif
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d9e5a7d6217..d731ac3f4d7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -8,12 +8,6 @@
 
 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
 
-/*
- * This macro should be removed when we no longer care about backwards
- * compatibility with older operating systems.
- */
-#define CONFIG_PPC_SPINTABLE_COMPATIBLE
-
 #include <fsl_ddrc_version.h>
 
 #if defined(CONFIG_ARCH_MPC8548)
@@ -23,19 +17,9 @@
 #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_ARCH_P1010)
-#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 
-/* P1011 is single core version of P1020 */
-#elif defined(CONFIG_ARCH_P1011)
-#define CONFIG_TSECV2
-
-#elif defined(CONFIG_ARCH_P1020)
-#define CONFIG_TSECV2
-
 #elif defined(CONFIG_ARCH_P1021)
-#define CONFIG_TSECV2
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
@@ -47,13 +31,8 @@
 #define CFG_SYS_BMAN_NUM_PORTALS	3
 #define CFG_SYS_FM_MURAM_SIZE	0x10000
 
-/* P1024 is lower end variant of P1020 */
-#elif defined(CONFIG_ARCH_P1024)
-#define CONFIG_TSECV2
-
 /* P1025 is lower end variant of P1021 */
 #elif defined(CONFIG_ARCH_P1025)
-#define CONFIG_TSECV2
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
@@ -107,13 +86,9 @@
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_BSC9131)
-#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 
 #elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 
 #elif defined(CONFIG_ARCH_T4240)
@@ -152,8 +127,6 @@
 #define CFG_SYS_FM_MURAM_SIZE	0x60000
 
 #ifdef CONFIG_ARCH_B4860
-#define CONFIG_MAX_DSP_CPUS		12
-#define CONFIG_NUM_DSP_CPUS		6
 #define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CFG_SYS_NUM_FM1_DTSEC	6
 #define CFG_SYS_NUM_FM1_10GEC	2
@@ -161,7 +134,6 @@
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #else
-#define CONFIG_MAX_DSP_CPUS		2
 #define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
 #define CFG_SYS_NUM_FM1_DTSEC	4
 #define CFG_SYS_NUM_FM1_10GEC	0
@@ -172,11 +144,11 @@
 #define CONFIG_SYS_FSL_SRDS_1
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	5
-#define CONFIG_PME_PLAT_CLK_DIV		2
-#define CFG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CFG_PME_PLAT_CLK_DIV		2
+#define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_FM_PLAT_CLK_DIV	1
-#define CFG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
+#define CFG_FM_PLAT_CLK_DIV	1
+#define CFG_SYS_FM1_CLK		CFG_FM_PLAT_CLK_DIV
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
@@ -189,10 +161,9 @@
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	4
 #define CFG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM1_CLK		0
-#define CONFIG_QBMAN_CLK_DIV		1
+#define CFG_QBMAN_CLK_DIV		1
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
@@ -211,8 +182,8 @@
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #endif
-#define CONFIG_PME_PLAT_CLK_DIV		1
-#define CFG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CFG_PME_PLAT_CLK_DIV		1
+#define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
 #define CFG_SYS_FM1_CLK		0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM_MURAM_SIZE	0x28000
@@ -220,8 +191,6 @@
 
 
 #elif defined(CONFIG_ARCH_C29X)
-#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_TSECV2_1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h
index 727f4a7e92c..1459db74bee 100644
--- a/arch/powerpc/include/asm/fsl_dma.h
+++ b/arch/powerpc/include/asm/fsl_dma.h
@@ -117,7 +117,7 @@ typedef struct fsl_dma {
 void dma_init(void);
 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
 #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
-void dma_meminit(uint val, uint size);
+void dma_meminit(uint size);
 #endif
 #endif
 
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index e8b26802062..236098e718e 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -17,9 +17,7 @@
 
 #if defined(CONFIG_TARGET_T2080QDS) || \
 	defined(CONFIG_TARGET_T2080RDB) || \
-	defined(CONFIG_TARGET_T1042RDB) || \
 	defined(CONFIG_TARGET_T1042D4RDB) || \
-	defined(CONFIG_TARGET_T1042RDB_PI) || \
 	defined(CONFIG_ARCH_T1024)
 #undef CFG_SYS_INIT_L3_ADDR
 #define CFG_SYS_INIT_L3_ADDR			0xbff00000
@@ -35,24 +33,6 @@
 #define CFG_SYS_INIT_L3_ADDR		0xbff00000
 #endif
 #endif
-
-#if defined(CONFIG_ARCH_P3041)	||	\
-	defined(CONFIG_ARCH_P4080) ||	\
-	defined(CONFIG_ARCH_P5040) ||	\
-	defined(CONFIG_ARCH_P2041)
-	#define	CONFIG_FSL_TRUST_ARCH_v1
-#endif
-
-#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
-/* The key used for verification of next level images
- * is picked up from an Extension Table which has
- * been verified by the ISBC (Internal Secure boot Code)
- * in boot ROM of the SoC.
- * The feature is only applicable in case of NOR boot and is
- * not applicable in case of RAMBOOT (NAND, SD, SPI).
- */
-#define CONFIG_FSL_ISBC_KEY_EXT
-#endif
 #endif /* #ifdef CONFIG_NXP_ESBC */
 
 #ifdef CONFIG_CHAIN_OF_TRUST
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 19774f3053b..24bd438c143 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -873,9 +873,4 @@ struct ccsr_gpio {
 
 #define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
-#define CFG_SYS_TSEC1_OFFSET		0x24000
-#define CFG_SYS_MDIO1_OFFSET		0x24000
-
-#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 #endif				/* __IMMAP_83xx__ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 283fdf3b458..7293720fb3c 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2541,13 +2541,6 @@ struct ccsr_pman {
 #define CFG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
-#ifdef CONFIG_TSECV2
-#define CFG_SYS_TSEC1_OFFSET			0xB0000
-#elif defined(CONFIG_TSECV2_1)
-#define CFG_SYS_TSEC1_OFFSET			0x10000
-#else
-#define CFG_SYS_TSEC1_OFFSET			0x24000
-#endif
 #define CFG_SYS_MDIO1_OFFSET			0x24000
 #define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
@@ -2673,7 +2666,6 @@ struct ccsr_pman {
 #define CFG_SYS_SEC_MON_ADDR  \
 	(CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET)
 
-#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2