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Diffstat (limited to 'arch/riscv/cpu/andes/cache.c')
-rw-r--r--arch/riscv/cpu/andes/cache.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c
index 7d3df8722dd..bb57498d75a 100644
--- a/arch/riscv/cpu/andes/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -43,9 +43,7 @@ static void cache_ops(int (*ops)(struct udevice *dev))
void flush_dcache_all(void)
{
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
-#endif
+ csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
}
void flush_dcache_range(unsigned long start, unsigned long end)