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-rw-r--r--arch/riscv/cpu/cpu.c6
-rw-r--r--arch/riscv/cpu/cv1800b/Kconfig1
-rw-r--r--arch/riscv/cpu/cv1800b/Makefile1
-rw-r--r--arch/riscv/cpu/cv1800b/cache.c45
-rw-r--r--arch/riscv/cpu/th1520/Kconfig22
-rw-r--r--arch/riscv/cpu/th1520/Makefile8
-rw-r--r--arch/riscv/cpu/th1520/cache.c32
-rw-r--r--arch/riscv/cpu/th1520/cpu.c21
-rw-r--r--arch/riscv/cpu/th1520/dram.c21
-rw-r--r--arch/riscv/cpu/th1520/spl.c96
10 files changed, 207 insertions, 46 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 5b31da64cbd..15c4e14599d 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -18,6 +18,7 @@
#include <asm/hwcap.h>
#include <asm/cpufeature.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
#include <dm/uclass-internal.h>
#include <linux/bitops.h>
#include <linux/log2.h>
@@ -746,3 +747,8 @@ __weak int cleanup_before_linux(void)
return 0;
}
+
+void arch_setup_gd(gd_t *new_gd)
+{
+ set_gd(new_gd);
+}
diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
index 7225b1210c5..57f724ae043 100644
--- a/arch/riscv/cpu/cv1800b/Kconfig
+++ b/arch/riscv/cpu/cv1800b/Kconfig
@@ -6,6 +6,7 @@ config SOPHGO_CV1800B
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
+ select SYS_CACHE_THEAD_CMO
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
index 95beb34b51a..da12e0f64e1 100644
--- a/arch/riscv/cpu/cv1800b/Makefile
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -4,4 +4,3 @@
obj-y += dram.o
obj-y += cpu.o
-obj-y += cache.o
diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c
deleted file mode 100644
index b8051e29e02..00000000000
--- a/arch/riscv/cpu/cv1800b/cache.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
- */
-
-#include <cpu_func.h>
-
-/*
- * dcache.ipa rs1 (invalidate)
- * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
- * 0000001 01010 rs1 000 00000 0001011
- *
- * dcache.cpa rs1 (clean)
- * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
- * 0000001 01001 rs1 000 00000 0001011
- *
- * dcache.cipa rs1 (clean then invalidate)
- * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
- * 0000001 01011 rs1 000 00000 0001011
- *
- * sync.s
- * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
- * 0000000 11001 00000 000 00000 0001011
- */
-#define DCACHE_IPA_A0 ".long 0x02a5000b"
-#define DCACHE_CPA_A0 ".long 0x0295000b"
-#define DCACHE_CIPA_A0 ".long 0x02b5000b"
-
-#define SYNC_S ".long 0x0190000b"
-
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
- register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
- for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
- __asm__ __volatile__(DCACHE_IPA_A0);
- __asm__ __volatile__(SYNC_S);
-}
-
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
- register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
- for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
- __asm__ __volatile__(DCACHE_CPA_A0);
- __asm__ __volatile__(SYNC_S);
-}
diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig
new file mode 100644
index 00000000000..4d44191bd22
--- /dev/null
+++ b/arch/riscv/cpu/th1520/Kconfig
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+# Copyright (C) 2025, Yao Zi <ziyao@disroot.org>
+
+config THEAD_TH1520
+ bool
+ select ARCH_EARLY_INIT_R
+ select SYS_CACHE_SHIFT_6
+ select SUPPORT_SPL
+ select BINMAN if SPL
+ select SYS_CACHE_THEAD_CMO
+ select CLK_THEAD
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply RISCV_ACLINT if RISCV_MMODE
+ imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
+ imply CMD_CPU
+ imply SPL_CPU
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/th1520/Makefile b/arch/riscv/cpu/th1520/Makefile
new file mode 100644
index 00000000000..5d806c06e2e
--- /dev/null
+++ b/arch/riscv/cpu/th1520/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025, Yao Zi <ziyao@disroot.org>
+
+obj-y += cache.o
+obj-y += cpu.o
+obj-y += dram.o
+obj-y += spl.o
diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c
new file mode 100644
index 00000000000..08aa1f789fd
--- /dev/null
+++ b/arch/riscv/cpu/th1520/cache.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
+ */
+
+#include <asm/io.h>
+#include <cpu_func.h>
+#include <linux/bitops.h>
+
+#define CSR_MHCR 0x7c1
+#define CSR_MHCR_IE BIT(0)
+#define CSR_MHCR_DE BIT(1)
+
+void icache_enable(void)
+{
+ csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
+}
+
+void dcache_enable(void)
+{
+ csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_DE);
+}
+
+int icache_status(void)
+{
+ return (csr_read(CSR_MHCR) & CSR_MHCR_IE) != 0;
+}
+
+int dcache_status(void)
+{
+ return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
+}
diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c
new file mode 100644
index 00000000000..b83f1272c67
--- /dev/null
+++ b/arch/riscv/cpu/th1520/cpu.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
+ *
+ * TH1520 SoC has a set of undocumented customized PMP registers that are
+ * configured through MMIO operation. It must be disabled before entering
+ * the DRAM region, or an exception will be raised.
+ */
+
+#include <asm/io.h>
+#include <cpu_func.h>
+
+#define TH1520_PMP_BASE (void *)0xffdc020000
+
+void th1520_invalidate_pmp(void)
+{
+ /* Invalidate the PMP configuration as in vendor U-Boot code */
+ writel(0x0, TH1520_PMP_BASE + 0x0);
+
+ invalidate_icache_all();
+}
diff --git a/arch/riscv/cpu/th1520/dram.c b/arch/riscv/cpu/th1520/dram.c
new file mode 100644
index 00000000000..91007c0a3d3
--- /dev/null
+++ b/arch/riscv/cpu/th1520/dram.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c
new file mode 100644
index 00000000000..362fe895f86
--- /dev/null
+++ b/arch/riscv/cpu/th1520/spl.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ */
+#include <asm/arch/iopmp.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <linux/sizes.h>
+#include <log.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220)
+#define TH1520_SUBSYS_CLK_VO_EN BIT(2)
+#define TH1520_SUBSYS_CLK_VI_EN BIT(1)
+#define TH1520_SUBSYS_CLK_DSP_EN BIT(0)
+#define TH1520_SUBSYS_RST (void __iomem *)(0xffff015000 + 0x220)
+#define TH1520_SUBSYS_RST_VP_N BIT(3)
+#define TH1520_SUBSYS_RST_VO_N BIT(2)
+#define TH1520_SUBSYS_RST_VI_N BIT(1)
+#define TH1520_SUBSYS_RST_DSP_N BIT(0)
+
+int spl_dram_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = fdtdec_setup_mem_size_base();
+ if (ret) {
+ printf("failed to setup memory size and base: %d\n", ret);
+ return ret;
+ }
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void __iomem *th1520_iopmp_regs[] = {
+ TH1520_IOPMP_EMMC,
+ TH1520_IOPMP_SDIO0,
+ TH1520_IOPMP_SDIO1,
+ TH1520_IOPMP_USB0,
+ TH1520_IOPMP_AO,
+ TH1520_IOPMP_AUD,
+ TH1520_IOPMP_CHIP_DBG,
+ TH1520_IOPMP_EIP120I,
+ TH1520_IOPMP_EIP120II,
+ TH1520_IOPMP_EIP120III,
+ TH1520_IOPMP_ISP0,
+ TH1520_IOPMP_ISP1,
+ TH1520_IOPMP_DW200,
+ TH1520_IOPMP_VIPRE,
+ TH1520_IOPMP_VENC,
+ TH1520_IOPMP_VDEC,
+ TH1520_IOPMP_G2D,
+ TH1520_IOPMP_FCE,
+ TH1520_IOPMP_NPU,
+ TH1520_IOPMP_DPU0,
+ TH1520_IOPMP_DPU1,
+ TH1520_IOPMP_GPU,
+ TH1520_IOPMP_GMAC1,
+ TH1520_IOPMP_GMAC2,
+ TH1520_IOPMP_DMAC,
+ TH1520_IOPMP_TEE_DMAC,
+ TH1520_IOPMP_DSP0,
+ TH1520_IOPMP_DSP1,
+};
+
+void harts_early_init(void)
+{
+ int i;
+
+ /*
+ * Set IOPMPs to the default attribute, allowing the application
+ * processor to access various peripherals. Subsystem clocks should be
+ * enabled and resets should be deasserted ahead of time, or the HART
+ * will hang when configuring corresponding IOPMP entries.
+ */
+ setbits_le32(TH1520_SUBSYS_CLK, TH1520_SUBSYS_CLK_VO_EN |
+ TH1520_SUBSYS_CLK_VI_EN |
+ TH1520_SUBSYS_CLK_DSP_EN);
+ setbits_le32(TH1520_SUBSYS_RST, TH1520_SUBSYS_RST_VP_N |
+ TH1520_SUBSYS_RST_VO_N |
+ TH1520_SUBSYS_RST_VI_N |
+ TH1520_SUBSYS_RST_DSP_N);
+
+ for (i = 0; i < ARRAY_SIZE(th1520_iopmp_regs); i++)
+ writel(TH1520_IOPMP_DEFAULT_ATTR, th1520_iopmp_regs[i]);
+}
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-02 01:06:06 +0000