diff options
Diffstat (limited to 'arch/riscv/include/asm/arch-andes/csr.h')
| -rw-r--r-- | arch/riscv/include/asm/arch-andes/csr.h | 29 |
1 files changed, 17 insertions, 12 deletions
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 393d51c6dde..028fd01c2f3 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -12,20 +12,25 @@ #define CSR_MCACHE_CTL 0x7ca #define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 #define CSR_MCCTLCOMMAND 0x7cc -#define MCACHE_CTL_IC_EN_OFFSET 0 -#define MCACHE_CTL_DC_EN_OFFSET 1 -#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 -#define MCACHE_CTL_DC_COHEN_OFFSET 19 -#define MCACHE_CTL_DC_COHSTA_OFFSET 20 - -#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) -#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) -#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) -#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) -#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) +/* mcache_ctl register */ + +#define MCACHE_CTL_IC_EN BIT(0) +#define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_IC_ECCEN BIT(3) +#define MCACHE_CTL_DC_ECCEN BIT(5) +#define MCACHE_CTL_CCTL_SUEN BIT(8) +#define MCACHE_CTL_IC_PREFETCH_EN BIT(9) +#define MCACHE_CTL_DC_PREFETCH_EN BIT(10) +#define MCACHE_CTL_DC_WAROUND_EN BIT(13) +#define MCACHE_CTL_L2C_WAROUND_EN BIT(15) +#define MCACHE_CTL_TLB_ECCEN BIT(18) +#define MCACHE_CTL_DC_COHEN BIT(19) +#define MCACHE_CTL_DC_COHSTA BIT(20) + +/* mmisc_ctl register */ +#define MMISC_CTL_NON_BLOCKING_EN BIT(8) #define CCTL_L1D_WBINVAL_ALL 6 |