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-rw-r--r--arch/riscv/lib/cache.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index 1d67c49c2c0..d642a38a071 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -12,6 +12,16 @@ void flush_dcache_range(unsigned long start, unsigned long end)
void invalidate_icache_range(unsigned long start, unsigned long end)
{
+ /*
+ * RISC-V does not have an instruction for invalidating parts of the
+ * instruction cache. Invalidate all of it instead.
+ */
+ invalidate_icache_all();
+}
+
+void invalidate_icache_all(void)
+{
+ asm volatile ("fence.i" ::: "memory");
}
void invalidate_dcache_range(unsigned long start, unsigned long end)