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-rw-r--r--arch/riscv/Kconfig26
-rw-r--r--arch/riscv/cpu/ast2700/Kconfig6
-rw-r--r--arch/riscv/cpu/ast2700/Makefile1
-rw-r--r--arch/riscv/cpu/ast2700/cpu.c23
-rw-r--r--arch/riscv/cpu/u-boot-spl.lds2
-rw-r--r--arch/riscv/dts/Makefile1
-rw-r--r--arch/riscv/dts/ast2700-ibex.dts22
-rw-r--r--arch/riscv/dts/ast2700-u-boot.dtsi40
-rw-r--r--arch/riscv/dts/ast2700.dtsi76
-rw-r--r--arch/riscv/dts/cv18xx.dtsi40
-rw-r--r--arch/riscv/include/asm/arch-ast2700/fmc_hdr.h52
-rw-r--r--arch/riscv/include/asm/arch-ast2700/scu.h145
-rw-r--r--arch/riscv/include/asm/arch-ast2700/sdram.h137
-rw-r--r--arch/riscv/include/asm/arch-ast2700/sli.h82
-rw-r--r--arch/riscv/include/asm/bitops.h40
-rw-r--r--arch/riscv/lib/interrupts.c7
16 files changed, 668 insertions, 32 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa3b016c527..fa371027d45 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -46,6 +46,9 @@ config TARGET_TH1520_LPI4A
config TARGET_XILINX_MBV
bool "Support AMD/Xilinx MicroBlaze V"
+config TARGET_ASPEED_AST2700_IBEX
+ bool "Support Ibex RISC-V cores on Aspeed AST2700 SoC"
+
endchoice
config SYS_ICACHE_OFF
@@ -81,6 +84,7 @@ config SPL_ZERO_MEM_BEFORE_USE
# board-specific options below
source "board/andestech/ae350/Kconfig"
+source "board/aspeed/ibex_ast2700/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
@@ -97,6 +101,7 @@ source "arch/riscv/cpu/andes/Kconfig"
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
+source "arch/riscv/cpu/ast2700/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
source "arch/riscv/cpu/jh7110/Kconfig"
@@ -133,6 +138,7 @@ config FRAMEPOINTER
config SPL_FRAMEPOINTER
bool "Build SPL with frame pointer for stack unwinding"
+ depends on SPL
help
Choose this option to use the frame pointer so the stack can be
unwound if needed. This is useful for tracing where faults came
@@ -308,7 +314,10 @@ config TPL_USE_ARCH_STRNCMP
endmenu
config RISCV_ISA_A
- def_bool y
+ bool "Standard extension for Atomic Instructions"
+ default y
+ help
+ Adds "A" to the ISA string passed to the compiler.
config DMA_ADDR_T_64BIT
bool
@@ -437,7 +446,20 @@ config AVAILABLE_HARTS
If disable this, it will send IPI by CPUs node numbers of device tree.
config SHOW_REGS
+ default y
bool "Show registers on unhandled exception"
+ help
+ By default only the program counter and the return address register
+ are shown in crash dumps. Enable this symbol to show all registers in
+ main U-Boot.
+
+config SPL_SHOW_REGS
+ bool "In SPL show registers on unhandled exception"
+ depends on SPL
+ help
+ By default only the program counter and the return address register
+ are shown in crash dumps. Enable this symbol to show all registers in
+ SPL.
config RISCV_PRIV_1_9
bool "Use version 1.9 of the RISC-V priviledged specification"
@@ -450,7 +472,7 @@ config RISCV_PRIV_1_9
memory is configured was also changed.
config STACK_SIZE_SHIFT
- int
+ int "Stack size shift"
default 14
config OF_BOARD_FIXUP
diff --git a/arch/riscv/cpu/ast2700/Kconfig b/arch/riscv/cpu/ast2700/Kconfig
new file mode 100644
index 00000000000..b16f0fc7cad
--- /dev/null
+++ b/arch/riscv/cpu/ast2700/Kconfig
@@ -0,0 +1,6 @@
+config RISCV_AST2700
+ bool
+ imply CPU
+ imply CPU_RISCV
+ help
+ Run U-Boot on AST2700 with IBex RISC-V CPU integrated.
diff --git a/arch/riscv/cpu/ast2700/Makefile b/arch/riscv/cpu/ast2700/Makefile
new file mode 100644
index 00000000000..1f843c706ad
--- /dev/null
+++ b/arch/riscv/cpu/ast2700/Makefile
@@ -0,0 +1 @@
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/ast2700/cpu.c b/arch/riscv/cpu/ast2700/cpu.c
new file mode 100644
index 00000000000..c1540546a9a
--- /dev/null
+++ b/arch/riscv/cpu/ast2700/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2024, Aspeed Technology Inc.
+ */
+
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index d1113a59aa6..907094620bd 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -44,8 +44,6 @@ SECTIONS
__binman_sym_end = .;
} > .spl_mem
- . = ALIGN(8);
-
_end = .;
_image_binary_end = .;
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 17cda483e12..c4c44057bad 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
+dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
include $(srctree)/scripts/Makefile.dts
diff --git a/arch/riscv/dts/ast2700-ibex.dts b/arch/riscv/dts/ast2700-ibex.dts
new file mode 100644
index 00000000000..f7a05e5771b
--- /dev/null
+++ b/arch/riscv/dts/ast2700-ibex.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "ast2700.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart12;
+ tick-timer = &ast_ibex_timer;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&uart12 {
+ status = "okay";
+ clock-frequency = <1846153>;
+};
diff --git a/arch/riscv/dts/ast2700-u-boot.dtsi b/arch/riscv/dts/ast2700-u-boot.dtsi
new file mode 100644
index 00000000000..ddc08a4bcef
--- /dev/null
+++ b/arch/riscv/dts/ast2700-u-boot.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+ cpus {
+ bootph-all;
+ };
+
+ memory@80000000 {
+ bootph-all;
+ };
+
+ soc0: soc@12000000 {
+ bootph-all;
+
+ sdrammc: sdrammc@12c00000 {
+ bootph-all;
+ };
+
+ syscon0: syscon@12c02000 {
+ bootph-all;
+ };
+ };
+
+ soc1: soc@14000000 {
+ bootph-all;
+
+ syscon1: syscon@14c02000 {
+ bootph-all;
+ };
+
+ uart12: serial@14c33b00 {
+ bootph-all;
+ };
+
+ ast_ibex_timer: timer {
+ bootph-all;
+ };
+ };
+
+};
diff --git a/arch/riscv/dts/ast2700.dtsi b/arch/riscv/dts/ast2700.dtsi
new file mode 100644
index 00000000000..9b482dfdd84
--- /dev/null
+++ b/arch/riscv/dts/ast2700.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ model = "Aspeed AST2700 Ibex BootMCU";
+ compatible = "aspeed,ast2700-ibex";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "lowrisc,ibex";
+ device_type = "cpu";
+ reg = <0>;
+ comptaible = "riscv";
+ riscv,isa = "rv32imc";
+ };
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x80000000>;
+ };
+
+ soc0: soc@12000000 {
+ compatible = "aspeed,soc1","simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sdrammc: sdrammc@12c00000 {
+ compatible = "aspeed,ast2700-sdrammc";
+ reg = <0x12c00000 0x3000>, <0x13000000 0x1000>;
+ aspeed,scu0 = <&syscon0>;
+ aspeed,scu1 = <&syscon1>;
+ };
+
+ syscon0: syscon@12c02000 {
+ compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
+ reg = <0x12c02000 0x1000>;
+ ranges = <0 0x12c02000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ soc1: soc@14000000 {
+ compatible = "aspeed,soc1","simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon1: syscon@14c02000 {
+ compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd";
+ reg = <0x14c02000 0x1000>;
+ ranges = <0 0x14c02000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ uart12: serial@14c33b00 {
+ compatible = "ns16550a";
+ reg = <0x14c33b00 0x20>;
+ reg-shift = <2>;
+ no-loopback-test;
+ clock-frequency = <1846153>;
+ status = "disabled";
+ };
+
+ ast_ibex_timer: timer {
+ compatible = "aspeed,ast2700-ibex-timer";
+ clock-frequency = <200000000>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 4b0143450e8..8a7386b76e6 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo,cv1800.h>
/ {
#address-cells = <1>;
@@ -45,13 +46,6 @@
#clock-cells = <0>;
};
- sdhci_clk: sdhci-clock {
- compatible = "fixed-clock";
- clock-frequency = <375000000>;
- clock-output-names = "sdhci_clk";
- #clock-cells = <0>;
- };
-
eth_csrclk: eth-csrclk {
compatible = "fixed-clock";
clock-frequency = <250000000>;
@@ -66,13 +60,6 @@
#clock-cells = <0x0>;
};
- spif_clk: spi-flash-clock {
- compatible = "fixed-clock";
- clock-frequency = <300000000>;
- clock-output-names = "spif_clk";
- #clock-cells = <0>;
- };
-
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -163,8 +150,8 @@
compatible = "sophgo,cv1800b-dwmac";
reg = <0x04070000 0x10000>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&eth_csrclk>, <&eth_ptpclk>;
- clock-names = "stmmaceth", "ptp_ref";
+ clocks = <&clk CLK_ETH0_500M>, <&clk CLK_AXI4_ETH0>;
+ clock-names = "stmmaceth", "pclk";
status = "disabled";
};
@@ -172,7 +159,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -182,7 +170,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -192,7 +181,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -202,7 +192,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -212,7 +203,8 @@
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
+ clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -222,8 +214,8 @@
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4310000 0x1000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sdhci_clk>;
- clock-names = "core";
+ clocks = <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>;
+ clock-names = "core", "bus";
status = "disabled";
};
@@ -232,7 +224,7 @@
reg = <0x10000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&spif_clk>;
+ clocks = <&clk CLK_AHB_SF>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
diff --git a/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h b/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h
new file mode 100644
index 00000000000..fbbcdb25cca
--- /dev/null
+++ b/arch/riscv/include/asm/arch-ast2700/fmc_hdr.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#ifndef __ASM_AST2700_FMC_HDR_H__
+#define __ASM_AST2700_FMC_HDR_H__
+
+#include <linux/types.h>
+
+#define HDR_MAGIC 0x48545341 /* ASTH */
+#define HDR_PB_MAX 30
+
+enum prebuilt_type {
+ PBT_END_MARK = 0x0,
+
+ PBT_DDR4_PMU_TRAIN_IMEM,
+ PBT_DDR4_PMU_TRAIN_DMEM,
+ PBT_DDR4_2D_PMU_TRAIN_IMEM,
+ PBT_DDR4_2D_PMU_TRAIN_DMEM,
+ PBT_DDR5_PMU_TRAIN_IMEM,
+ PBT_DDR5_PMU_TRAIN_DMEM,
+ PBT_DP_FW,
+ PBT_UEFI_X64_AST2700,
+
+ PBT_NUM
+};
+
+struct fmc_hdr_preamble {
+ uint32_t magic;
+ uint32_t version;
+};
+
+struct fmc_hdr_body {
+ uint32_t fmc_size;
+ union {
+ struct {
+ uint32_t type;
+ uint32_t size;
+ } pbs[0];
+ uint32_t raz[29];
+ };
+};
+
+struct fmc_hdr {
+ struct fmc_hdr_preamble preamble;
+ struct fmc_hdr_body body;
+} __packed;
+
+int fmc_hdr_get_prebuilt(uint32_t type, uint32_t *ofst, uint32_t *size);
+
+#endif
diff --git a/arch/riscv/include/asm/arch-ast2700/scu.h b/arch/riscv/include/asm/arch-ast2700/scu.h
new file mode 100644
index 00000000000..1aa7d38bace
--- /dev/null
+++ b/arch/riscv/include/asm/arch-ast2700/scu.h
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef __ASM_AST2700_SCU_H__
+#define __ASM_AST2700_SCU_H__
+
+/* SCU0: CPU-die SCU */
+#define SCU0_HWSTRAP 0x010
+#define SCU0_HWSTRAP_DIS_RVAS BIT(30)
+#define SCU0_HWSTRAP_DIS_WDTFULL BIT(25)
+#define SCU0_HWSTRAP_DISARMICE_TZ BIT(22)
+#define SCU0_HWSTRAP_DISABLE_XHCI BIT(21)
+#define SCU0_HWSTRAP_BOOTEMMCSPEED BIT(20)
+#define SCU0_HWSTRAP_VGA_CC BIT(18)
+#define SCU0_HWSTRAP_EN_OPROM BIT(17)
+#define SCU0_HWSTRAP_DISARMICE BIT(16)
+#define SCU0_HWSTRAP_TSPRSNTSEL BIT(9)
+#define SCU0_HWSTRAP_DISDEBUG BIT(8)
+#define SCU0_HWSTRAP_HCLKHPLL BIT(7)
+#define SCU0_HWSTRAP_HCLKSEL GENMASK(6, 5)
+#define SCU0_HWSTRAP_CPUHPLL BIT(4)
+#define SCU0_HWSTRAP_HPLLFREQ GENMASK(3, 2)
+#define SCU0_HWSTRAP_BOOTSPI BIT(1)
+#define SCU0_HWSTRAP_HWSTRAP_DISCPU BIT(0)
+#define SCU0_DBGCTL 0x0c8
+#define SCU0_DBGCTL_MASK GENMASK(14, 0)
+#define SCU0_DBGCTL_UARTDBG BIT(1)
+#define SCU0_RSTCTL1 0x200
+#define SCU0_RSTCTL1_EMMC BIT(17)
+#define SCU0_RSTCTL1_HACE BIT(4)
+#define SCU0_RSTCTL1_CLR 0x204
+#define SCU0_RSTCTL1_CLR_EMMC BIT(17)
+#define SCU0_RSTCTL1_CLR_HACE BIT(4)
+#define SCU0_CLKGATE1 0x240
+#define SCU0_CLKGATE1_EMMC BIT(27)
+#define SCU0_CLKGATE1_HACE BIT(13)
+#define SCU0_CLKGATE1_DDRPHY BIT(11)
+#define SCU0_CLKGATE1_CLR 0x244
+#define SCU0_CLKGATE1_CLR_EMMC BIT(27)
+#define SCU0_CLKGATE1_CLR_HACE BIT(13)
+#define SCU0_CLKGATE1_CLR_DDRPHY BIT(11)
+#define SCU0_VGA0_SCRATCH 0x900
+#define SCU0_VGA0_SCRATCH_DRAM_INIT BIT(6)
+#define SCU0_PCI_MISC70 0xa70
+#define SCU0_PCI_MISC70_EN_PCIEXHCI0 BIT(3)
+#define SCU0_PCI_MISC70_EN_PCIEEHCI0 BIT(2)
+#define SCU0_PCI_MISC70_EN_PCIEVGA0 BIT(0)
+#define SCU0_PCI_MISC80 0xa80
+#define SCU0_PCI_MISC80_EN_PCIEXHCI1 BIT(3)
+#define SCU0_PCI_MISC80_EN_PCIEEHCI1 BIT(2)
+#define SCU0_PCI_MISC80_EN_PCIEVGA1 BIT(0)
+#define SCU0_PCI_MISCF0 0xaf0
+#define SCU0_PCI_MISCF0_EN_PCIEXHCI1 BIT(3)
+#define SCU0_PCI_MISCF0_EN_PCIEEHCI1 BIT(2)
+#define SCU0_PCI_MISCF0_EN_PCIEVGA1 BIT(0)
+#define SCU0_WPROT1 0xe04
+#define SCU0_WPROT1_0C8 BIT(18)
+
+/* SCU1: IO-die SCU */
+#define SCU1_REVISION 0x000
+#define SCU1_REVISION_HWID GENMASK(23, 16)
+#define SCU1_REVISION_CHIP_EFUSE GENMASK(15, 8)
+#define SCU1_HWSTRAP1 0x010
+#define SCU1_HWSTRAP1_DIS_CPTRA BIT(30)
+#define SCU1_HWSTRAP1_RECOVERY_USB_PORT GENMASK(29, 28)
+#define SCU1_HWSTRAP1_RECOVERY_INTERFACE GENMASK(27, 26)
+#define SCU1_HWSTRAP1_RECOVERY_I3C (BIT(26) | BIT(27))
+#define SCU1_HWSTRAP1_RECOVERY_I2C BIT(27)
+#define SCU1_HWSTRAP1_RECOVERY_USB BIT(26)
+#define SCU1_HWSTRAP1_SPI_FLASH_4_BYTE_MODE BIT(25)
+#define SCU1_HWSTRAP1_SPI_FLASH_WAIT_READY BIT(24)
+#define SCU1_HWSTRAP1_BOOT_UFS BIT(23)
+#define SCU1_HWSTRAP1_DIS_ROM BIT(22)
+#define SCU1_HWSTRAP1_DIS_CPTRAJTAG BIT(20)
+#define SCU1_HWSTRAP1_UARTDBGSEL BIT(19)
+#define SCU1_HWSTRAP1_DIS_UARTDBG BIT(18)
+#define SCU1_HWSTRAP1_DIS_WDTFULL BIT(17)
+#define SCU1_HWSTRAP1_DISDEBUG1 BIT(16)
+#define SCU1_HWSTRAP1_LTPI0_IO_DRIVING GENMASK(15, 14)
+#define SCU1_HWSTRAP1_ACPI_1 BIT(13)
+#define SCU1_HWSTRAP1_ACPI_0 BIT(12)
+#define SCU1_HWSTRAP1_BOOT_EMMC_UFS BIT(11)
+#define SCU1_HWSTRAP1_DDR4 BIT(10)
+#define SCU1_HWSTRAP1_LOW_SECURE BIT(8)
+#define SCU1_HWSTRAP1_EN_EMCS BIT(7)
+#define SCU1_HWSTRAP1_EN_GPIOPT BIT(6)
+#define SCU1_HWSTRAP1_EN_SECBOOT BIT(5)
+#define SCU1_HWSTRAP1_EN_RECOVERY_BOOT BIT(4)
+#define SCU1_HWSTRAP1_LTPI0_EN BIT(3)
+#define SCU1_HWSTRAP1_LTPI_IDX BIT(2)
+#define SCU1_HWSTRAP1_LTPI1_EN BIT(1)
+#define SCU1_HWSTRAP1_LTPI_MODE BIT(0)
+#define SCU1_HWSTRAP2 0x030
+#define SCU1_HWSTRAP2_FMC_ABR_SINGLE_FLASH BIT(29)
+#define SCU1_HWSTRAP2_FMC_ABR_CS_SWAP_DIS BIT(28)
+#define SCU1_HWSTRAP2_SPI_TPM_PCR_EXT_EN BIT(27)
+#define SCU1_HWSTRAP2_SPI_TPM_HASH_ALGO GENMASK(26, 25)
+#define SCU1_HWSTRAP2_BOOT_SPI_FREQ GENMASK(24, 23)
+#define SCU1_HWSTRAP2_RESERVED GENMASK(22, 19)
+#define SCU1_HWSTRAP2_FWSPI_CRTM GENMASK(18, 17)
+#define SCU1_HWSTRAP2_EN_FWSPIAUX BIT(16)
+#define SCU1_HWSTRAP2_FWSPISIZE GENMASK(15, 13)
+#define SCU1_HWSTRAP2_DIS_REC BIT(12)
+#define SCU1_HWSTRAP2_EN_CPTRA_DBG BIT(11)
+#define SCU1_HWSTRAP2_TPM_PCR_INDEX GENMASK(6, 2)
+#define SCU1_HWSTRAP2_ROM_CLEAR_SRAM BIT(1)
+#define SCU1_HWSTRAP2_ABR BIT(0)
+#define SCU1_RSTLOG0 0x050
+#define SCU1_RSTLOG0_BMC_CPU BIT(12)
+#define SCU1_RSTLOG0_ABR BIT(2)
+#define SCU1_RSTLOG0_EXTRSTN BIT(1)
+#define SCU1_RSTLOG0_SRST BIT(0)
+#define SCU1_MISC1 0x0c0
+#define SCU1_MISC1_UARTDBG_ROUTE GENMASK(23, 22)
+#define SCU1_MISC1_UART12_ROUTE GENMASK(21, 20)
+#define SCU1_DBGCTL 0x0c8
+#define SCU1_DBGCTL_MASK GENMASK(7, 0)
+#define SCU1_DBGCTL_UARTDBG BIT(6)
+#define SCU1_RNG_DATA 0x0f4
+#define SCU1_RSTCTL1 0x200
+#define SCU1_RSTCTL1_I3C(x) (BIT(16) << (x))
+#define SCU1_RSTCTL1_CLR 0x204
+#define SCU1_RSTCTL1_CLR_I3C(x) (BIT(16) << (x))
+#define SCU1_RSTCTL2 0x220
+#define SCU1_RSTCTL2_LTPI1 BIT(22)
+#define SCU1_RSTCTL2_LTPI0 BIT(20)
+#define SCU1_RSTCTL2_I2C BIT(15)
+#define SCU1_RSTCTL2_CPTRA BIT(9)
+#define SCU1_RSTCTL2_CLR 0x224
+#define SCU1_RSTCTL2_CLR_I2C BIT(15)
+#define SCU1_RSTCTL2_CLR_CPTRA BIT(9)
+#define SCU1_CLKGATE1 0x240
+#define SCU1_CLKGATE1_I3C(x) (BIT(16) << (x))
+#define SCU1_CLKGATE1_I2C BIT(15)
+#define SCU1_CLKGATE1_CLR 0x244
+#define SCU1_CLKGATE1_CLR_I3C(x) (BIT(16) << (x))
+#define SCU1_CLKGATE1_CLR_I2C BIT(15)
+#define SCU1_CLKGATE2 0x260
+#define SCU1_CLKGATE2_LTPI1_TX BIT(19)
+#define SCU1_CLKGATE2_LTPI_AHB BIT(10)
+#define SCU1_CLKGATE2_LTPI0_TX BIT(9)
+#define SCU1_CLKGATE2_CLR 0x264
+
+#endif
diff --git a/arch/riscv/include/asm/arch-ast2700/sdram.h b/arch/riscv/include/asm/arch-ast2700/sdram.h
new file mode 100644
index 00000000000..daf48dd6ed1
--- /dev/null
+++ b/arch/riscv/include/asm/arch-ast2700/sdram.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef __ASM_AST2700_SDRAM_H__
+#define __ASM_AST2700_SDRAM_H__
+
+struct sdrammc_regs {
+ u32 prot_key;
+ u32 intr_status;
+ u32 intr_clear;
+ u32 intr_mask;
+ u32 mcfg;
+ u32 mctl;
+ u32 msts;
+ u32 error_status;
+ u32 actime1;
+ u32 actime2;
+ u32 actime3;
+ u32 actime4;
+ u32 actime5;
+ u32 actime6;
+ u32 actime7;
+ u32 dfi_timing;
+ u32 dcfg;
+ u32 dctl;
+ u32 mrctl;
+ u32 mrwr;
+ u32 mrrd;
+ u32 mr01;
+ u32 mr23;
+ u32 mr45;
+ u32 mr67;
+ u32 refctl;
+ u32 refmng_ctl;
+ u32 refsts;
+ u32 zqctl;
+ u32 ecc_addr_range;
+ u32 ecc_failure_status;
+ u32 ecc_failure_addr;
+ u32 ecc_test_control;
+ u32 ecc_test_status;
+ u32 arbctl;
+ u32 enccfg;
+ u32 protect_lock_set;
+ u32 protect_lock_status;
+ u32 protect_lock_reset;
+ u32 enc_min_addr;
+ u32 enc_max_addr;
+ u32 enc_key[4];
+ u32 enc_iv[3];
+ u32 bistcfg;
+ u32 bist_addr;
+ u32 bist_size;
+ u32 bist_patt;
+ u32 bist_res;
+ u32 bist_fail_addr;
+ u32 bist_fail_data[4];
+ u32 reserved2[2];
+ u32 debug_control;
+ u32 debug_status;
+ u32 phy_intf_status;
+ u32 testcfg;
+ u32 gfmcfg;
+ u32 gfm0ctl;
+ u32 gfm1ctl;
+ u32 reserved3[0xf8];
+};
+
+#define DRAMC_UNLK_KEY 0x1688a8a8
+
+/* offset 0x04 */
+#define DRAMC_IRQSTA_PWRCTL_ERR BIT(16)
+#define DRAMC_IRQSTA_PHY_ERR BIT(15)
+#define DRAMC_IRQSTA_LOWPOWER_DONE BIT(12)
+#define DRAMC_IRQSTA_FREQ_CHG_DONE BIT(11)
+#define DRAMC_IRQSTA_REF_DONE BIT(10)
+#define DRAMC_IRQSTA_ZQ_DONE BIT(9)
+#define DRAMC_IRQSTA_BIST_DONE BIT(8)
+#define DRAMC_IRQSTA_ECC_RCVY_ERR BIT(5)
+#define DRAMC_IRQSTA_ECC_ERR BIT(4)
+#define DRAMC_IRQSTA_PROT_ERR BIT(3)
+#define DRAMC_IRQSTA_OVERSZ_ERR BIT(2)
+#define DRAMC_IRQSTA_MR_DONE BIT(1)
+#define DRAMC_IRQSTA_PHY_INIT_DONE BIT(0)
+
+/* offset 0x14 */
+#define DRAMC_MCTL_WB_SOFT_RESET BIT(24)
+#define DRAMC_MCTL_PHY_CLK_DIS BIT(18)
+#define DRAMC_MCTL_PHY_RESET BIT(17)
+#define DRAMC_MCTL_PHY_POWER_ON BIT(16)
+#define DRAMC_MCTL_FREQ_CHG_START BIT(3)
+#define DRAMC_MCTL_PHY_LOWPOWER_START BIT(2)
+#define DRAMC_MCTL_SELF_REF_START BIT(1)
+#define DRAMC_MCTL_PHY_INIT_START BIT(0)
+
+/* offset 0x40 */
+#define DRAMC_DFICFG_WD_POL BIT(18)
+#define DRAMC_DFICFG_CKE_OUT BIT(17)
+#define DRAMC_DFICFG_RESET BIT(16)
+
+/* offset 0x48 */
+#define DRAMC_MRCTL_ERR_STATUS BIT(31)
+#define DRAMC_MRCTL_READY_STATUS BIT(30)
+#define DRAMC_MRCTL_MR_ADDR BIT(8)
+#define DRAMC_MRCTL_CMD_DLL_RST BIT(7)
+#define DRAMC_MRCTL_CMD_DQ_SEL BIT(6)
+#define DRAMC_MRCTL_CMD_TYPE BIT(2)
+#define DRAMC_MRCTL_CMD_WR_CTL BIT(1)
+#define DRAMC_MRCTL_CMD_START BIT(0)
+
+/* offset 0xC0 */
+#define DRAMC_BISTRES_RUNNING BIT(10)
+#define DRAMC_BISTRES_FAIL BIT(9)
+#define DRAMC_BISTRES_DONE BIT(8)
+#define DRAMC_BISTCFG_INIT_MODE BIT(7)
+#define DRAMC_BISTCFG_PMODE GENMASK(6, 4)
+#define DRAMC_BISTCFG_BMODE GENMASK(3, 2)
+#define DRAMC_BISTCFG_ENABLE BIT(1)
+#define DRAMC_BISTCFG_START BIT(0)
+#define BIST_PMODE_CRC (3)
+#define BIST_BMODE_RW_SWITCH (3)
+
+/* DRAMC048 MR Control Register */
+#define MR_TYPE_SHIFT 2
+#define MR_RW (0 << MR_TYPE_SHIFT)
+#define MR_MPC BIT(2)
+#define MR_VREFCS (2 << MR_TYPE_SHIFT)
+#define MR_VREFCA (3 << MR_TYPE_SHIFT)
+#define MR_ADDRESS_SHIFT 8
+#define MR_ADDR(n) (((n) << MR_ADDRESS_SHIFT) | DRAMC_MRCTL_CMD_WR_CTL)
+#define MR_NUM_SHIFT 4
+#define MR_NUM(n) ((n) << MR_NUM_SHIFT)
+#define MR_DLL_RESET BIT(7)
+#define MR_1T_MODE BIT(16)
+
+#endif
diff --git a/arch/riscv/include/asm/arch-ast2700/sli.h b/arch/riscv/include/asm/arch-ast2700/sli.h
new file mode 100644
index 00000000000..42f0f9ac93d
--- /dev/null
+++ b/arch/riscv/include/asm/arch-ast2700/sli.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) Aspeed Technology Inc.
+ */
+#ifndef __ASM_AST2700_SLI_H__
+#define __ASM_AST2700_SLI_H__
+
+#define SLI_CPU_ADRBASE 0x12c17000
+#define SLI_IOD_ADRBASE 0x14c1e000
+#define SLIM_CPU_BASE (SLI_CPU_ADRBASE + 0x000)
+#define SLIH_CPU_BASE (SLI_CPU_ADRBASE + 0x200)
+#define SLIV_CPU_BASE (SLI_CPU_ADRBASE + 0x400)
+#define SLIM_IOD_BASE (SLI_IOD_ADRBASE + 0x000)
+#define SLIH_IOD_BASE (SLI_IOD_ADRBASE + 0x200)
+#define SLIV_IOD_BASE (SLI_IOD_ADRBASE + 0x400)
+
+#define SLI_CTRL_I 0x00
+#define SLIV_RAW_MODE BIT(15)
+#define SLI_TX_MODE BIT(14)
+#define SLI_RX_PHY_LAH_SEL_REV BIT(13)
+#define SLI_RX_PHY_LAH_SEL_NEG BIT(12)
+#define SLI_AUTO_SEND_TRN_OFF BIT(8)
+#define SLI_CLEAR_BUS BIT(6)
+#define SLI_TRANS_EN BIT(5)
+#define SLI_CLEAR_RX BIT(2)
+#define SLI_CLEAR_TX BIT(1)
+#define SLI_RESET_TRIGGER BIT(0)
+#define SLI_CTRL_II 0x04
+#define SLI_CTRL_III 0x08
+#define SLI_CLK_SEL GENMASK(31, 28)
+#define SLI_CLK_500M 0x6
+#define SLI_CLK_200M 0x3
+#define SLI_PHYCLK_SEL GENMASK(27, 24)
+#define SLI_PHYCLK_25M 0x0
+#define SLI_PHYCLK_800M 0x1
+#define SLI_PHYCLK_400M 0x2
+#define SLI_PHYCLK_200M 0x3
+#define SLI_PHYCLK_788M 0x5
+#define SLI_PHYCLK_500M 0x6
+#define SLI_PHYCLK_250M 0x7
+#define SLIH_PAD_DLY_TX1 GENMASK(23, 18)
+#define SLIH_PAD_DLY_TX0 GENMASK(17, 12)
+#define SLIH_PAD_DLY_RX1 GENMASK(11, 6)
+#define SLIH_PAD_DLY_RX0 GENMASK(5, 0)
+#define SLIM_PAD_DLY_RX3 GENMASK(23, 18)
+#define SLIM_PAD_DLY_RX2 GENMASK(17, 12)
+#define SLIM_PAD_DLY_RX1 GENMASK(11, 6)
+#define SLIM_PAD_DLY_RX0 GENMASK(5, 0)
+#define SLI_CTRL_IV 0x0c
+#define SLIM_PAD_DLY_TX3 GENMASK(23, 18)
+#define SLIM_PAD_DLY_TX2 GENMASK(17, 12)
+#define SLIM_PAD_DLY_TX1 GENMASK(11, 6)
+#define SLIM_PAD_DLY_TX0 GENMASK(5, 0)
+#define SLI_INTR_EN 0x10
+#define SLI_INTR_STATUS 0x14
+#define SLI_INTR_RX_SYNC BIT(15)
+#define SLI_INTR_RX_ERR BIT(13)
+#define SLI_INTR_RX_NACK BIT(12)
+#define SLI_INTR_RX_TRAIN_PKT BIT(10)
+#define SLI_INTR_RX_DISCONN BIT(6)
+#define SLI_INTR_TX_SUSPEND BIT(4)
+#define SLI_INTR_TX_TRAIN BIT(3)
+#define SLI_INTR_TX_IDLE BIT(2)
+#define SLI_INTR_RX_SUSPEND BIT(1)
+#define SLI_INTR_RX_IDLE BIT(0)
+#define SLI_INTR_RX_ERRORS \
+ (SLI_INTR_RX_ERR | SLI_INTR_RX_NACK | SLI_INTR_RX_DISCONN)
+
+#define SLIM_MARB_FUNC_I 0x60
+#define SLIM_SLI_MARB_RR BIT(0)
+
+#define SLI_TARGET_PHYCLK SLI_PHYCLK_400M
+#define SLIH_DEFAULT_DELAY 11
+#if (SLI_TARGET_PHYCLK == SLI_PHYCLK_800M) || (SLI_TARGET_PHYCLK == SLI_PHYCLK_788M)
+#define SLIM_DEFAULT_DELAY 5
+#define SLIM_LAH_CONFIG 1
+#else
+#define SLIM_DEFAULT_DELAY 12
+#define SLIM_LAH_CONFIG 0
+#endif
+#endif
+int sli_init(void);
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
index 35f1368b837..2f2994c4ddc 100644
--- a/arch/riscv/include/asm/bitops.h
+++ b/arch/riscv/include/asm/bitops.h
@@ -138,6 +138,43 @@ static inline unsigned long ffz(unsigned long word)
return k;
}
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+ unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG);
+ unsigned long result = offset & ~(BITS_PER_LONG - 1);
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= (BITS_PER_LONG - 1);
+ if (offset) {
+ tmp = *(p++);
+ tmp |= ~0UL >> (BITS_PER_LONG - offset);
+ if (size < BITS_PER_LONG)
+ goto found_first;
+ if (~tmp)
+ goto found_middle;
+ size -= BITS_PER_LONG;
+ result += BITS_PER_LONG;
+ }
+ while (size & ~(BITS_PER_LONG - 1)) {
+ tmp = *(p++);
+ if (~tmp)
+ goto found_middle;
+ result += BITS_PER_LONG;
+ size -= BITS_PER_LONG;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ tmp |= ~0UL << size;
+found_middle:
+ return result + ffz(tmp);
+}
+
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
@@ -158,6 +195,9 @@ static inline unsigned long ffz(unsigned long word)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
+#define find_first_zero_bit(addr, size) \
+ find_next_zero_bit((addr), (size), 0)
+
#define test_and_set_bit __test_and_set_bit
#define test_and_clear_bit __test_and_clear_bit
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index f9a1428a486..714cc92d03e 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -34,9 +34,8 @@ static void show_efi_loaded_images(uintptr_t epc)
efi_print_image_infos((void *)epc);
}
-static void show_regs(struct pt_regs *regs)
+static void __maybe_unused show_regs(struct pt_regs *regs)
{
-#ifdef CONFIG_SHOW_REGS
printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n",
regs->sp, regs->gp, regs->tp);
printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n",
@@ -57,7 +56,6 @@ static void show_regs(struct pt_regs *regs)
regs->s10, regs->s11, regs->t3);
printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n",
regs->t4, regs->t5, regs->t6);
-#endif
}
static void __maybe_unused show_backtrace(struct pt_regs *regs)
@@ -157,7 +155,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n",
epc - gd->reloc_off, regs->ra - gd->reloc_off);
- show_regs(regs);
+ if (CONFIG_IS_ENABLED(SHOW_REGS))
+ show_regs(regs);
if (CONFIG_IS_ENABLED(FRAMEPOINTER))
show_backtrace(regs);
show_code(epc);
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 02:12:53 +0000