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-rw-r--r--arch/riscv/cpu/k1/Kconfig1
-rw-r--r--arch/riscv/dts/binman.dtsi10
-rw-r--r--arch/riscv/dts/cv18xx.dtsi14
-rw-r--r--arch/riscv/dts/k1.dtsi35
-rw-r--r--arch/riscv/dts/starfive-visionfive2-binman.dtsi76
-rw-r--r--arch/riscv/lib/crt0_riscv_efi.S1
6 files changed, 34 insertions, 103 deletions
diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig
index d9cd8dce964..14201df80f2 100644
--- a/arch/riscv/cpu/k1/Kconfig
+++ b/arch/riscv/cpu/k1/Kconfig
@@ -13,6 +13,7 @@ config SPACEMIT_K1
imply RISCV_ACLINT if RISCV_MMODE
imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
imply CMD_CPU
+ imply DM_RESET
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 0405faca574..ceb916b74a7 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -82,8 +82,9 @@
};
};
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
@fdt-SEQ {
+ fit,operation = "gen-fdt-nodes";
description = "NAME";
type = "flat_dt";
compression = "none";
@@ -92,9 +93,12 @@
};
configurations {
+
+#ifndef CONFIG_MULTI_DTB_FIT
default = "conf-1";
+#endif
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
@conf-SEQ {
#else
conf-1 {
@@ -115,7 +119,7 @@
#endif
#endif /* CONFIG_OPTEE */
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
fdt = "fdt-SEQ";
#endif
};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 8a7386b76e6..6fac247e7ac 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -46,20 +46,6 @@
#clock-cells = <0>;
};
- eth_csrclk: eth-csrclk {
- compatible = "fixed-clock";
- clock-frequency = <250000000>;
- clock-output-names = "eth_csrclk";
- #clock-cells = <0x0>;
- };
-
- eth_ptpclk: eth-ptpclk {
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- clock-output-names = "eth_ptpclk";
- #clock-cells = <0x0>;
- };
-
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 514be453dba..7c0f1b928e2 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -327,7 +327,7 @@
ranges;
uart0: serial@d4017000 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017000 0x0 0x100>;
interrupts = <42>;
clock-frequency = <14857000>;
@@ -337,7 +337,7 @@
};
uart2: serial@d4017100 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017100 0x0 0x100>;
interrupts = <44>;
clock-frequency = <14857000>;
@@ -347,7 +347,7 @@
};
uart3: serial@d4017200 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017200 0x0 0x100>;
interrupts = <45>;
clock-frequency = <14857000>;
@@ -357,7 +357,7 @@
};
uart4: serial@d4017300 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017300 0x0 0x100>;
interrupts = <46>;
clock-frequency = <14857000>;
@@ -367,7 +367,7 @@
};
uart5: serial@d4017400 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017400 0x0 0x100>;
interrupts = <47>;
clock-frequency = <14857000>;
@@ -377,7 +377,7 @@
};
uart6: serial@d4017500 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017500 0x0 0x100>;
interrupts = <48>;
clock-frequency = <14857000>;
@@ -387,7 +387,7 @@
};
uart7: serial@d4017600 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017600 0x0 0x100>;
interrupts = <49>;
clock-frequency = <14857000>;
@@ -397,7 +397,7 @@
};
uart8: serial@d4017700 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017700 0x0 0x100>;
interrupts = <50>;
clock-frequency = <14857000>;
@@ -407,7 +407,7 @@
};
uart9: serial@d4017800 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017800 0x0 0x100>;
interrupts = <51>;
clock-frequency = <14857000>;
@@ -447,7 +447,7 @@
};
sec_uart1: serial@f0612000 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xf0612000 0x0 0x100>;
interrupts = <43>;
clock-frequency = <14857000>;
@@ -455,5 +455,20 @@
reg-io-width = <4>;
status = "reserved"; /* for TEE usage */
};
+
+ reset: reset-controller@d4050000 {
+ compatible = "spacemit,k1-reset";
+ reg = <0x0 0xd4050000 0x0 0x209c>,
+ <0x0 0xd4282800 0x0 0x400>,
+ <0x0 0xd4015000 0x0 0x1000>,
+ <0x0 0xd4090000 0x0 0x1000>,
+ <0x0 0xd4282c00 0x0 0x400>,
+ <0x0 0xd8440000 0x0 0x98>,
+ <0x0 0xc0000000 0x0 0x4280>,
+ <0x0 0xf0610000 0x0 0x20>;
+ reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2";
+ #reset-cells = <1>;
+ status = "disabled";
+ };
};
}; \ No newline at end of file
diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
index 4cce001e80d..05787bdb92d 100644
--- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
@@ -13,82 +13,6 @@
};
&binman {
- itb {
- fit {
- images {
- fdt-jh7110-milkv-mars {
- description = "jh7110-milkv-mars";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb";
- };
- };
-
- fdt-jh7110-pine64-star64 {
- description = "jh7110-pine64-star64";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb";
- };
- };
-
- fdt-jh7110-starfive-visionfive-2-v1.2a {
- description = "jh7110-starfive-visionfive-2-v1.2a";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
- };
- };
-
- fdt-jh7110-starfive-visionfive-2-v1.3b {
- description = "jh7110-starfive-visionfive-2-v1.3b";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
- };
- };
- };
-
- configurations {
- conf-jh7110-milkv-mars {
- description = "jh7110-milkv-mars";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-milkv-mars";
- };
-
- conf-jh7110-pine64-star64 {
- description = "jh7110-pine64-star64";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-pine64-star64";
- };
-
- conf-jh7110-starfive-visionfive-2-v1.2a {
- description = "jh7110-starfive-visionfive-2-v1.2a";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a";
- };
-
- conf-jh7110-starfive-visionfive-2-v1.3b {
- description = "jh7110-starfive-visionfive-2-v1.3b";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b";
- };
- };
- };
- };
-
spl-img {
filename = "spl/u-boot-spl.bin.normal.out";
diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S
index 9eacbe4a859..f170e4b26d6 100644
--- a/arch/riscv/lib/crt0_riscv_efi.S
+++ b/arch/riscv/lib/crt0_riscv_efi.S
@@ -179,6 +179,7 @@ section_table:
IMAGE_SCN_CNT_INITIALIZED_DATA)
.align 12
+ .globl _start
_start:
addi sp, sp, -(SIZE_LONG * 3)
SAVE_LONG(a0, 0)
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 09:05:03 +0000