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-rw-r--r--arch/riscv/Makefile2
-rw-r--r--arch/riscv/cpu/k1/Kconfig1
-rw-r--r--arch/riscv/cpu/start.S4
-rw-r--r--arch/riscv/cpu/u-boot-spl.lds2
-rw-r--r--arch/riscv/cpu/u-boot.lds3
-rw-r--r--arch/riscv/dts/binman.dtsi12
-rw-r--r--arch/riscv/dts/cv18xx.dtsi14
-rw-r--r--arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi7
-rw-r--r--arch/riscv/dts/jh7110-u-boot.dtsi4
-rw-r--r--arch/riscv/dts/k1-bananapi-f3.dts3
-rw-r--r--arch/riscv/dts/k1-pinctrl.dtsi19
-rw-r--r--arch/riscv/dts/k1.dtsi43
-rw-r--r--arch/riscv/dts/starfive-visionfive2-binman.dtsi77
-rw-r--r--arch/riscv/include/asm/arch-jh7110/gpio.h5
-rw-r--r--arch/riscv/include/asm/setjmp.h15
-rw-r--r--arch/riscv/lib/Makefile9
-rw-r--r--arch/riscv/lib/board.c19
-rw-r--r--arch/riscv/lib/bootm.c4
-rw-r--r--arch/riscv/lib/cache.c6
-rw-r--r--arch/riscv/lib/setjmp.S11
20 files changed, 132 insertions, 128 deletions
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 4e6f347038d..6f80f4a7108 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -48,7 +48,7 @@ endif
ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
-mcmodel=$(CMODEL)
-ifeq ($(CONFIG_$(XPL_)FRAMEPOINTER),y)
+ifeq ($(CONFIG_$(PHASE_)FRAMEPOINTER),y)
ARCH_FLAGS += -fno-omit-frame-pointer
endif
diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig
index d9cd8dce964..14201df80f2 100644
--- a/arch/riscv/cpu/k1/Kconfig
+++ b/arch/riscv/cpu/k1/Kconfig
@@ -13,6 +13,7 @@ config SPACEMIT_K1
imply RISCV_ACLINT if RISCV_MMODE
imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
imply CMD_CPU
+ imply DM_RESET
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 3f78932aa9d..7bafdfd390a 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -90,8 +90,8 @@ _start:
* Set stackpointer in internal/ex RAM to call board_init_f
*/
call_board_init_f:
-#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
- li t0, CONFIG_SPL_STACK
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+ li t0, CONFIG_VAL(STACK)
#else
li t0, SYS_INIT_SP_ADDR
#endif
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 907094620bd..0717833df55 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -16,6 +16,7 @@ ENTRY(_start)
SECTIONS
{
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text : {
arch/riscv/cpu/start.o (.text)
*(.text*)
@@ -46,6 +47,7 @@ SECTIONS
_end = .;
_image_binary_end = .;
+ __image_copy_end = .;
.bss : {
__bss_start = .;
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 2ffe6ba3c8f..b11ea8b56d2 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -10,6 +10,7 @@ ENTRY(_start)
SECTIONS
{
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text : {
arch/riscv/cpu/start.o (.text)
}
@@ -57,6 +58,8 @@ SECTIONS
__efi_runtime_rel_stop = .;
}
+ __image_copy_end = .;
+
/DISCARD/ : { *(.rela.plt*) }
.rela.dyn : {
__rel_dyn_start = .;
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 0405faca574..5aeeeddb59f 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -35,7 +35,7 @@
compression = "none";
load = /bits/ 64 <CONFIG_TEXT_BASE>;
- uboot_blob: blob-ext {
+ uboot_blob: u-boot-nodtb {
filename = "u-boot-nodtb.bin";
};
};
@@ -82,8 +82,9 @@
};
};
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
@fdt-SEQ {
+ fit,operation = "gen-fdt-nodes";
description = "NAME";
type = "flat_dt";
compression = "none";
@@ -92,9 +93,12 @@
};
configurations {
+
+#ifndef CONFIG_MULTI_DTB_FIT
default = "conf-1";
+#endif
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
@conf-SEQ {
#else
conf-1 {
@@ -115,7 +119,7 @@
#endif
#endif /* CONFIG_OPTEE */
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
fdt = "fdt-SEQ";
#endif
};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 8a7386b76e6..6fac247e7ac 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -46,20 +46,6 @@
#clock-cells = <0>;
};
- eth_csrclk: eth-csrclk {
- compatible = "fixed-clock";
- clock-frequency = <250000000>;
- clock-output-names = "eth_csrclk";
- #clock-cells = <0x0>;
- };
-
- eth_ptpclk: eth-ptpclk {
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- clock-output-names = "eth_ptpclk";
- #clock-cells = <0x0>;
- };
-
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
new file mode 100644
index 00000000000..ab882d07f6f
--- /dev/null
+++ b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+
+#include "jh7110-common-u-boot.dtsi"
+#include "starfive-visionfive2-binman.dtsi"
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index ce7d9e16961..a9e318c4a31 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -102,6 +102,10 @@
bootph-pre-ram;
};
+&pllclk {
+ bootph-pre-ram;
+};
+
&syscrg {
bootph-pre-ram;
};
diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts
index d2486f70906..6b5b83bcdb9 100644
--- a/arch/riscv/dts/k1-bananapi-f3.dts
+++ b/arch/riscv/dts/k1-bananapi-f3.dts
@@ -5,6 +5,7 @@
#include "k1.dtsi"
#include "binman.dtsi"
+#include "k1-pinctrl.dtsi"
/ {
model = "Banana Pi BPI-F3";
@@ -21,5 +22,7 @@
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi
new file mode 100644
index 00000000000..14e7096fbcf
--- /dev/null
+++ b/arch/riscv/dts/k1-pinctrl.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Yixun Lan <dlan@gentoo.org>
+ */
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
+
+&pinctrl {
+ uart0_2_cfg: uart0-2-cfg {
+ uart0-2-pins {
+ pinmux = <K1_PADCONF(68, 2)>,
+ <K1_PADCONF(69, 2)>;
+
+ bias-pull-up = <0>;
+ drive-strength = <32>;
+ };
+ };
+};
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 514be453dba..a633e43da32 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -327,7 +327,7 @@
ranges;
uart0: serial@d4017000 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017000 0x0 0x100>;
interrupts = <42>;
clock-frequency = <14857000>;
@@ -337,7 +337,7 @@
};
uart2: serial@d4017100 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017100 0x0 0x100>;
interrupts = <44>;
clock-frequency = <14857000>;
@@ -347,7 +347,7 @@
};
uart3: serial@d4017200 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017200 0x0 0x100>;
interrupts = <45>;
clock-frequency = <14857000>;
@@ -357,7 +357,7 @@
};
uart4: serial@d4017300 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017300 0x0 0x100>;
interrupts = <46>;
clock-frequency = <14857000>;
@@ -367,7 +367,7 @@
};
uart5: serial@d4017400 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017400 0x0 0x100>;
interrupts = <47>;
clock-frequency = <14857000>;
@@ -377,7 +377,7 @@
};
uart6: serial@d4017500 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017500 0x0 0x100>;
interrupts = <48>;
clock-frequency = <14857000>;
@@ -387,7 +387,7 @@
};
uart7: serial@d4017600 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017600 0x0 0x100>;
interrupts = <49>;
clock-frequency = <14857000>;
@@ -397,7 +397,7 @@
};
uart8: serial@d4017700 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017700 0x0 0x100>;
interrupts = <50>;
clock-frequency = <14857000>;
@@ -407,7 +407,7 @@
};
uart9: serial@d4017800 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xd4017800 0x0 0x100>;
interrupts = <51>;
clock-frequency = <14857000>;
@@ -447,7 +447,7 @@
};
sec_uart1: serial@f0612000 {
- compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+ compatible = "spacemit,k1-uart", "intel,xscale-uart";
reg = <0x0 0xf0612000 0x0 0x100>;
interrupts = <43>;
clock-frequency = <14857000>;
@@ -455,5 +455,26 @@
reg-io-width = <4>;
status = "reserved"; /* for TEE usage */
};
+
+ reset: reset-controller@d4050000 {
+ compatible = "spacemit,k1-reset";
+ reg = <0x0 0xd4050000 0x0 0x209c>,
+ <0x0 0xd4282800 0x0 0x400>,
+ <0x0 0xd4015000 0x0 0x1000>,
+ <0x0 0xd4090000 0x0 0x1000>,
+ <0x0 0xd4282c00 0x0 0x400>,
+ <0x0 0xd8440000 0x0 0x98>,
+ <0x0 0xc0000000 0x0 0x4280>,
+ <0x0 0xf0610000 0x0 0x20>;
+ reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2";
+ #reset-cells = <1>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@d401e000 {
+ compatible = "spacemit,k1-pinctrl", "pinctrl-single";
+ reg = <0x0 0xd401e000 0x0 0x400>;
+ pinctrl-single,register-width = <32>;
+ };
};
-}; \ No newline at end of file
+};
diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
index 4cce001e80d..6e083bf0537 100644
--- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
@@ -13,82 +13,6 @@
};
&binman {
- itb {
- fit {
- images {
- fdt-jh7110-milkv-mars {
- description = "jh7110-milkv-mars";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb";
- };
- };
-
- fdt-jh7110-pine64-star64 {
- description = "jh7110-pine64-star64";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb";
- };
- };
-
- fdt-jh7110-starfive-visionfive-2-v1.2a {
- description = "jh7110-starfive-visionfive-2-v1.2a";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
- };
- };
-
- fdt-jh7110-starfive-visionfive-2-v1.3b {
- description = "jh7110-starfive-visionfive-2-v1.3b";
- load = <0x40400000>;
- compression = "none";
-
- blob-ext {
- filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
- };
- };
- };
-
- configurations {
- conf-jh7110-milkv-mars {
- description = "jh7110-milkv-mars";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-milkv-mars";
- };
-
- conf-jh7110-pine64-star64 {
- description = "jh7110-pine64-star64";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-pine64-star64";
- };
-
- conf-jh7110-starfive-visionfive-2-v1.2a {
- description = "jh7110-starfive-visionfive-2-v1.2a";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a";
- };
-
- conf-jh7110-starfive-visionfive-2-v1.3b {
- description = "jh7110-starfive-visionfive-2-v1.3b";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b";
- };
- };
- };
- };
-
spl-img {
filename = "spl/u-boot-spl.bin.normal.out";
@@ -96,6 +20,7 @@
args = "-T sfspl";
u-boot-spl {
+ no-write-symbols;
};
};
};
diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
index 90aa2f8a9ed..be2a1e0d1c8 100644
--- a/arch/riscv/include/asm/arch-jh7110/gpio.h
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -63,6 +63,11 @@ enum gpio_state {
GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+#define SYS_IOMUX_DIN_DISABLED(gpi)\
+ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+ GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+ ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
#define SYS_IOMUX_SET_DS(gpio, ds) \
clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
diff --git a/arch/riscv/include/asm/setjmp.h b/arch/riscv/include/asm/setjmp.h
index 72383d43303..08687e0f92b 100644
--- a/arch/riscv/include/asm/setjmp.h
+++ b/arch/riscv/include/asm/setjmp.h
@@ -3,13 +3,9 @@
* (C) Copyright 2018 Alexander Graf <agraf@suse.de>
*/
-#ifndef _SETJMP_H_
-#define _SETJMP_H_ 1
+#ifndef _ASM_SETJMP_H_
+#define _ASM_SETJMP_H_ 1
-/*
- * This really should be opaque, but the EFI implementation wrongly
- * assumes that a 'struct jmp_buf_data' is defined.
- */
struct jmp_buf_data {
/* x2, x8, x9, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, sp */
unsigned long s_regs[12]; /* s0 - s11 */
@@ -17,9 +13,4 @@ struct jmp_buf_data {
unsigned long sp;
};
-typedef struct jmp_buf_data jmp_buf[1];
-
-int setjmp(jmp_buf jmp);
-void longjmp(jmp_buf jmp, int ret);
-
-#endif /* _SETJMP_H_ */
+#endif /* _ASM_SETJMP_H_ */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 268116f3757..189b35c24d3 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,22 +11,23 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
-ifeq ($(CONFIG_$(XPL_)RISCV_MMODE),y)
-obj-$(CONFIG_$(XPL_)RISCV_ACLINT) += aclint_ipi.o
+ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y)
+obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o
obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
else
obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
endif
obj-y += interrupts.o
-ifeq ($(CONFIG_$(XPL_)SYSRESET),)
+ifeq ($(CONFIG_$(PHASE_)SYSRESET),)
obj-y += reset.o
endif
obj-y += setjmp.o
-obj-$(CONFIG_$(XPL_)SMP) += smp.o
+obj-$(CONFIG_$(PHASE_)SMP) += smp.o
obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += fdt_fixup.o
obj-$(CONFIG_$(SPL)CMD_BDI) += bdinfo.o
+obj-$(CONFIG_OF_BOARD) += board.o
# For building EFI apps
CFLAGS_NON_EFI := -fstack-protector-strong
diff --git a/arch/riscv/lib/board.c b/arch/riscv/lib/board.c
new file mode 100644
index 00000000000..624c4eaaf4d
--- /dev/null
+++ b/arch/riscv/lib/board.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * RISC-V-specific handling of firmware FDT
+ */
+
+#include <asm/global_data.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int board_fdt_blob_setup(void **fdtp)
+{
+ if (!gd->arch.firmware_fdt_addr)
+ return -EEXIST;
+
+ *fdtp = (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
+
+ return 0;
+}
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 76c610bcee0..9544907ab1e 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -46,10 +46,6 @@ static void announce_and_cleanup(int fake)
bootstage_report();
#endif
-#ifdef CONFIG_USB_DEVICE
- udc_disconnect();
-#endif
-
board_quiesce_devices();
/*
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index 71e4937ab54..31aa30bc7d7 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <asm/insn-def.h>
#include <linux/const.h>
+#include <linux/errno.h>
#define CBO_INVAL(base) \
INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
@@ -151,3 +152,8 @@ __weak void enable_caches(void)
if (!zicbom_block_size)
log_debug("Zicbom not initialized.\n");
}
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+ return -ENOSYS;
+}
diff --git a/arch/riscv/lib/setjmp.S b/arch/riscv/lib/setjmp.S
index 99d6195827e..9e1f3d5749b 100644
--- a/arch/riscv/lib/setjmp.S
+++ b/arch/riscv/lib/setjmp.S
@@ -59,3 +59,14 @@ ENTRY(longjmp)
ret
ENDPROC(longjmp)
.popsection
+
+.pushsection .text.initjmp, "ax"
+ENTRY(initjmp)
+ /* a1: entry point address, a2: stack base, a3: stack size */
+ add a2, a2, a3
+ STORE_IDX(a1, 12)
+ STORE_IDX(a2, 13)
+ li a0, 0
+ ret
+ENDPROC(initjmp)
+.popsection
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-06 20:24:16 +0000