diff options
Diffstat (limited to 'arch/sh/cpu/sh4/cache.c')
| -rw-r--r-- | arch/sh/cpu/sh4/cache.c | 88 |
1 files changed, 42 insertions, 46 deletions
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index e1ee970a91c..6175c67e47a 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -1,50 +1,15 @@ /* - * (C) Copyright 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com> + * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <command.h> -#include <asm/processor.h> #include <asm/io.h> - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ - do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ - } while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ - do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ - } while (0) +#include <asm/processor.h> +#include <asm/system.h> #define CACHE_VALID 1 #define CACHE_UPDATED 2 @@ -53,10 +18,10 @@ static inline void cache_wback_all(void) { unsigned long addr, data, i, j; - jump_to_P2(); - for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){ + for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { - addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT) + addr = CACHE_OC_ADDRESS_ARRAY + | (j << CACHE_OC_WAY_SHIFT) | (i << CACHE_OC_ENTRY_SHIFT); data = inl(addr); if (data & CACHE_UPDATED) { @@ -65,14 +30,12 @@ static inline void cache_wback_all(void) } } } - back_to_P1(); } - #define CACHE_ENABLE 0 #define CACHE_DISABLE 1 -int cache_control(unsigned int cmd) +static int cache_control(unsigned int cmd) { unsigned long ccr; @@ -97,7 +60,7 @@ void flush_dcache_range(unsigned long start, unsigned long end) start &= ~(L1_CACHE_BYTES - 1); for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbwb %0" : /* no output */ + asm volatile ("ocbp %0" : /* no output */ : "m" (__m(v))); } } @@ -112,3 +75,36 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) : "m" (__m(v))); } } + +void flush_cache(unsigned long addr, unsigned long size) +{ + flush_dcache_range(addr , addr + size); +} + +void icache_enable(void) +{ + cache_control(CACHE_ENABLE); +} + +void icache_disable(void) +{ + cache_control(CACHE_DISABLE); +} + +int icache_status(void) +{ + return 0; +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +int dcache_status(void) +{ + return 0; +} |