diff options
Diffstat (limited to 'arch/sh/cpu/sh4/cache.c')
| -rw-r--r-- | arch/sh/cpu/sh4/cache.c | 31 |
1 files changed, 27 insertions, 4 deletions
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 0f7dfdd3cf7..56161ee72e4 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -4,13 +4,14 @@ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ -#include <common.h> #include <command.h> #include <cpu_func.h> +#include <stdio.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/processor.h> #include <asm/system.h> +#include <linux/errno.h> #define CACHE_VALID 1 #define CACHE_UPDATED 2 @@ -33,8 +34,9 @@ static inline void cache_wback_all(void) } } -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 +#define CACHE_ENABLE 0 +#define CACHE_DISABLE 1 +#define CACHE_INVALIDATE 2 static int cache_control(unsigned int cmd) { @@ -46,7 +48,9 @@ static int cache_control(unsigned int cmd) if (ccr & CCR_CACHE_ENABLE) cache_wback_all(); - if (cmd == CACHE_DISABLE) + if (cmd == CACHE_INVALIDATE) + outl(CCR_CACHE_ICI | ccr, CCR); + else if (cmd == CACHE_DISABLE) outl(CCR_CACHE_STOP, CCR); else outl(CCR_CACHE_INIT, CCR); @@ -66,6 +70,15 @@ void flush_dcache_range(unsigned long start, unsigned long end) } } +/* + * Default implementation: + * do a range flush for the entire range + */ +void flush_dcache_all(void) +{ + flush_dcache_range(0, ~0); +} + void invalidate_dcache_range(unsigned long start, unsigned long end) { u32 v; @@ -92,6 +105,11 @@ void icache_disable(void) cache_control(CACHE_DISABLE); } +void invalidate_icache_all(void) +{ + cache_control(CACHE_INVALIDATE); +} + int icache_status(void) { return 0; @@ -109,3 +127,8 @@ int dcache_status(void) { return 0; } + +int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) +{ + return -ENOSYS; +} |