14 files changed, 6 insertions, 167 deletions

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index e7979254dbf..2ff237701df 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -22,7 +22,6 @@ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
 obj-$(CONFIG_QEMU) += qemu/
-obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
 obj-$(CONFIG_INTEL_QUARK) += quark/
 obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index a009c14bd9b..9b30451b28e 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -28,9 +28,6 @@ int arch_cpu_init(void)
 	int ret;
 
 	post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-	timer_set_base(rdtsc());
-#endif
 
 	ret = x86_cpu_init_f();
 	if (ret)
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index 0edee6bd2c2..b3827951e6e 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -27,28 +27,6 @@ static struct timestamp_table *ts_table  __attribute__((section(".data")));
 
 void timestamp_init(void)
 {
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-	uint64_t base_time;
-#endif
-
-	ts_table = lib_sysinfo.tstamp_table;
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-	/*
-	 * If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
-	 * of base_time in coreboot's timestamp table as our timer base,
-	 * otherwise TSC counter value will be used.
-	 *
-	 * Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
-	 * the value of base_time in the timestamp table is still zero, so
-	 * we must exclude this case too (this is currently seen on booting
-	 * coreboot in qemu)
-	 */
-	if (ts_table && ts_table->base_time)
-		base_time = ts_table->base_time;
-	else
-		base_time = rdtsc();
-	timer_set_base(base_time);
-#endif
 	timestamp_add_now(TS_U_BOOT_INITTED);
 }
 
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 812c5e4e6be..381d83526fb 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -399,6 +399,11 @@ int x86_cpu_init_f(void)
 		}
 	}
 
+#ifdef CONFIG_I8254_TIMER
+	/* Set up the i8254 timer if required */
+	i8254_init();
+#endif
+
 	return 0;
 }
 
@@ -641,24 +646,6 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)
 
 void show_boot_progress(int val)
 {
-#if MIN_PORT80_KCLOCKS_DELAY
-	/*
-	 * Scale the time counter reading to avoid using 64 bit arithmetics.
-	 * Can't use get_timer() here becuase it could be not yet
-	 * initialized or even implemented.
-	 */
-	if (!gd->arch.tsc_prev) {
-		gd->arch.tsc_base_kclocks = rdtsc() / 1000;
-		gd->arch.tsc_prev = 0;
-	} else {
-		uint32_t now;
-
-		do {
-			now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
-		} while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
-		gd->arch.tsc_prev = now;
-	}
-#endif
 	outb(val, POST_PORT);
 }
 
diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/efi.c
index 75ba0d4844a..993ab8dcde2 100644
--- a/arch/x86/cpu/efi/efi.c
+++ b/arch/x86/cpu/efi/efi.c
@@ -10,10 +10,6 @@
 
 int arch_cpu_init(void)
 {
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-	timer_set_base(rdtsc());
-#endif
-
 	return 0;
 }
 
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 0e249a40a6f..56abd8fae35 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -5,44 +5,13 @@
 #
 # SPDX-License-Identifier:	GPL-2.0
 
-
-config NORTHBRIDGE_INTEL_SANDYBRIDGE
-	bool
-	select CACHE_MRC_BIN
-	select CPU_INTEL_MODEL_206AX
-
 config NORTHBRIDGE_INTEL_IVYBRIDGE
 	bool
 	select CACHE_MRC_BIN
-	select CPU_INTEL_MODEL_306AX
-
-if NORTHBRIDGE_INTEL_SANDYBRIDGE
-
-config VGA_BIOS_ID
-	string
-	default "8086,0106"
-
-config CACHE_MRC_SIZE_KB
-	int
-	default 256
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xff7f0000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x10000
-
-endif
 
 if NORTHBRIDGE_INTEL_IVYBRIDGE
 
-config VGA_BIOS_ID
-	string
-	default "8086,0166"
-
-config EXTERNAL_MRC_BLOB
+config CACHE_MRC_BIN
 	bool
 	default n
 
@@ -58,10 +27,6 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x20000
 
-endif
-
-if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
-
 config HAVE_MRC
         bool "Add a System Agent binary"
         help
@@ -80,25 +45,9 @@ config DCACHE_RAM_MRC_VAR_SIZE
 	  memory reference code. This should be set to 16KB (0x4000 hex)
 	  so that MRC has enough space to run.
 
-config MRC_FILE
-	string "Intel System Agent path and filename"
-	depends on HAVE_MRC
-	default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
-	default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
-	help
-	  The path and filename of the file to use as System Agent
-	  binary.
-
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select SMM_TSEG
-	select ARCH_BOOTBLOCK_X86_32
-	select ARCH_ROMSTAGE_X86_32
-	select ARCH_RAMSTAGE_X86_32
-	select SSE2
-	select UDELAY_LAPIC
-	select CPU_MICROCODE_IN_CBFS
-	select TSC_SYNC_MFENCE
 	select HAVE_INTEL_ME
 	select X86_RAMTEST
 
@@ -124,20 +73,3 @@ config ENABLE_VMX
 	  slowly.
 
 endif
-
-config CPU_INTEL_SOCKET_RPGA989
-	bool
-
-if CPU_INTEL_SOCKET_RPGA989
-
-config SOCKET_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select MMX
-	select SSE
-	select CACHE_AS_RAM
-
-config CACHE_MRC_BIN
-	bool
-	default n
-
-endif
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 0e6512c675c..343bfb4e98e 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -118,7 +118,6 @@ static void set_spi_speed(void)
 int arch_cpu_init(void)
 {
 	post_code(POST_CPU_INIT);
-	timer_set_base(rdtsc());
 
 	return x86_cpu_init_f();
 }
@@ -299,16 +298,7 @@ int print_cpuinfo(void)
 	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
 
 	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		debug("Resume from S3 detected.\n");
-		boot_mode = PEI_BOOT_RESUME;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
-#else
 		debug("Resume from S3 detected, but disabled.\n");
-#endif
 	} else {
 		/*
 		 * TODO: An indication of life might be possible here (e.g.
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 3efd3e841f4..af5d4a89089 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -240,15 +240,6 @@ static void pch_rtc_init(pci_dev_t dev)
 	}
 	debug("rtc_failed = 0x%x\n", rtc_failed);
 
-#if CONFIG_HAVE_ACPI_RESUME
-	/* Avoid clearing pending interrupts and resetting the RTC control
-	 * register in the resume path because the Linux kernel relies on
-	 * this to know if it should restart the RTC timerqueue if the wake
-	 * was due to the RTC alarm.
-	 */
-	if (acpi_get_slp_type() == 3)
-		return;
-#endif
 	/* TODO: Handle power failure */
 	if (rtc_failed)
 		printf("RTC power failed\n");
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index e95e60e5190..e3d8c139dfd 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -169,20 +169,4 @@ void northbridge_init(pci_dev_t dev)
 
 void northbridge_enable(pci_dev_t dev)
 {
-#if CONFIG_HAVE_ACPI_RESUME
-	switch (x86_pci_read_config32(dev, SKPAD)) {
-	case 0xcafebabe:
-		debug("Normal boot.\n");
-		apci_set_slp_type(0);
-		break;
-	case 0xcafed00d:
-		debug("S3 Resume.\n");
-		apci_set_slp_type(3);
-		break;
-	default:
-		debug("Unknown boot method, assuming normal.\n");
-		apci_set_slp_type(0);
-		break;
-	}
-#endif
 }
diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index fb775d7d283..4f9862194a9 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -6,7 +6,6 @@
 
 config QEMU
 	bool
-	select TSC_CALIBRATION_BYPASS
 
 if QEMU
 
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 84fb082077d..1f93f72dc8d 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -64,9 +64,6 @@ int arch_cpu_init(void)
 	int ret;
 
 	post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-	timer_set_base(rdtsc());
-#endif
 
 	ret = x86_cpu_init_f();
 	if (ret)
diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig
index bc961ef07cf..163caac6608 100644
--- a/arch/x86/cpu/quark/Kconfig
+++ b/arch/x86/cpu/quark/Kconfig
@@ -7,7 +7,6 @@
 config INTEL_QUARK
 	bool
 	select HAVE_RMU
-	select TSC_CALIBRATION_BYPASS
 
 if INTEL_QUARK
 
@@ -119,8 +118,4 @@ config SYS_CAR_SIZE
 	  Space in bytes in eSRAM used as Cache-As-ARM (CAR).
 	  Note this size must not exceed eSRAM's total size.
 
-config TSC_FREQ_IN_MHZ
-	int
-	default 400
-
 endif
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index f737e1921f7..c2bf497d684 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -233,9 +233,6 @@ int arch_cpu_init(void)
 	int ret;
 
 	post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-	timer_set_base(rdtsc());
-#endif
 
 	ret = x86_cpu_init_f();
 	if (ret)
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 933d189f05e..fb81919c212 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -52,9 +52,6 @@ int arch_cpu_init(void)
 	int ret;
 
 	post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
-	timer_set_base(rdtsc());
-#endif
 
 	ret = x86_cpu_init_f();
 	if (ret)