4 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index e88e6e2a98..22c536e0c3 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -92,3 +92,22 @@ void imx_iomux_set_gpr_register(int group, int start_bit,
 	reg |= (value << start_bit);
 	writel(reg, base + group * 4);
 }
+
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+				unsigned int direction)
+{
+        u32 reg;
+	/*
+	 * Only on Vybrid the input/output buffer enable flags
+	 * are part of the shared mux/conf register.
+	 */
+	reg = readl(base + (gpio << 2));
+        if(direction)
+                reg |= 0x2;
+        else
+		reg &= ~0x2;
+
+        writel(reg, (base + (gpio << 2)));
+}
+#endif
diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h
new file mode 100644
index 0000000000..57d50c3b01
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2015
+ * Bhuvanchandra DV, Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_VF610_GPIO_H
+#define __ASM_ARCH_VF610_GPIO_H
+
+#define VYBRID_GPIO_COUNT		32
+#define VF610_GPIO_DIRECTION_IN		0x0
+#define VF610_GPIO_DIRECTION_OUT	0x1
+
+/* GPIO registers */
+struct vybrid_gpio_regs {
+	u32 gpio_pdor;
+	u32 gpio_psor;
+	u32 gpio_pcor;
+	u32 gpio_ptor;
+	u32 gpio_pdir;
+};
+
+struct vybrid_gpio_platdata {
+	unsigned int chip;
+	u32 base;
+};
+#endif	/* __ASM_ARCH_VF610_GPIO_H */
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 512bc1fdb5..5ca3abba58 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -82,6 +82,11 @@
 #define VREG_DIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x0006D000)
 #define SRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006E000)
 #define CMU_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006F000)
+#define GPIO0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF000)
+#define GPIO1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF040)
+#define GPIO2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF080)
+#define GPIO3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF0C0)
+#define GPIO4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF100)
 
 /* AIPS 1 */
 #define OCOTP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00025000)
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 5f161bb5f1..a817b0cc03 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -190,6 +190,8 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 */
 void imx_iomux_set_gpr_register(int group, int start_bit,
 					 int num_bits, int value);
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+				unsigned int direction);
 
 /* macros for declaring and using pinmux array */
 #if defined(CONFIG_MX6QDL)