diff options
Diffstat (limited to 'arch')
261 files changed, 11782 insertions, 6518 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index a6a4742451..ec1b420951 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -23,13 +23,11 @@ CROSS_COMPILE ?= arm-linux- -ifeq ($(BOARD),omap2420h4) -STANDALONE_LOAD_ADDR = 0x80300000 -else +ifndef CONFIG_STANDALONE_LOAD_ADDR ifeq ($(SOC),omap3) -STANDALONE_LOAD_ADDR = 0x80300000 +CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 else -STANDALONE_LOAD_ADDR = 0xc100000 +CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 endif endif @@ -63,7 +61,6 @@ ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS))) PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o endif endif -LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds # needed for relocation ifndef CONFIG_NAND_SPL diff --git a/arch/arm/cpu/arm1136/mx31/devices.c b/arch/arm/cpu/arm1136/mx31/devices.c index 1f4ca7eb44..1e7d48f8fb 100644 --- a/arch/arm/cpu/arm1136/mx31/devices.c +++ b/arch/arm/cpu/arm1136/mx31/devices.c @@ -24,8 +24,8 @@ */ #include <common.h> -#include <asm/arch/mx31-regs.h> -#include <asm/arch/mx31.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> #ifdef CONFIG_SYS_MX31_UART1 void mx31_uart1_hw_init(void) diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 8bd23ee870..18572b9d37 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> #include <asm/io.h> static u32 mx31_decode_pll(u32 reg, u32 infreq) @@ -106,11 +106,64 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } +struct mx3_cpu_type mx31_cpu_type[] = { + { .srev = 0x00, .v = "1.0" }, + { .srev = 0x10, .v = "1.1" }, + { .srev = 0x11, .v = "1.1" }, + { .srev = 0x12, .v = "1.15" }, + { .srev = 0x13, .v = "1.15" }, + { .srev = 0x14, .v = "1.2" }, + { .srev = 0x15, .v = "1.2" }, + { .srev = 0x28, .v = "2.0" }, + { .srev = 0x29, .v = "2.0" }, +}; + +char *get_cpu_rev(void) +{ + u32 i, srev; + + /* read SREV register from IIM module */ + struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR; + srev = readl(&iim->iim_srev); + + for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) + if (srev == mx31_cpu_type[i].srev) + return mx31_cpu_type[i].v; + return "unknown"; +} + +char *get_reset_cause(void) +{ + /* read RCSR register from CCM module */ + struct clock_control_regs *ccm = + (struct clock_control_regs *)CCM_BASE; + + u32 cause = readl(&ccm->rcsr) & 0x07; + + switch (cause) { + case 0x0000: + return "POR"; + break; + case 0x0001: + return "RST"; + break; + case 0x0002: + return "WDOG"; + break; + case 0x0006: + return "JTAG"; + break; + default: + return "unknown reset"; + } +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { - printf("CPU: Freescale i.MX31 at %d MHz\n", - mx31_get_mcu_main_clk() / 1000000); + printf("CPU: Freescale i.MX31 rev %s at %d MHz.", + get_cpu_rev(), mx31_get_mcu_main_clk() / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); return 0; } #endif diff --git a/arch/arm/cpu/arm1136/mx31/timer.c b/arch/arm/cpu/arm1136/mx31/timer.c index f6be3b94a4..c4bc3b3521 100644 --- a/arch/arm/cpu/arm1136/mx31/timer.c +++ b/arch/arm/cpu/arm1136/mx31/timer.c @@ -22,8 +22,10 @@ */ #include <common.h> -#include <asm/arch/mx31-regs.h> +#include <asm/arch/imx-regs.h> #include <div64.h> +#include <watchdog.h> +#include <asm/io.h> #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ @@ -165,5 +167,39 @@ void __udelay (unsigned long usec) void reset_cpu (ulong addr) { - __REG16(WDOG_BASE) = 4; + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; + wdog->wcr = WDOG_ENABLE; + while (1) + ; } + +#ifdef CONFIG_HW_WATCHDOG +void mxc_hw_watchdog_enable(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; + u16 secs; + + /* + * The timer watchdog can be set between + * 0.5 and 128 Seconds. If not defined + * in configuration file, sets 64 Seconds + */ +#ifdef CONFIG_SYS_WD_TIMER_SECS + secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF; + if (!secs) secs = 1; +#else + secs = 64; +#endif + writew(readw(&wdog->wcr) | (secs << WDOG_WT_SHIFT) | WDOG_ENABLE, + &wdog->wcr); +} + + +void mxc_hw_watchdog_reset(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE; + + writew(0x5555, &wdog->wsr); + writew(0xAAAA, &wdog->wsr); +} +#endif diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile index 31da706e59..50eb265665 100644 --- a/arch/arm/cpu/arm920t/a320/Makefile +++ b/arch/arm/cpu/arm920t/a320/Makefile @@ -27,7 +27,6 @@ LIB = $(obj)lib$(SOC).o SOBJS += reset.o COBJS += timer.o -COBJS += ftsmc020.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/arm920t/a320/ftsmc020.c b/arch/arm/cpu/arm920t/a320/ftsmc020.c deleted file mode 100644 index 76465373ec..0000000000 --- a/arch/arm/cpu/arm920t/a320/ftsmc020.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> -#include <asm/arch/ftsmc020.h> - -struct ftsmc020_config { - unsigned int config; - unsigned int timing; -}; - -static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; - -static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; - -static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg) -{ - if (bank > 3) { - printf("bank # %u invalid\n", bank); - return; - } - - writel(cfg->config, &smc->bank[bank].cr); - writel(cfg->timing, &smc->bank[bank].tpr); -} - -void ftsmc020_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(config); i++) - ftsmc020_setup_bank(i, &config[i]); -} diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c index d2e316fd54..95cb8fd19f 100644 --- a/arch/arm/cpu/arm920t/a320/timer.c +++ b/arch/arm/cpu/arm920t/a320/timer.c @@ -19,21 +19,19 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/ftpmu010.h> -#include <asm/arch/fttmr010.h> +#include <faraday/ftpmu010.h> +#include <faraday/fttmr010.h> static ulong timestamp; static ulong lastdec; static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; -static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; #define TIMER_CLOCK 32768 #define TIMER_LOAD_VAL 0xffffffff int timer_init(void) { - unsigned int oscc; unsigned int cr; debug("%s()\n", __func__); @@ -41,23 +39,8 @@ int timer_init(void) /* disable timers */ writel(0, &tmr->cr); - /* - * use 32768Hz oscillator for RTC, WDT, TIMER - */ - - /* enable the 32768Hz oscillator */ - oscc = readl(&pmu->OSCC); - oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); - writel(oscc, &pmu->OSCC); - - /* wait until ready */ - while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) - ; - - /* select 32768Hz oscillator */ - oscc = readl(&pmu->OSCC); - oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; - writel(oscc, &pmu->OSCC); + /* use 32768Hz oscillator for RTC, WDT, TIMER */ + ftpmu010_32768osc_enable(); /* setup timer */ writel(TIMER_LOAD_VAL, &tmr->timer3_load); diff --git a/arch/arm/cpu/arm920t/at91rm9200/ether.c b/arch/arm/cpu/arm920t/at91rm9200/ether.c index e1cdebab9d..d7135c57d5 100644 --- a/arch/arm/cpu/arm920t/at91rm9200/ether.c +++ b/arch/arm/cpu/arm920t/at91rm9200/ether.c @@ -39,7 +39,7 @@ typedef struct { #define RBF_MULTICAST (1<<30) #define RBF_UNICAST (1<<29) #define RBF_EXTERNAL (1<<28) -#define RBF_UNKOWN (1<<27) +#define RBF_UNKNOWN (1<<27) #define RBF_SIZE 0x07ff #define RBF_LOCAL4 (1<<26) #define RBF_LOCAL3 (1<<25) diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c index 62aa1753ce..c21938e31f 100644 --- a/arch/arm/cpu/arm926ejs/armada100/cpu.c +++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c @@ -62,6 +62,16 @@ int arch_cpu_init(void) /* Enable GPIO clock */ writel(APBC_APBCLK, &apb1clkres->gpio); +#ifdef CONFIG_I2C_MV + /* Enable general I2C clock */ + writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0); + writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0); + + /* Enable power I2C clock */ + writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1); + writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1); +#endif + /* * Enable Functional and APB clock at 14.7456MHz * for configured UART console @@ -90,3 +100,9 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_I2C_MV +void i2c_clk_enable(void) +{ +} +#endif diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index c6e114634a..76e4b5c397 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -145,7 +145,7 @@ int cpu_mmc_init (bd_t * bis) } #ifdef CONFIG_MXC_UART -void mx25_uart_init_pins (void) +void mx25_uart1_init_pins(void) { struct iomuxc_mux_ctl *muxctl; struct iomuxc_pad_ctl *padctl; diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile index e5a9994e6b..a4298b4b9c 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/Makefile +++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> +# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> # # Based on original Kirkwood support which is # (C) Copyright 2009 diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 1894b52fbf..05bd45c3f6 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * Based on original Kirkwood support which is * (C) Copyright 2009 diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c index b749282099..3e1ff7d8ea 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * Based on original Kirkwood support which is * (C) Copyright 2009 @@ -38,7 +38,7 @@ u32 orion5x_sdram_bar(enum memory_bank bank) { struct orion5x_ddr_addr_decode_registers *winregs = (struct orion5x_ddr_addr_decode_registers *) - ORION5X_CPU_WIN_BASE; + ORION5X_DRAM_BASE; u32 result = 0; u32 enable = 0x01 & winregs[bank].size; diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S index 0523bd468a..a2de3cf710 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c index bbab2269dd..9d45260612 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/timer.c +++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * Based on original Kirkwood support which is * Copyright (C) Marvell International Ltd. and its affiliates diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index 9ddc77c071..8b2eafa40b 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -59,6 +59,12 @@ int arch_cpu_init(void) /* Enable GPIO clock */ writel(APBC_APBCLK, &apbclkres->gpio); +#ifdef CONFIG_I2C_MV + /* Enable I2C clock */ + writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); + writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); +#endif + icache_enable(); return 0; @@ -76,3 +82,9 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_I2C_MV +void i2c_clk_enable(void) +{ +} +#endif diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index fefcfa2f88..09409370c9 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -10,7 +10,7 @@ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> * Copyright (c) 2003 Kshitij <kshitij@ti.com> - * Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr> + * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 00914f42e9..0054b22e4a 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -10,7 +10,7 @@ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> * Copyright (c) 2003 Kshitij <kshitij@ti.com> - * Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr> + * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 09500b3b9f..6f4e8db74d 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -77,6 +77,33 @@ u32 get_cpu_rev(void) return system_rev; } +static char *get_reset_cause(void) +{ + u32 cause; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + cause = readl(&src_regs->srsr); + writel(cause, &src_regs->srsr); + + switch (cause) { + case 0x00001: + return "POR"; + case 0x00004: + return "CSU"; + case 0x00008: + return "IPP USER"; + case 0x00010: + return "WDOG"; + case 0x00020: + return "JTAG HIGH-Z"; + case 0x00040: + return "JTAG SW"; + case 0x10000: + return "WARM BOOT"; + default: + return "unknown reset"; + } +} #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) @@ -89,6 +116,7 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); return 0; } #endif diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 2238c52e3b..3d38d08ccb 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -278,6 +278,25 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index) wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); } +static void dpll5_init_34xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_per2_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr = ptr + clk_index; + + /* PER2 DPLL (DPLL5) */ + sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP); + wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); + sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */ + sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */ + sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/ + sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */ + sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); +} + static void mpu_init_34xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; @@ -587,6 +606,7 @@ void prcm_init(void) dpll3_init_34xx(sil_index, clk_index); dpll4_init_34xx(sil_index, clk_index); + dpll5_init_34xx(sil_index, clk_index); iva_init_34xx(sil_index, clk_index); mpu_init_34xx(sil_index, clk_index); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 109481e1c6..14580729bb 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -360,6 +360,28 @@ get_per_dpll_param: adr r0, per_dpll_param mov pc, lr +/* PER2 DPLL values */ +per2_dpll_param: +/* 12MHz */ +.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12 + +/* 13MHz */ +.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13 + +/* 19.2MHz */ +.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2 + +/* 26MHz */ +.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26 + +/* 38.4MHz */ +.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4 + +.globl get_per2_dpll_param +get_per2_dpll_param: + adr r0, per2_dpll_param + mov pc, lr + /* * Tables for 36XX/37XX devices * diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index bd914b0ee5..a01c303e71 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -31,16 +31,6 @@ #include <asm/arch/sys_proto.h> #include <command.h> -/* - * Only One NAND allowed on board at a time. - * The GPMC CS Base for the same - */ -unsigned int boot_flash_base; -unsigned int boot_flash_off; -unsigned int boot_flash_sec; -unsigned int boot_flash_type; -volatile unsigned int boot_flash_env_addr; - struct gpmc *gpmc_cfg; #if defined(CONFIG_CMD_NAND) @@ -134,10 +124,6 @@ void gpmc_init(void) const u32 *gpmc_config = NULL; u32 base = 0; u32 size = 0; -#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND) - u32 f_off = CONFIG_SYS_MONITOR_LEN; - u32 f_sec = 0; -#endif #endif u32 config = 0; @@ -162,15 +148,6 @@ void gpmc_init(void) base = PISMO1_NAND_BASE; size = PISMO1_NAND_SIZE; enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#if defined(CONFIG_ENV_IS_IN_NAND) - f_off = SMNAND_ENV_OFFSET; - f_sec = (128 << 10); /* 128 KiB */ - /* env setup */ - boot_flash_base = base; - boot_flash_off = f_off; - boot_flash_sec = f_sec; - boot_flash_env_addr = f_off; -#endif #endif #if defined(CONFIG_CMD_ONENAND) @@ -178,14 +155,5 @@ void gpmc_init(void) base = PISMO1_ONEN_BASE; size = PISMO1_ONEN_SIZE; enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#if defined(CONFIG_ENV_IS_IN_ONENAND) - f_off = ONENAND_ENV_OFFSET; - f_sec = (128 << 10); /* 128 KiB */ - /* env setup */ - boot_flash_base = base; - boot_flash_off = f_off; - boot_flash_sec = f_sec; - boot_flash_env_addr = f_off; -#endif #endif } diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index d83d501837..2929fc7e32 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -70,6 +70,18 @@ _end_vect: _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_TEGRA2 +/* + * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). + * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, + * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU + * to pick up its reset vector, which points here. + */ +.globl _armboot_start +_armboot_start: + .word _start +#endif + /* * These are defined in the board-specific linker script. */ @@ -115,7 +127,7 @@ reset: orr r0, r0, #0xd3 msr cpsr,r0 -#if (CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP34XX) /* Copy vectors to mask ROM indirect addr */ adr r0, _start @ r0 <- current position of code add r0, r0, #4 @ skip reset vector diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index 687c8871c5..f1ea915851 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := board.o sys_info.o timer.o +COBJS := ap20.o board.o sys_info.o timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c new file mode 100644 index 0000000000..60dd5dfc08 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -0,0 +1,358 @@ +/* +* (C) Copyright 2010-2011 +* NVIDIA Corporation <www.nvidia.com> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include "ap20.h" +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/pmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/scu.h> +#include <common.h> + +u32 s_first_boot = 1; + +void init_pllx(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + /* If PLLX is already enabled, just return */ + reg = readl(&clkrst->crc_pllx_base); + if (reg & PLL_ENABLE) + return; + + /* Set PLLX_MISC */ + reg = CPCON; /* CPCON[11:8] = 0001 */ + writel(reg, &clkrst->crc_pllx_misc); + + /* Use 12MHz clock here */ + reg = (PLL_BYPASS | PLL_DIVM); + reg |= (1000 << 8); /* DIVN = 0x3E8 */ + writel(reg, &clkrst->crc_pllx_base); + + reg |= PLL_ENABLE; + writel(reg, &clkrst->crc_pllx_base); + + reg &= ~PLL_BYPASS; + writel(reg, &clkrst->crc_pllx_base); +} + +static void enable_cpu_clock(int enable) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg, clk; + + /* + * NOTE: + * Regardless of whether the request is to enable or disable the CPU + * clock, every processor in the CPU complex except the master (CPU 0) + * will have it's clock stopped because the AVP only talks to the + * master. The AVP does not know (nor does it need to know) that there + * are multiple processors in the CPU complex. + */ + + if (enable) { + /* Initialize PLLX */ + init_pllx(); + + /* Wait until all clocks are stable */ + udelay(PLL_STABILIZATION_DELAY); + + writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); + writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); + } + + /* Fetch the register containing the main CPU complex clock enable */ + reg = readl(&clkrst->crc_clk_out_enb_l); + reg |= CLK_ENB_CPU; + + /* + * Read the register containing the individual CPU clock enables and + * always stop the clock to CPU 1. + */ + clk = readl(&clkrst->crc_clk_cpu_cmplx); + clk |= CPU1_CLK_STP; + + if (enable) { + /* Unstop the CPU clock */ + clk &= ~CPU0_CLK_STP; + } else { + /* Stop the CPU clock */ + clk |= CPU0_CLK_STP; + } + + writel(clk, &clkrst->crc_clk_cpu_cmplx); + writel(reg, &clkrst->crc_clk_out_enb_l); +} + +static int is_cpu_powered(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + + return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0; +} + +static void remove_cpu_io_clamps(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + + /* Remove the clamps on the CPU I/O signals */ + reg = readl(&pmc->pmc_remove_clamping); + reg |= CPU_CLMP; + writel(reg, &pmc->pmc_remove_clamping); + + /* Give I/O signals time to stabilize */ + udelay(IO_STABILIZATION_DELAY); +} + +static void powerup_cpu(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + int timeout = IO_STABILIZATION_DELAY; + + if (!is_cpu_powered()) { + /* Toggle the CPU power state (OFF -> ON) */ + reg = readl(&pmc->pmc_pwrgate_toggle); + reg &= PARTID_CP; + reg |= START_CP; + writel(reg, &pmc->pmc_pwrgate_toggle); + + /* Wait for the power to come up */ + while (!is_cpu_powered()) { + if (timeout-- == 0) + printf("CPU failed to power up!\n"); + else + udelay(10); + } + + /* + * Remove the I/O clamps from CPU power partition. + * Recommended only on a Warm boot, if the CPU partition gets + * power gated. Shouldn't cause any harm when called after a + * cold boot according to HW, probably just redundant. + */ + remove_cpu_io_clamps(); + } +} + +static void enable_cpu_power_rail(void) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + u32 reg; + + reg = readl(&pmc->pmc_cntrl); + reg |= CPUPWRREQ_OE; + writel(reg, &pmc->pmc_cntrl); + + /* + * The TI PMU65861C needs a 3.75ms delay between enabling + * the power rail and enabling the CPU clock. This delay + * between SM1EN and SM1 is for switching time + the ramp + * up of the voltage to the CPU (VDD_CPU from PMU). + */ + udelay(3750); +} + +static void reset_A9_cpu(int reset) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg, cpu; + + /* + * NOTE: Regardless of whether the request is to hold the CPU in reset + * or take it out of reset, every processor in the CPU complex + * except the master (CPU 0) will be held in reset because the + * AVP only talks to the master. The AVP does not know that there + * are multiple processors in the CPU complex. + */ + + /* Hold CPU 1 in reset */ + cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1; + writel(cpu, &clkrst->crc_cpu_cmplx_set); + + reg = readl(&clkrst->crc_rst_dev_l); + if (reset) { + /* Now place CPU0 into reset */ + cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0; + writel(cpu, &clkrst->crc_cpu_cmplx_set); + + /* Enable master CPU reset */ + reg |= SWR_CPU_RST; + } else { + /* Take CPU0 out of reset */ + cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0; + writel(cpu, &clkrst->crc_cpu_cmplx_clr); + + /* Disable master CPU reset */ + reg &= ~SWR_CPU_RST; + } + + writel(reg, &clkrst->crc_rst_dev_l); +} + +static void clock_enable_coresight(int enable) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 rst, clk, src; + + rst = readl(&clkrst->crc_rst_dev_u); + clk = readl(&clkrst->crc_clk_out_enb_u); + + if (enable) { + rst &= ~SWR_CSITE_RST; + clk |= CLK_ENB_CSITE; + } else { + rst |= SWR_CSITE_RST; + clk &= ~CLK_ENB_CSITE; + } + + writel(clk, &clkrst->crc_clk_out_enb_u); + writel(rst, &clkrst->crc_rst_dev_u); + + if (enable) { + /* + * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by + * 1.5, giving an effective frequency of 144MHz. + * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor + * (bits 7:0), so 00000001b == 1.5 (n+1 + .5) + */ + src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); + writel(src, &clkrst->crc_clk_src_csite); + + /* Unlock the CPU CoreSight interfaces */ + rst = 0xC5ACCE55; + writel(rst, CSITE_CPU_DBG0_LAR); + writel(rst, CSITE_CPU_DBG1_LAR); + } +} + +void start_cpu(u32 reset_vector) +{ + /* Enable VDD_CPU */ + enable_cpu_power_rail(); + + /* Hold the CPUs in reset */ + reset_A9_cpu(1); + + /* Disable the CPU clock */ + enable_cpu_clock(0); + + /* Enable CoreSight */ + clock_enable_coresight(1); + + /* + * Set the entry point for CPU execution from reset, + * if it's a non-zero value. + */ + if (reset_vector) + writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR); + + /* Enable the CPU clock */ + enable_cpu_clock(1); + + /* If the CPU doesn't already have power, power it up */ + powerup_cpu(); + + /* Take the CPU out of reset */ + reset_A9_cpu(0); +} + + +void halt_avp(void) +{ + for (;;) { + writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \ + | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)), + FLOW_CTLR_HALT_COP_EVENTS); + } +} + +void enable_scu(void) +{ + struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; + u32 reg; + + /* If SCU already setup/enabled, return */ + if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) + return; + + /* Invalidate all ways for all processors */ + writel(0xFFFF, &scu->scu_inv_all); + + /* Enable SCU - bit 0 */ + reg = readl(&scu->scu_ctrl); + reg |= SCU_CTRL_ENABLE; + writel(reg, &scu->scu_ctrl); +} + +void init_pmc_scratch(void) +{ + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; + int i; + + /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ + for (i = 0; i < 23; i++) + writel(0, &pmc->pmc_scratch1+i); + + /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ + writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); +} + +void cpu_start(void) +{ + struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + + /* enable JTAG */ + writel(0xC0, &pmt->pmt_cfg_ctl); + + if (s_first_boot) { + /* + * Need to set this before cold-booting, + * otherwise we'll end up in an infinite loop. + */ + s_first_boot = 0; + cold_boot(); + } +} + +void tegra2_start() +{ + if (s_first_boot) { + /* Init Debug UART Port (115200 8n1) */ + uart_init(); + + /* Init PMC scratch memory */ + init_pmc_scratch(); + } + +#ifdef CONFIG_ENABLE_CORTEXA9 + /* take the mpcore out of reset */ + cpu_start(); + + /* configure cache */ + cache_configure(); +#endif +} diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/cpu/armv7/tegra2/ap20.h new file mode 100644 index 0000000000..49fe340a28 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/ap20.h @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2010-2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <asm/types.h> + +/* Stabilization delays, in usec */ +#define PLL_STABILIZATION_DELAY (300) +#define IO_STABILIZATION_DELAY (1000) + +#define NVBL_PLLP_KHZ (216000) + +#define PLLX_ENABLED (1 << 30) +#define CCLK_BURST_POLICY 0x20008888 +#define SUPER_CCLK_DIVIDER 0x80000000 + +/* Calculate clock fractional divider value from ref and target frequencies */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) + +/* Calculate clock frequency value from reference and clock divider value */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) + +/* AVP/CPU ID */ +#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ +#define PG_UP_TAG_0 0x0 + +#define CORESIGHT_UNLOCK 0xC5ACCE55; + +/* AP20-Specific Base Addresses */ + +/* AP20 Base physical address of SDRAM. */ +#define AP20_BASE_PA_SDRAM 0x00000000 +/* AP20 Base physical address of internal SRAM. */ +#define AP20_BASE_PA_SRAM 0x40000000 +/* AP20 Size of internal SRAM (256KB). */ +#define AP20_BASE_PA_SRAM_SIZE 0x00040000 +/* AP20 Base physical address of flash. */ +#define AP20_BASE_PA_NOR_FLASH 0xD0000000 +/* AP20 Base physical address of boot information table. */ +#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM + +/* + * Super-temporary stacks for EXTREMELY early startup. The values chosen for + * these addresses must be valid on ALL SOCs because this value is used before + * we are able to differentiate between the SOC types. + * + * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its + * stack is placed below the AVP stack. Once the CPU stack has been moved, + * the AVP is free to use the IRAM the CPU stack previously occupied if + * it should need to do so. + * + * NOTE: In multi-processor CPU complex configurations, each processor will have + * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a + * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a + * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous + * CPU. + */ + +/* Common AVP early boot stack limit */ +#define AVP_EARLY_BOOT_STACK_LIMIT \ + (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2)) +/* Common AVP early boot stack size */ +#define AVP_EARLY_BOOT_STACK_SIZE 0x1000 +/* Common CPU early boot stack limit */ +#define CPU_EARLY_BOOT_STACK_LIMIT \ + (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE) +/* Common CPU early boot stack size */ +#define CPU_EARLY_BOOT_STACK_SIZE 0x1000 + +#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) +#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) +#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) + +#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) +#define FLOW_MODE_STOP 2 +#define HALT_COP_EVENT_JTAG (1 << 28) +#define HALT_COP_EVENT_IRQ_1 (1 << 11) +#define HALT_COP_EVENT_FIQ_1 (1 << 9) + +/* Prototypes */ + +void tegra2_start(void); +void uart_init(void); +void udelay(unsigned long); +void cold_boot(void); +void cache_configure(void); diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S index 7f15746861..f24a2ff57d 100644 --- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S +++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S @@ -26,6 +26,7 @@ #include <config.h> #include <version.h> + _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file @@ -58,8 +59,101 @@ lowlevel_init: mov pc, lr @ back to arch calling code + +.globl startup_cpu +startup_cpu: + @ Initialize the AVP, clocks, and memory controller + @ SDRAM is guaranteed to be on at this point + + ldr r0, =cold_boot @ R0 = reset vector for CPU + bl start_cpu @ start the CPU + + @ Transfer control to the AVP code + bl halt_avp + + @ Should never get here +_loop_forever2: + b _loop_forever2 + +.globl cache_configure +cache_configure: + stmdb r13!,{r14} + @ invalidate instruction cache + mov r1, #0 + mcr p15, 0, r1, c7, c5, 0 + + @ invalidate the i&d tlb entries + mcr p15, 0, r1, c8, c5, 0 + mcr p15, 0, r1, c8, c6, 0 + + @ enable instruction cache + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, #(1<<12) + mcr p15, 0, r1, c1, c0, 0 + + bl enable_scu + + @ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x41 + mcr p15, 0, r0, c1, c0, 1 + + @ Now flush the Dcache + mov r0, #0 + @ 256 cache lines + mov r1, #256 + +invalidate_loop: + add r1, r1, #-1 + mov r0, r1, lsl #5 + @ invalidate d-cache using line (way0) + mcr p15, 0, r0, c7, c6, 2 + + orr r2, r0, #(1<<30) + @ invalidate d-cache using line (way1) + mcr p15, 0, r2, c7, c6, 2 + + orr r2, r0, #(2<<30) + @ invalidate d-cache using line (way2) + mcr p15, 0, r2, c7, c6, 2 + + orr r2, r0, #(3<<30) + @ invalidate d-cache using line (way3) + mcr p15, 0, r2, c7, c6, 2 + cmp r1, #0 + bne invalidate_loop + + @ FIXME: should have ap20's L2 disabled too? +invalidate_done: + ldmia r13!,{pc} + +.globl cold_boot +cold_boot: + msr cpsr_c, #0xD3 + @ Check current processor: CPU or AVP? + @ If CPU, go to CPU boot code, else continue on AVP path + + ldr r0, =NV_PA_PG_UP_BASE + ldr r1, [r0] + ldr r2, =PG_UP_TAG_AVP + + @ are we the CPU? + ldr sp, CPU_STACK + cmp r1, r2 + @ yep, we are the CPU + bne _armboot_start + + @ AVP initialization follows this path + ldr sp, AVP_STACK + @ Init AVP and start CPU + b startup_cpu + @ the literal pools origin .ltorg SRAM_STACK: .word LOW_LEVEL_SRAM_STACK +AVP_STACK: + .word EARLY_AVP_STACK +CPU_STACK: + .word EARLY_CPU_STACK diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile index 49a6ed3c74..e8b59a30c9 100644 --- a/arch/arm/cpu/pxa/Makefile +++ b/arch/arm/cpu/pxa/Makefile @@ -28,7 +28,6 @@ LIB = $(obj)lib$(CPU).o START = start.o COBJS += cpu.o -COBJS += i2c.o COBJS += pxafb.o COBJS += timer.o COBJS += usb.o diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c index 7d49cbb4fd..9970a4b45b 100644 --- a/arch/arm/cpu/pxa/cpu.c +++ b/arch/arm/cpu/pxa/cpu.c @@ -318,3 +318,13 @@ int arch_cpu_init(void) pxa_clock_setup(); return 0; } + +void i2c_clk_enable(void) +{ + /* set the global I2C clock on */ +#ifdef CONFIG_CPU_MONAHANS + writel(readl(CKENB) | (CKENB_4_I2C), CKENB); +#else + writel(readl(CKEN) | CKEN14_I2C, CKEN); +#endif +} diff --git a/arch/arm/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c deleted file mode 100644 index 7aa49ae4a0..0000000000 --- a/arch/arm/cpu/pxa/i2c.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2003 Pengutronix e.K. - * Robert Schwebel <r.schwebel@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Back ported to the 8xx platform (from the 8260 platform) by - * Murray.Jensen@cmst.csiro.au, 27-Jan-01. - */ - -/* FIXME: this file is PXA255 specific! What about other XScales? */ - -#include <common.h> -#include <asm/io.h> - -#ifdef CONFIG_HARD_I2C - -/* - * - CONFIG_SYS_I2C_SPEED - * - I2C_PXA_SLAVE_ADDR - */ - -#include <asm/arch/hardware.h> -#include <asm/arch/pxa-regs.h> -#include <i2c.h> - -/*#define DEBUG_I2C 1 /###* activate local debugging output */ -#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ - -#if (CONFIG_SYS_I2C_SPEED == 400000) -#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) -#else -#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) -#endif - -#define I2C_ISR_INIT 0x7FF - -#ifdef DEBUG_I2C -#define PRINTD(x) printf x -#else -#define PRINTD(x) -#endif - - -/* Shall the current transfer have a start/stop condition? */ -#define I2C_COND_NORMAL 0 -#define I2C_COND_START 1 -#define I2C_COND_STOP 2 - -/* Shall the current transfer be ack/nacked or being waited for it? */ -#define I2C_ACKNAK_WAITACK 1 -#define I2C_ACKNAK_SENDACK 2 -#define I2C_ACKNAK_SENDNAK 4 - -/* Specify who shall transfer the data (master or slave) */ -#define I2C_READ 0 -#define I2C_WRITE 1 - -/* All transfers are described by this data structure */ -struct i2c_msg { - u8 condition; - u8 acknack; - u8 direction; - u8 data; -}; - - -/** - * i2c_pxa_reset: - reset the host controller - * - */ - -static void i2c_reset( void ) -{ - writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ - writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */ - udelay(100); - writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ -#ifdef CONFIG_CPU_MONAHANS - /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ - writel(readl(CKENB) | (CKENB_4_I2C), CKENB); -#else /* CONFIG_CPU_MONAHANS */ - /* set the global I2C clock on */ - writel(readl(CKEN) | CKEN14_I2C, CKEN); -#endif - writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */ - writel(I2C_ICR_INIT, ICR); /* set control reg values */ - writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */ - writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */ - udelay(100); -} - - -/** - * i2c_isr_set_cleared: - wait until certain bits of the I2C status register - * are set and cleared - * - * @return: 1 in case of success, 0 means timeout (no match within 10 ms). - */ -static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) -{ - int timeout = 10000; - - while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){ - udelay( 10 ); - if( timeout-- < 0 ) return 0; - } - - return 1; -} - - -/** - * i2c_transfer: - Transfer one byte over the i2c bus - * - * This function can tranfer a byte over the i2c bus in both directions. - * It is used by the public API functions. - * - * @return: 0: transfer successful - * -1: message is empty - * -2: transmit timeout - * -3: ACK missing - * -4: receive timeout - * -5: illegal parameters - * -6: bus is busy and couldn't be aquired - */ -int i2c_transfer(struct i2c_msg *msg) -{ - int ret; - - if (!msg) - goto transfer_error_msg_empty; - - switch(msg->direction) { - - case I2C_WRITE: - - /* check if bus is not busy */ - if (!i2c_isr_set_cleared(0,ISR_IBB)) - goto transfer_error_bus_busy; - - /* start transmission */ - writel(readl(ICR) & ~ICR_START, ICR); - writel(readl(ICR) & ~ICR_STOP, ICR); - writel(msg->data, IDBR); - if (msg->condition == I2C_COND_START) - writel(readl(ICR) | ICR_START, ICR); - if (msg->condition == I2C_COND_STOP) - writel(readl(ICR) | ICR_STOP, ICR); - if (msg->acknack == I2C_ACKNAK_SENDNAK) - writel(readl(ICR) | ICR_ACKNAK, ICR); - if (msg->acknack == I2C_ACKNAK_SENDACK) - writel(readl(ICR) & ~ICR_ACKNAK, ICR); - writel(readl(ICR) & ~ICR_ALDIE, ICR); - writel(readl(ICR) | ICR_TB, ICR); - - /* transmit register empty? */ - if (!i2c_isr_set_cleared(ISR_ITE,0)) - goto transfer_error_transmit_timeout; - - /* clear 'transmit empty' state */ - writel(readl(ISR) | ISR_ITE, ISR); - - /* wait for ACK from slave */ - if (msg->acknack == I2C_ACKNAK_WAITACK) - if (!i2c_isr_set_cleared(0,ISR_ACKNAK)) - goto transfer_error_ack_missing; - break; - - case I2C_READ: - - /* check if bus is not busy */ - if (!i2c_isr_set_cleared(0,ISR_IBB)) - goto transfer_error_bus_busy; - - /* start receive */ - writel(readl(ICR) & ~ICR_START, ICR); - writel(readl(ICR) & ~ICR_STOP, ICR); - if (msg->condition == I2C_COND_START) - writel(readl(ICR) | ICR_START, ICR); - if (msg->condition == I2C_COND_STOP) - writel(readl(ICR) | ICR_STOP, ICR); - if (msg->acknack == I2C_ACKNAK_SENDNAK) - writel(readl(ICR) | ICR_ACKNAK, ICR); - if (msg->acknack == I2C_ACKNAK_SENDACK) - writel(readl(ICR) & ~ICR_ACKNAK, ICR); - writel(readl(ICR) & ~ICR_ALDIE, ICR); - writel(readl(ICR) | ICR_TB, ICR); - - /* receive register full? */ - if (!i2c_isr_set_cleared(ISR_IRF,0)) - goto transfer_error_receive_timeout; - - msg->data = readl(IDBR); - - /* clear 'receive empty' state */ - writel(readl(ISR) | ISR_IRF, ISR); - - break; - - default: - - goto transfer_error_illegal_param; - - } - - return 0; - -transfer_error_msg_empty: - PRINTD(("i2c_transfer: error: 'msg' is empty\n")); - ret = -1; goto i2c_transfer_finish; - -transfer_error_transmit_timeout: - PRINTD(("i2c_transfer: error: transmit timeout\n")); - ret = -2; goto i2c_transfer_finish; - -transfer_error_ack_missing: - PRINTD(("i2c_transfer: error: ACK missing\n")); - ret = -3; goto i2c_transfer_finish; - -transfer_error_receive_timeout: - PRINTD(("i2c_transfer: error: receive timeout\n")); - ret = -4; goto i2c_transfer_finish; - -transfer_error_illegal_param: - PRINTD(("i2c_transfer: error: illegal parameters\n")); - ret = -5; goto i2c_transfer_finish; - -transfer_error_bus_busy: - PRINTD(("i2c_transfer: error: bus is busy\n")); - ret = -6; goto i2c_transfer_finish; - -i2c_transfer_finish: - PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR)); - i2c_reset(); - return ret; - -} - -/* ------------------------------------------------------------------------ */ -/* API Functions */ -/* ------------------------------------------------------------------------ */ - -void i2c_init(int speed, int slaveaddr) -{ -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#endif -} - - -/** - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ - -int i2c_probe(uchar chip) -{ - struct i2c_msg msg; - - i2c_reset(); - - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1) + 1; - if (i2c_transfer(&msg)) return -1; - - msg.condition = I2C_COND_STOP; - msg.acknack = I2C_ACKNAK_SENDNAK; - msg.direction = I2C_READ; - msg.data = 0x00; - if (i2c_transfer(&msg)) return -1; - - return 0; -} - - -/** - * i2c_read: - Read multiple bytes from an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be read - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to write the data - * @len: how much byte do we want to read - * @return: 0 in case of success - */ - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - int ret; - - PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); - - i2c_reset(); - - /* dummy chip address write */ - PRINTD(("i2c_read: dummy chip address write\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data &= 0xFE; - if ((ret=i2c_transfer(&msg))) return -1; - - /* - * send memory address bytes; - * alen defines how much bytes we have to send. - */ - /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */ - addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); - - while (--alen >= 0) { - - PRINTD(("i2c_read: send memory word address byte %1d\n",alen)); - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = addr_bytes[alen]; - if ((ret=i2c_transfer(&msg))) return -1; - } - - - /* start read sequence */ - PRINTD(("i2c_read: start read sequence\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data |= 0x01; - if ((ret=i2c_transfer(&msg))) return -1; - - /* read bytes; send NACK at last byte */ - while (len--) { - - if (len==0) { - msg.condition = I2C_COND_STOP; - msg.acknack = I2C_ACKNAK_SENDNAK; - } else { - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_SENDACK; - } - - msg.direction = I2C_READ; - msg.data = 0x00; - if ((ret=i2c_transfer(&msg))) return -1; - - *buffer = msg.data; - PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); - buffer++; - - } - - i2c_reset(); - - return 0; -} - - -/** - * i2c_write: - Write multiple bytes to an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be written - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to find the data to be written - * @len: how much byte do we want to read - * @return: 0 in case of success - */ - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - - PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); - - i2c_reset(); - - /* chip address write */ - PRINTD(("i2c_write: chip address write\n")); - msg.condition = I2C_COND_START; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = (chip << 1); - msg.data &= 0xFE; - if (i2c_transfer(&msg)) return -1; - - /* - * send memory address bytes; - * alen defines how much bytes we have to send. - */ - addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); - - while (--alen >= 0) { - - PRINTD(("i2c_write: send memory word address\n")); - msg.condition = I2C_COND_NORMAL; - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = addr_bytes[alen]; - if (i2c_transfer(&msg)) return -1; - } - - /* write bytes; send NACK at last byte */ - while (len--) { - - PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); - - if (len==0) - msg.condition = I2C_COND_STOP; - else - msg.condition = I2C_COND_NORMAL; - - msg.acknack = I2C_ACKNAK_WAITACK; - msg.direction = I2C_WRITE; - msg.data = *(buffer++); - - if (i2c_transfer(&msg)) return -1; - - } - - i2c_reset(); - - return 0; - -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/arch/arm/include/asm/arch-a320/ftsdmc020.h b/arch/arm/include/asm/arch-a320/ftsdmc020.h deleted file mode 100644 index 069977200b..0000000000 --- a/arch/arm/include/asm/arch-a320/ftsdmc020.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * SDRAM Controller - */ -#ifndef __FTSDMC020_H -#define __FTSDMC020_H - -#define FTSDMC020_OFFSET_TP0 0x00 -#define FTSDMC020_OFFSET_TP1 0x04 -#define FTSDMC020_OFFSET_CR 0x08 -#define FTSDMC020_OFFSET_BANK0_BSR 0x0C -#define FTSDMC020_OFFSET_BANK1_BSR 0x10 -#define FTSDMC020_OFFSET_BANK2_BSR 0x14 -#define FTSDMC020_OFFSET_BANK3_BSR 0x18 -#define FTSDMC020_OFFSET_BANK4_BSR 0x1C -#define FTSDMC020_OFFSET_BANK5_BSR 0x20 -#define FTSDMC020_OFFSET_BANK6_BSR 0x24 -#define FTSDMC020_OFFSET_BANK7_BSR 0x28 -#define FTSDMC020_OFFSET_ACR 0x34 - -/* - * Timing Parametet 0 Register - */ -#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) -#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) -#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) -#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) -#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parametet 1 Register - */ -#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) -#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * Configuration Register - */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC020_BANK_ENABLE (1 << 28) - -#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) - -#define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) -#define FTSDMC020_BANK_DDW_X16 (2 << 12) -#define FTSDMC020_BANK_DDW_X32 (3 << 12) - -#define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) -#define FTSDMC020_BANK_DSZ_128M (2 << 8) -#define FTSDMC020_BANK_DSZ_256M (3 << 8) - -#define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) -#define FTSDMC020_BANK_MBW_32 (2 << 4) - -#define FTSDMC020_BANK_SIZE_1M 0x0 -#define FTSDMC020_BANK_SIZE_2M 0x1 -#define FTSDMC020_BANK_SIZE_4M 0x2 -#define FTSDMC020_BANK_SIZE_8M 0x3 -#define FTSDMC020_BANK_SIZE_16M 0x4 -#define FTSDMC020_BANK_SIZE_32M 0x5 -#define FTSDMC020_BANK_SIZE_64M 0x6 -#define FTSDMC020_BANK_SIZE_128M 0x7 -#define FTSDMC020_BANK_SIZE_256M 0x8 - -/* - * Arbiter Control Register - */ -#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) - -#endif /* __FTSDMC020_H */ diff --git a/arch/arm/include/asm/arch-a320/ftsmc020.h b/arch/arm/include/asm/arch-a320/ftsmc020.h deleted file mode 100644 index 95d9500339..0000000000 --- a/arch/arm/include/asm/arch-a320/ftsmc020.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Static Memory Controller - */ -#ifndef __FTSMC020_H -#define __FTSMC020_H - -#ifndef __ASSEMBLY__ - -struct ftsmc020 { - struct { - unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ - unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ - } bank[4]; - unsigned int pad[8]; /* 0x20 - 0x3c */ - unsigned int ssr; /* 0x40 */ -}; - -void ftsmc020_init(void); - -#endif /* __ASSEMBLY__ */ - -/* - * Memory Bank Configuration Register - */ -#define FTSMC020_BANK_ENABLE (1 << 28) -#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) - -#define FTSMC020_BANK_WPROT (1 << 11) - -#define FTSMC020_BANK_SIZE_32K (0xb << 4) -#define FTSMC020_BANK_SIZE_64K (0xc << 4) -#define FTSMC020_BANK_SIZE_128K (0xd << 4) -#define FTSMC020_BANK_SIZE_256K (0xe << 4) -#define FTSMC020_BANK_SIZE_512K (0xf << 4) -#define FTSMC020_BANK_SIZE_1M (0x0 << 4) -#define FTSMC020_BANK_SIZE_2M (0x1 << 4) -#define FTSMC020_BANK_SIZE_4M (0x2 << 4) -#define FTSMC020_BANK_SIZE_8M (0x3 << 4) -#define FTSMC020_BANK_SIZE_16M (0x4 << 4) -#define FTSMC020_BANK_SIZE_32M (0x5 << 4) - -#define FTSMC020_BANK_MBW_8 (0x0 << 0) -#define FTSMC020_BANK_MBW_16 (0x1 << 0) -#define FTSMC020_BANK_MBW_32 (0x2 << 0) - -/* - * Memory Bank Timing Parameter Register - */ -#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) -#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) -#define FTSMC020_TPR_RBE (1 << 20) -#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) -#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) -#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) -#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) -#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) -#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) -#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) - -#endif /* __FTSMC020_H */ diff --git a/arch/arm/include/asm/arch-a320/fttmr010.h b/arch/arm/include/asm/arch-a320/fttmr010.h deleted file mode 100644 index 72abcb365d..0000000000 --- a/arch/arm/include/asm/arch-a320/fttmr010.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -/* - * Timer - */ -#ifndef __FTTMR010_H -#define __FTTMR010_H - -struct fttmr010 { - unsigned int timer1_counter; /* 0x00 */ - unsigned int timer1_load; /* 0x04 */ - unsigned int timer1_match1; /* 0x08 */ - unsigned int timer1_match2; /* 0x0c */ - unsigned int timer2_counter; /* 0x10 */ - unsigned int timer2_load; /* 0x14 */ - unsigned int timer2_match1; /* 0x18 */ - unsigned int timer2_match2; /* 0x1c */ - unsigned int timer3_counter; /* 0x20 */ - unsigned int timer3_load; /* 0x24 */ - unsigned int timer3_match1; /* 0x28 */ - unsigned int timer3_match2; /* 0x2c */ - unsigned int cr; /* 0x30 */ - unsigned int interrupt_state; /* 0x34 */ - unsigned int interrupt_mask; /* 0x38 */ -}; - -/* - * Timer Control Register - */ -#define FTTMR010_TM3_UPDOWN (1 << 11) -#define FTTMR010_TM2_UPDOWN (1 << 10) -#define FTTMR010_TM1_UPDOWN (1 << 9) -#define FTTMR010_TM3_OFENABLE (1 << 8) -#define FTTMR010_TM3_CLOCK (1 << 7) -#define FTTMR010_TM3_ENABLE (1 << 6) -#define FTTMR010_TM2_OFENABLE (1 << 5) -#define FTTMR010_TM2_CLOCK (1 << 4) -#define FTTMR010_TM2_ENABLE (1 << 3) -#define FTTMR010_TM1_OFENABLE (1 << 2) -#define FTTMR010_TM1_CLOCK (1 << 1) -#define FTTMR010_TM1_ENABLE (1 << 0) - -/* - * Timer Interrupt State & Mask Registers - */ -#define FTTMR010_TM3_OVERFLOW (1 << 8) -#define FTTMR010_TM3_MATCH2 (1 << 7) -#define FTTMR010_TM3_MATCH1 (1 << 6) -#define FTTMR010_TM2_OVERFLOW (1 << 5) -#define FTTMR010_TM2_MATCH2 (1 << 4) -#define FTTMR010_TM2_MATCH1 (1 << 3) -#define FTTMR010_TM1_OVERFLOW (1 << 2) -#define FTTMR010_TM1_MATCH2 (1 << 1) -#define FTTMR010_TM1_MATCH1 (1 << 0) - -#endif /* __FTTMR010_H */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index d8040025ed..1126b38a27 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -40,5 +40,17 @@ #define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE #define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register represents UART Unit Enable */ +/* + * I2C definition + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MV 1 +#define CONFIG_MV_I2C_NUM 2 +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_MV_I2C_REG {0xd4011000, 0xd4025000} +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 0 +#define CONFIG_SYS_I2C_SLAVE 0xfe +#endif #endif /* _ARMD1_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h index d21a79fa1f..73783a7647 100644 --- a/arch/arm/include/asm/arch-armada100/mfp.h +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -37,28 +37,32 @@ * offset, pull,pF, drv,dF, edge,eF ,afn,aF */ /* UART1 */ -#define MFP107_UART1_TXD MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST -#define MFP107_UART1_RXD MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST -#define MFP108_UART1_RXD MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST -#define MFP108_UART1_TXD MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST -#define MFP109_UART1_CTS MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM -#define MFP109_UART1_RTS MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM -#define MFP110_UART1_RTS MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM -#define MFP110_UART1_CTS MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM -#define MFP111_UART1_RI MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM -#define MFP111_UART1_DSR MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM -#define MFP112_UART1_DTR MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM -#define MFP112_UART1_DCD MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM +#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) +#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) +#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) +#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) +#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) /* UART2 */ -#define MFP47_UART2_RXD MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM -#define MFP48_UART2_TXD MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM -#define MFP88_UART2_RXD MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM -#define MFP89_UART2_TXD MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM +#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) +#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) +#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) /* UART3 */ -#define MFPO8_UART3_RXD MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM -#define MFPO9_UART3_TXD MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM +#define MFPO8_UART3_RXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFPO9_UART3_TXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) + +/* I2c */ +#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) +#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) /* More macros can be defined here... */ diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/clock.h index a755212f0d..8dc6e82bc6 100644 --- a/arch/arm/include/asm/arch-mx31/mx31.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MX31_H -#define __ASM_ARCH_MX31_H +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H extern u32 mx31_get_ipg_clk(void); #define imx_get_uartclk mx31_get_ipg_clk @@ -32,4 +32,4 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config); void mx31_uart1_hw_init(void); void mx31_spi2_hw_init(void); -#endif /* __ASM_ARCH_MX31_H */ +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 105f7d8be5..c830a0374e 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef __ASM_ARCH_MX31_REGS_H -#define __ASM_ARCH_MX31_REGS_H +#ifndef __ASM_ARCH_MX31_IMX_REGS_H +#define __ASM_ARCH_MX31_IMX_REGS_H #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> @@ -75,6 +75,39 @@ struct cspi_regs { u32 test; }; +/* Watchdog Timer (WDOG) registers */ +#define WDOG_ENABLE (1 << 2) +#define WDOG_WT_SHIFT 8 +struct wdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ +}; + +/* IIM Control Registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; +}; + +struct mx3_cpu_type { + u8 srev; + char *v; +}; + #define IOMUX_PADNUM_MASK 0x1ff #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) @@ -470,6 +503,8 @@ enum iomux_pins { #define CCMR_FPM (1 << 1) #define CCMR_CKIH (2 << 1) +#define MX31_IIM_BASE_ADDR 0x5001C000 + #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) @@ -739,4 +774,4 @@ enum iomux_pins { #define MXC_EHCI_IPPUE_DOWN (1 << 8) #define MXC_EHCI_IPPUE_UP (1 << 9) -#endif /* __ASM_ARCH_MX31_REGS_H */ +#endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clocks.h index 40f80baf61..bed0002ec0 100644 --- a/arch/arm/include/asm/arch-omap3/clocks.h +++ b/arch/arm/include/asm/arch-omap3/clocks.h @@ -68,6 +68,7 @@ extern dpll_param *get_mpu_dpll_param(void); extern dpll_param *get_iva_dpll_param(void); extern dpll_param *get_core_dpll_param(void); extern dpll_param *get_per_dpll_param(void); +extern dpll_param *get_per2_dpll_param(void); extern dpll_param *get_36x_mpu_dpll_param(void); extern dpll_param *get_36x_iva_dpll_param(void); diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h index 30ef690fa2..ef600dd9db 100644 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -282,6 +282,32 @@ #define PER_FSEL_38P4 0x07 #define PER_M2_38P4 0x09 +/* PER2 DPLL */ +#define PER2_M_12 0x78 +#define PER2_N_12 0x0B +#define PER2_FSEL_12 0x03 +#define PER2_M2_12 0x01 + +#define PER2_M_13 0x78 +#define PER2_N_13 0x0C +#define PER2_FSEL_13 0x03 +#define PER2_M2_13 0x01 + +#define PER2_M_19P2 0x2EE +#define PER2_N_19P2 0x0B +#define PER2_FSEL_19P2 0x06 +#define PER2_M2_19P2 0x0A + +#define PER2_M_26 0x78 +#define PER2_N_26 0x0C +#define PER2_FSEL_26 0x03 +#define PER2_M2_26 0x01 + +#define PER2_M_38P4 0x2EE +#define PER2_N_38P4 0x0B +#define PER2_FSEL_38P4 0x06 +#define PER2_M2_38P4 0x0A + /* 36XX PER DPLL */ #define PER_36XX_M_12 0x1B0 diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 962d6d40aa..e944de7192 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -347,10 +347,13 @@ struct prcm { u32 clksel2_pll_mpu; /* 0x944 */ u8 res6[0xb8]; u32 fclken1_core; /* 0xa00 */ - u8 res7[0xc]; + u32 res_fclken2_core; + u32 fclken3_core; /* 0xa08 */ + u8 res7[0x4]; u32 iclken1_core; /* 0xa10 */ u32 iclken2_core; /* 0xa14 */ - u8 res8[0x28]; + u32 iclken3_core; /* 0xa18 */ + u8 res8[0x24]; u32 clksel_core; /* 0xa40 */ u8 res9[0xbc]; u32 fclken_gfx; /* 0xb00 */ @@ -368,13 +371,17 @@ struct prcm { u32 clksel_wkup; /* 0xc40 */ u8 res16[0xbc]; u32 clken_pll; /* 0xd00 */ - u8 res17[0x1c]; + u32 clken2_pll; /* 0xd04 */ + u8 res17[0x18]; u32 idlest_ckgen; /* 0xd20 */ - u8 res18[0x1c]; + u32 idlest2_ckgen; /* 0xd24 */ + u8 res18[0x18]; u32 clksel1_pll; /* 0xd40 */ u32 clksel2_pll; /* 0xd44 */ u32 clksel3_pll; /* 0xd48 */ - u8 res19[0xb4]; + u32 clksel4_pll; /* 0xd4c */ + u32 clksel5_pll; /* 0xd50 */ + u8 res19[0xac]; u32 fclken_dss; /* 0xe00 */ u8 res20[0xc]; u32 iclken_dss; /* 0xe10 */ @@ -394,6 +401,10 @@ struct prcm { u32 clksel_per; /* 0x1040 */ u8 res28[0xfc]; u32 clksel1_emu; /* 0x1140 */ + u8 res29[0x2bc]; + u32 fclken_usbhost; /* 0x1400 */ + u8 res30[0xc]; + u32 iclken_usbhost; /* 0x1410 */ }; #else /* __ASSEMBLY__ */ #define CM_CLKSEL_CORE 0x48004a40 diff --git a/arch/arm/include/asm/arch-omap3/ehci_omap3.h b/arch/arm/include/asm/arch-omap3/ehci_omap3.h new file mode 100644 index 0000000000..cd01f50295 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/ehci_omap3.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2011 + * Alexander Holler <holler@ahsoftware.de> + * + * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37 + * + * See there for additional Copyrights. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +#ifndef _EHCI_OMAP3_H_ +#define _EHCI_OMAP3_H_ + +/* USB/EHCI registers */ +#define OMAP3_USBTLL_BASE 0x48062000UL +#define OMAP3_UHH_BASE 0x48064000UL +#define OMAP3_EHCI_BASE 0x48064800UL + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG (0x10) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) + +#define OMAP_USBTLL_SYSSTATUS (0x14) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) + +/* UHH Register Set */ +#define OMAP_UHH_SYSCONFIG (0x10) +#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) +#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) +#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) +#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) +#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) + +#define OMAP_UHH_HOSTCONFIG (0x40) +#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) +#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) +#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) + +#endif /* _EHCI_OMAP3_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h new file mode 100644 index 0000000000..818214f466 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/omap3-regs.h @@ -0,0 +1,95 @@ +/* + * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP3_REGS_H +#define _OMAP3_REGS_H + +/* + * Register definitions for OMAP3 processors. + */ + +/* + * GPMC_CONFIG1 - GPMC_CONFIG7 + */ + +/* Values for GPMC_CONFIG1 - signal control parameters */ +#define WRAPBURST (1 << 31) +#define READMULTIPLE (1 << 30) +#define READTYPE (1 << 29) +#define WRITEMULTIPLE (1 << 28) +#define WRITETYPE (1 << 27) +#define CLKACTIVATIONTIME(x) (((x) & 3) << 25) +#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) +#define WAITREADMONITORING (1 << 22) +#define WAITWRITEMONITORING (1 << 21) +#define WAITMONITORINGTIME(x) (((x) & 3) << 18) +#define WAITPINSELECT(x) (((x) & 3) << 16) +#define DEVICESIZE(x) (((x) & 3) << 12) +#define DEVICESIZE_8BIT DEVICESIZE(0) +#define DEVICESIZE_16BIT DEVICESIZE(1) +#define DEVICETYPE(x) (((x) & 3) << 10) +#define DEVICETYPE_NOR DEVICETYPE(0) +#define DEVICETYPE_NAND DEVICETYPE(2) +#define MUXADDDATA (1 << 9) +#define TIMEPARAGRANULARITY (1 << 4) +#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) + +/* Values for GPMC_CONFIG2 - CS timing */ +#define CSWROFFTIME(x) (((x) & 0x1f) << 16) +#define CSRDOFFTIME(x) (((x) & 0x1f) << 8) +#define CSEXTRADELAY (1 << 7) +#define CSONTIME(x) (((x) & 0xf) << 0) + +/* Values for GPMC_CONFIG3 - nADV timing */ +#define ADVWROFFTIME(x) (((x) & 0x1f) << 16) +#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) +#define ADVEXTRADELAY (1 << 7) +#define ADVONTIME(x) (((x) & 0xf) << 0) + +/* Values for GPMC_CONFIG4 - nWE and nOE timing */ +#define WEOFFTIME(x) (((x) & 0x1f) << 24) +#define WEEXTRADELAY (1 << 23) +#define WEONTIME(x) (((x) & 0xf) << 16) +#define OEOFFTIME(x) (((x) & 0x1f) << 8) +#define OEEXTRADELAY (1 << 7) +#define OEONTIME(x) (((x) & 0xf) << 0) + +/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ +#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) +#define RDACCESSTIME(x) (((x) & 0x1f) << 16) +#define WRCYCLETIME(x) (((x) & 0x1f) << 8) +#define RDCYCLETIME(x) (((x) & 0x1f) << 0) + +/* Values for GPMC_CONFIG6 - misc timings */ +#define WRACCESSTIME(x) (((x) & 0x1f) << 24) +#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) +#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) +#define CYCLE2CYCLESAMECSEN (1 << 7) +#define CYCLE2CYCLEDIFFCSEN (1 << 6) +#define BUSTURNAROUND(x) (((x) & 0xf) << 0) + +/* Values for GPMC_CONFIG7 - CS address mapping configuration */ +#define MASKADDRESS(x) (((x) & 0xf) << 8) +#define CSVALID (1 << 6) +#define BASEADDRESS(x) (((x) & 0x3f) << 0) + +#endif /* _OMAP3_REGS_H */ diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h index 3957c796f2..cc2b5415c1 100644 --- a/arch/arm/include/asm/arch-omap3/omap3.h +++ b/arch/arm/include/asm/arch-omap3/omap3.h @@ -50,6 +50,20 @@ /* CONTROL */ #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000) +#ifndef __ASSEMBLY__ +/* Signal Integrity Parameter Control Registers */ +struct control_prog_io { + unsigned char res[0x408]; + unsigned int io2; /* 0x408 */ + unsigned char res2[0x38]; + unsigned int io0; /* 0x444 */ + unsigned int io1; /* 0x448 */ +}; +#endif /* __ASSEMBLY__ */ + +/* Bit definition for CONTROL_PROG_IO1 */ +#define PRG_I2C2_PULLUPRESX 0x00000001 + /* UART */ #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index c84efaf02b..2f52ca8407 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * Based on original Kirorion5x_ood support which is * (C) Copyright 2009 diff --git a/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/arch/arm/include/asm/arch-orion5x/mv88f5182.h index 86ba08deba..0b46aef001 100644 --- a/arch/arm/include/asm/arch-orion5x/mv88f5182.h +++ b/arch/arm/include/asm/arch-orion5x/mv88f5182.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * Based on original Kirkwood 88F6182 support which is * (C) Copyright 2009 diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h index e3d3f76dbb..9aeef88f36 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr> + * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> * * Based on original Kirkwood support which is * (C) Copyright 2009 @@ -42,6 +42,7 @@ #define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x) /* Documented registers */ +#define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500)) #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h index 710b3862ca..5658592f83 100644 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ b/arch/arm/include/asm/arch-pantheon/config.h @@ -34,5 +34,15 @@ #define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE #define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register represents UART Unit Enable */ +/* + * I2C definition + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MV 1 +#define CONFIG_MV_I2C_REG 0xd4011000 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 0 +#define CONFIG_SYS_I2C_SLAVE 0xfe +#endif #endif /* _PANTHEON_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h index 30f4393050..60955c5a55 100644 --- a/arch/arm/include/asm/arch-pantheon/cpu.h +++ b/arch/arm/include/asm/arch-pantheon/cpu.h @@ -50,7 +50,9 @@ struct panthapb_registers { u32 uart0; /*0x000*/ u32 uart1; /*0x004*/ u32 gpio; /*0x008*/ - u8 pad0[0x034 - 0x08 - 4]; + u8 pad0[0x02c - 0x08 - 4]; + u32 twsi; /*0x02c*/ + u8 pad1[0x034 - 0x2c - 4]; u32 timers; /*0x034*/ }; diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h index fb291cf554..e9391961b1 100644 --- a/arch/arm/include/asm/arch-pantheon/mfp.h +++ b/arch/arm/include/asm/arch-pantheon/mfp.h @@ -32,8 +32,10 @@ * offset, pull,pF, drv,dF, edge,eF ,afn,aF */ /* UART2 */ -#define MFP47_UART2_RXD MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM -#define MFP48_UART2_TXD MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM +#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM) +#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM) +#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM) +#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) /* More macros can be defined here... */ diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 65a387f9fc..109fdc06aa 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -456,62 +456,6 @@ typedef void (*ExcpHndlr) (void) ; IrSR_XMITIR_IR_MODE) /* - * I2C registers - */ -#define IBMR 0x40301680 /* I2C Bus Monitor Register - IBMR */ -#define IDBR 0x40301688 /* I2C Data Buffer Register - IDBR */ -#define ICR 0x40301690 /* I2C Control Register - ICR */ -#define ISR 0x40301698 /* I2C Status Register - ISR */ -#define ISAR 0x403016A0 /* I2C Slave Address Register - ISAR */ - -#ifdef CONFIG_CPU_MONAHANS -#define PWRIBMR 0x40f500C0 /* Power I2C Bus Monitor Register-IBMR */ -#define PWRIDBR 0x40f500C4 /* Power I2C Data Buffer Register-IDBR */ -#define PWRICR 0x40f500C8 /* Power I2C Control Register - ICR */ -#define PWRISR 0x40f500CC /* Power I2C Status Register - ISR */ -#define PWRISAR 0x40f500D0 /* Power I2C Slave Address Register-ISAR */ -#else -#define PWRIBMR 0x40f00180 /* Power I2C Bus Monitor Register-IBMR */ -#define PWRIDBR 0x40f00188 /* Power I2C Data Buffer Register-IDBR */ -#define PWRICR 0x40f00190 /* Power I2C Control Register - ICR */ -#define PWRISR 0x40f00198 /* Power I2C Status Register - ISR */ -#define PWRISAR 0x40f001A0 /* Power I2C Slave Address Register-ISAR */ -#endif - -/* ----- Control register bits ---------------------------------------- */ - -#define ICR_START 0x1 /* start bit */ -#define ICR_STOP 0x2 /* stop bit */ -#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ -#define ICR_TB 0x8 /* transfer byte bit */ -#define ICR_MA 0x10 /* master abort */ -#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */ -#define ICR_IUE 0x40 /* unit enable */ -#define ICR_GCD 0x80 /* general call disable */ -#define ICR_ITEIE 0x100 /* enable tx interrupts */ -#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */ -#define ICR_BEIE 0x400 /* enable bus error ints */ -#define ICR_SSDIE 0x800 /* slave STOP detected int enable */ -#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ -#define ICR_SADIE 0x2000 /* slave address detected int enable */ -#define ICR_UR 0x4000 /* unit reset */ -#define ICR_FM 0x8000 /* Fast Mode */ - -/* ----- Status register bits ----------------------------------------- */ - -#define ISR_RWM 0x1 /* read/write mode */ -#define ISR_ACKNAK 0x2 /* ack/nak status */ -#define ISR_UB 0x4 /* unit busy */ -#define ISR_IBB 0x8 /* bus busy */ -#define ISR_SSD 0x10 /* slave stop detected */ -#define ISR_ALD 0x20 /* arbitration loss detected */ -#define ISR_ITE 0x40 /* tx buffer empty */ -#define ISR_IRF 0x80 /* rx buffer full */ -#define ISR_GCAD 0x100 /* general call address detected */ -#define ISR_SAD 0x200 /* slave address detected */ -#define ISR_BED 0x400 /* bus error no ACK/NAK */ - -/* * Serial Audio Controller */ /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index 6d573bf465..bd8ad2ca04 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -149,6 +149,9 @@ struct clk_rst_ctlr { uint crc_clk_src_csite; /*_CSITE_0, 0x1D4 */ uint crc_reserved19[9]; /* 0x1D8-1F8 */ uint crc_clk_src_osc; /*_OSC_0, 0x1FC */ + uint crc_reserved20[80]; /* 0x200-33C */ + uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */ + uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */ }; #define PLL_BYPASS (1 << 31) @@ -157,9 +160,35 @@ struct clk_rst_ctlr { #define PLL_DIVP (1 << 20) /* post divider, b22:20 */ #define PLL_DIVM 0x0C /* input divider, b4:0 */ -#define SWR_UARTD_RST (1 << 2) -#define CLK_ENB_UARTD (1 << 2) +#define SWR_UARTD_RST (1 << 1) +#define CLK_ENB_UARTD (1 << 1) #define SWR_UARTA_RST (1 << 6) #define CLK_ENB_UARTA (1 << 6) +#define SWR_CPU_RST (1 << 0) +#define CLK_ENB_CPU (1 << 0) +#define SWR_CSITE_RST (1 << 9) +#define CLK_ENB_CSITE (1 << 9) + +#define SET_CPURESET0 (1 << 0) +#define SET_DERESET0 (1 << 4) +#define SET_DBGRESET0 (1 << 12) + +#define SET_CPURESET1 (1 << 1) +#define SET_DERESET1 (1 << 5) +#define SET_DBGRESET1 (1 << 13) + +#define CLR_CPURESET0 (1 << 0) +#define CLR_DERESET0 (1 << 4) +#define CLR_DBGRESET0 (1 << 12) + +#define CLR_CPURESET1 (1 << 1) +#define CLR_DERESET1 (1 << 5) +#define CLR_DBGRESET1 (1 << 13) + +#define CPU0_CLK_STP (1 << 8) +#define CPU1_CLK_STP (1 << 9) + +#define CPCON (1 << 8) + #endif /* CLK_RST_H */ diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h new file mode 100644 index 0000000000..0fb8f0d40f --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/gpio.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2011, Google Inc. All rights reserved. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA2_GPIO_H_ +#define _TEGRA2_GPIO_H_ + +/* + * The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports, + * each with 8 GPIOs. + */ +#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */ +#define TEGRA_GPIO_BANKS 8 /* The number of banks */ + +/* GPIO Controller registers for a single bank */ +struct gpio_ctlr_bank { + uint gpio_config[TEGRA_GPIO_PORTS]; + uint gpio_dir_out[TEGRA_GPIO_PORTS]; + uint gpio_out[TEGRA_GPIO_PORTS]; + uint gpio_in[TEGRA_GPIO_PORTS]; + uint gpio_int_status[TEGRA_GPIO_PORTS]; + uint gpio_int_enable[TEGRA_GPIO_PORTS]; + uint gpio_int_level[TEGRA_GPIO_PORTS]; + uint gpio_int_clear[TEGRA_GPIO_PORTS]; +}; + +struct gpio_ctlr { + struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; +}; + +#define GPIO_BANK(x) ((x) >> 5) +#define GPIO_PORT(x) (((x) >> 3) & 0x3) +#define GPIO_BIT(x) ((x) & 0x7) + +/* + * GPIO_PI3 = Port I = 8, bit = 3. + * Seaboard: used for UART/SPI selection + * Harmony: not used + */ +#define GPIO_PI3 ((8 << 3) | 3) + +#endif /* TEGRA2_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/pmc.h b/arch/arm/include/asm/arch-tegra2/pmc.h index 7ec9eeba1c..b1d47cd2e3 100644 --- a/arch/arm/include/asm/arch-tegra2/pmc.h +++ b/arch/arm/include/asm/arch-tegra2/pmc.h @@ -121,4 +121,12 @@ struct pmc_ctlr { uint pmc_gate; /* _GATE_0, offset 15C */ }; +#define CPU_PWRED 1 +#define CPU_CLMP 1 + +#define PARTID_CP 0xFFFFFFF8 +#define START_CP (1 << 8) + +#define CPUPWRREQ_OE (1 << 16) + #endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra2/scu.h b/arch/arm/include/asm/arch-tegra2/scu.h new file mode 100644 index 0000000000..787ded0fe0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/scu.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SCU_H_ +#define _SCU_H_ + +/* ARM Snoop Control Unit (SCU) registers */ +struct scu_ctlr { + uint scu_ctrl; /* SCU Control Register, offset 00 */ + uint scu_cfg; /* SCU Config Register, offset 04 */ + uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ + uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ + uint scu_reserved0[12]; /* reserved, offset 10-3C */ + uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ + uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ + uint scu_reserved1[2]; /* reserved, offset 48-4C */ + uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ + uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ +}; + +#define SCU_CTRL_ENABLE (1 << 0) + +#endif /* SCU_H */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index 9001b68994..742a75a0da 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -25,8 +25,13 @@ #define _TEGRA2_H_ #define NV_PA_SDRAM_BASE 0x00000000 +#define NV_PA_ARM_PERIPHBASE 0x50040000 +#define NV_PA_PG_UP_BASE 0x60000000 #define NV_PA_TMRUS_BASE 0x60005010 #define NV_PA_CLK_RST_BASE 0x60006000 +#define NV_PA_FLOW_BASE 0x60007000 +#define NV_PA_GPIO_BASE 0x6000D000 +#define NV_PA_EVP_BASE 0x6000F000 #define NV_PA_APB_MISC_BASE 0x70000000 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) #define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) @@ -34,9 +39,13 @@ #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) #define NV_PA_PMC_BASE 0x7000E400 +#define NV_PA_CSITE_BASE 0x70040000 #define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC +#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) +#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) +#define PG_UP_TAG_AVP 0xAAAAAAAA #ifndef __ASSEMBLY__ struct timerus { diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h new file mode 100644 index 0000000000..5e4789b145 --- /dev/null +++ b/arch/arm/include/asm/assembler.h @@ -0,0 +1,60 @@ +/* + * arch/arm/include/asm/assembler.h + * + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This file contains arm architecture specific defines + * for the different processors. + * + * Do not include any C declarations in this file - it is included by + * assembler source. + */ + +/* + * Endian independent macros for shifting bytes within registers. + */ +#ifndef __ARMEB__ +#define pull lsr +#define push lsl +#define get_byte_0 lsl #0 +#define get_byte_1 lsr #8 +#define get_byte_2 lsr #16 +#define get_byte_3 lsr #24 +#define put_byte_0 lsl #0 +#define put_byte_1 lsl #8 +#define put_byte_2 lsl #16 +#define put_byte_3 lsl #24 +#else +#define pull lsl +#define push lsr +#define get_byte_0 lsr #24 +#define get_byte_1 lsr #16 +#define get_byte_2 lsr #8 +#define get_byte_3 lsl #0 +#define put_byte_0 lsl #24 +#define put_byte_1 lsl #16 +#define put_byte_2 lsl #8 +#define put_byte_3 lsl #0 +#endif + +/* + * Data preload for architectures that support it + */ +#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \ + defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \ + defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \ + defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \ + defined(__ARM_ARCH_7R__) +#define PLD(code...) code +#else +#define PLD(code...) +#endif + +/* + * Cache alligned + */ +#define CALGN(code...) code diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h index c3ea582cab..c6dfb254b5 100644 --- a/arch/arm/include/asm/string.h +++ b/arch/arm/include/asm/string.h @@ -1,6 +1,8 @@ #ifndef __ASM_ARM_STRING_H #define __ASM_ARM_STRING_H +#include <config.h> + /* * We don't do inline string functions, since the * optimised inline asm versions are not small. @@ -12,7 +14,9 @@ extern char * strrchr(const char * s, int c); #undef __HAVE_ARCH_STRCHR extern char * strchr(const char * s, int c); -#undef __HAVE_ARCH_MEMCPY +#ifdef CONFIG_USE_ARCH_MEMCPY +#define __HAVE_ARCH_MEMCPY +#endif extern void * memcpy(void *, const void *, __kernel_size_t); #undef __HAVE_ARCH_MEMMOVE @@ -22,7 +26,9 @@ extern void * memmove(void *, const void *, __kernel_size_t); extern void * memchr(const void *, int, __kernel_size_t); #undef __HAVE_ARCH_MEMZERO -#undef __HAVE_ARCH_MEMSET +#ifdef CONFIG_USE_ARCH_MEMSET +#define __HAVE_ARCH_MEMSET +#endif extern void * memset(void *, int, __kernel_size_t); #if 0 diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 454440c057..03b1b5e4af 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -44,6 +44,8 @@ COBJS-y += cache-cp15.o endif COBJS-y += interrupts.o COBJS-y += reset.o +SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o +SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \ $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index dc46e21dba..1a784a1e19 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -356,9 +356,13 @@ void board_init_f (ulong bootflag) #endif /* CONFIG_VFD */ #ifdef CONFIG_LCD +#ifdef CONFIG_FB_ADDR + gd->fb_base = CONFIG_FB_ADDR; +#else /* reserve memory for LCD display (always full pages) */ addr = lcd_setmem (addr); gd->fb_base = addr; +#endif /* CONFIG_FB_ADDR */ #endif /* CONFIG_LCD */ /* @@ -399,7 +403,7 @@ void board_init_f (ulong bootflag) CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp); #endif /* leave 3 words for abort-stack */ - addr_sp -= 3; + addr_sp -= 12; /* 8-byte alignment for ABI compliance */ addr_sp &= ~0x07; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 77349530f0..802e833a2e 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -178,7 +178,6 @@ static int bootm_linux_fdt(int machid, bootm_headers_t *images) { ulong rd_len; void (*kernel_entry)(int zero, int dt_machid, void *dtblob); - ulong bootmap_base = getenv_bootm_low(); ulong of_size = images->ft_len; char **of_flat_tree = &images->ft_addr; ulong *initrd_start = &images->initrd_start; @@ -188,13 +187,15 @@ static int bootm_linux_fdt(int machid, bootm_headers_t *images) kernel_entry = (void (*)(int, int, void *))images->ep; + boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); + rd_len = images->rd_end - images->rd_start; ret = boot_ramdisk_high(lmb, images->rd_start, rd_len, initrd_start, initrd_end); if (ret) return ret; - ret = boot_relocate_fdt(lmb, bootmap_base, of_flat_tree, &of_size); + ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); if (ret) return ret; diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S new file mode 100644 index 0000000000..40db90e5f4 --- /dev/null +++ b/arch/arm/lib/memcpy.S @@ -0,0 +1,241 @@ +/* + * linux/arch/arm/lib/memcpy.S + * + * Author: Nicolas Pitre + * Created: Sep 28, 2005 + * Copyright: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <asm/assembler.h> + +#define W(instr) instr + +#define LDR1W_SHIFT 0 +#define STR1W_SHIFT 0 + + .macro ldr1w ptr reg abort + W(ldr) \reg, [\ptr], #4 + .endm + + .macro ldr4w ptr reg1 reg2 reg3 reg4 abort + ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4} + .endm + + .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort + ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} + .endm + + .macro ldr1b ptr reg cond=al abort + ldr\cond\()b \reg, [\ptr], #1 + .endm + + .macro str1w ptr reg abort + W(str) \reg, [\ptr], #4 + .endm + + .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort + stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8} + .endm + + .macro str1b ptr reg cond=al abort + str\cond\()b \reg, [\ptr], #1 + .endm + + .macro enter reg1 reg2 + stmdb sp!, {r0, \reg1, \reg2} + .endm + + .macro exit reg1 reg2 + ldmfd sp!, {r0, \reg1, \reg2} + .endm + + .text + +/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ + +.globl memcpy +memcpy: + + enter r4, lr + + subs r2, r2, #4 + blt 8f + ands ip, r0, #3 + PLD( pld [r1, #0] ) + bne 9f + ands ip, r1, #3 + bne 10f + +1: subs r2, r2, #(28) + stmfd sp!, {r5 - r8} + blt 5f + + CALGN( ands ip, r0, #31 ) + CALGN( rsb r3, ip, #32 ) + CALGN( sbcnes r4, r3, r2 ) @ C is always set here + CALGN( bcs 2f ) + CALGN( adr r4, 6f ) + CALGN( subs r2, r2, r3 ) @ C gets set + CALGN( add pc, r4, ip ) + + PLD( pld [r1, #0] ) +2: PLD( subs r2, r2, #96 ) + PLD( pld [r1, #28] ) + PLD( blt 4f ) + PLD( pld [r1, #60] ) + PLD( pld [r1, #92] ) + +3: PLD( pld [r1, #124] ) +4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f + subs r2, r2, #32 + str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f + bge 3b + PLD( cmn r2, #96 ) + PLD( bge 4b ) + +5: ands ip, r2, #28 + rsb ip, ip, #32 +#if LDR1W_SHIFT > 0 + lsl ip, ip, #LDR1W_SHIFT +#endif + addne pc, pc, ip @ C is always clear here + b 7f +6: + .rept (1 << LDR1W_SHIFT) + W(nop) + .endr + ldr1w r1, r3, abort=20f + ldr1w r1, r4, abort=20f + ldr1w r1, r5, abort=20f + ldr1w r1, r6, abort=20f + ldr1w r1, r7, abort=20f + ldr1w r1, r8, abort=20f + ldr1w r1, lr, abort=20f + +#if LDR1W_SHIFT < STR1W_SHIFT + lsl ip, ip, #STR1W_SHIFT - LDR1W_SHIFT +#elif LDR1W_SHIFT > STR1W_SHIFT + lsr ip, ip, #LDR1W_SHIFT - STR1W_SHIFT +#endif + add pc, pc, ip + nop + .rept (1 << STR1W_SHIFT) + W(nop) + .endr + str1w r0, r3, abort=20f + str1w r0, r4, abort=20f + str1w r0, r5, abort=20f + str1w r0, r6, abort=20f + str1w r0, r7, abort=20f + str1w r0, r8, abort=20f + str1w r0, lr, abort=20f + + CALGN( bcs 2b ) + +7: ldmfd sp!, {r5 - r8} + +8: movs r2, r2, lsl #31 + ldr1b r1, r3, ne, abort=21f + ldr1b r1, r4, cs, abort=21f + ldr1b r1, ip, cs, abort=21f + str1b r0, r3, ne, abort=21f + str1b r0, r4, cs, abort=21f + str1b r0, ip, cs, abort=21f + + exit r4, pc + +9: rsb ip, ip, #4 + cmp ip, #2 + ldr1b r1, r3, gt, abort=21f + ldr1b r1, r4, ge, abort=21f + ldr1b r1, lr, abort=21f + str1b r0, r3, gt, abort=21f + str1b r0, r4, ge, abort=21f + subs r2, r2, ip + str1b r0, lr, abort=21f + blt 8b + ands ip, r1, #3 + beq 1b + +10: bic r1, r1, #3 + cmp ip, #2 + ldr1w r1, lr, abort=21f + beq 17f + bgt 18f + + + .macro forward_copy_shift pull push + + subs r2, r2, #28 + blt 14f + + CALGN( ands ip, r0, #31 ) + CALGN( rsb ip, ip, #32 ) + CALGN( sbcnes r4, ip, r2 ) @ C is always set here + CALGN( subcc r2, r2, ip ) + CALGN( bcc 15f ) + +11: stmfd sp!, {r5 - r9} + + PLD( pld [r1, #0] ) + PLD( subs r2, r2, #96 ) + PLD( pld [r1, #28] ) + PLD( blt 13f ) + PLD( pld [r1, #60] ) + PLD( pld [r1, #92] ) + +12: PLD( pld [r1, #124] ) +13: ldr4w r1, r4, r5, r6, r7, abort=19f + mov r3, lr, pull #\pull + subs r2, r2, #32 + ldr4w r1, r8, r9, ip, lr, abort=19f + orr r3, r3, r4, push #\push + mov r4, r4, pull #\pull + orr r4, r4, r5, push #\push + mov r5, r5, pull #\pull + orr r5, r5, r6, push #\push + mov r6, r6, pull #\pull + orr r6, r6, r7, push #\push + mov r7, r7, pull #\pull + orr r7, r7, r8, push #\push + mov r8, r8, pull #\pull + orr r8, r8, r9, push #\push + mov r9, r9, pull #\pull + orr r9, r9, ip, push #\push + mov ip, ip, pull #\pull + orr ip, ip, lr, push #\push + str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f + bge 12b + PLD( cmn r2, #96 ) + PLD( bge 13b ) + + ldmfd sp!, {r5 - r9} + +14: ands ip, r2, #28 + beq 16f + +15: mov r3, lr, pull #\pull + ldr1w r1, lr, abort=21f + subs ip, ip, #4 + orr r3, r3, lr, push #\push + str1w r0, r3, abort=21f + bgt 15b + CALGN( cmp r2, #0 ) + CALGN( bge 11b ) + +16: sub r1, r1, #(\push / 8) + b 8b + + .endm + + + forward_copy_shift pull=8 push=24 + +17: forward_copy_shift pull=16 push=16 + +18: forward_copy_shift pull=24 push=8 + diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S new file mode 100644 index 0000000000..0cdf89535a --- /dev/null +++ b/arch/arm/lib/memset.S @@ -0,0 +1,126 @@ +/* + * linux/arch/arm/lib/memset.S + * + * Copyright (C) 1995-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * ASM optimised string functions + */ +#include <asm/assembler.h> + + .text + .align 5 + .word 0 + +1: subs r2, r2, #4 @ 1 do we have enough + blt 5f @ 1 bytes to align with? + cmp r3, #2 @ 1 + strltb r1, [r0], #1 @ 1 + strleb r1, [r0], #1 @ 1 + strb r1, [r0], #1 @ 1 + add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3)) +/* + * The pointer is now aligned and the length is adjusted. Try doing the + * memset again. + */ + +.globl memset +memset: + ands r3, r0, #3 @ 1 unaligned? + bne 1b @ 1 +/* + * we know that the pointer in r0 is aligned to a word boundary. + */ + orr r1, r1, r1, lsl #8 + orr r1, r1, r1, lsl #16 + mov r3, r1 + cmp r2, #16 + blt 4f + +#if ! CALGN(1)+0 + +/* + * We need an extra register for this loop - save the return address and + * use the LR + */ + str lr, [sp, #-4]! + mov ip, r1 + mov lr, r1 + +2: subs r2, r2, #64 + stmgeia r0!, {r1, r3, ip, lr} @ 64 bytes at a time. + stmgeia r0!, {r1, r3, ip, lr} + stmgeia r0!, {r1, r3, ip, lr} + stmgeia r0!, {r1, r3, ip, lr} + bgt 2b + ldmeqfd sp!, {pc} @ Now <64 bytes to go. +/* + * No need to correct the count; we're only testing bits from now on + */ + tst r2, #32 + stmneia r0!, {r1, r3, ip, lr} + stmneia r0!, {r1, r3, ip, lr} + tst r2, #16 + stmneia r0!, {r1, r3, ip, lr} + ldr lr, [sp], #4 + +#else + +/* + * This version aligns the destination pointer in order to write + * whole cache lines at once. + */ + + stmfd sp!, {r4-r7, lr} + mov r4, r1 + mov r5, r1 + mov r6, r1 + mov r7, r1 + mov ip, r1 + mov lr, r1 + + cmp r2, #96 + tstgt r0, #31 + ble 3f + + and ip, r0, #31 + rsb ip, ip, #32 + sub r2, r2, ip + movs ip, ip, lsl #(32 - 4) + stmcsia r0!, {r4, r5, r6, r7} + stmmiia r0!, {r4, r5} + tst ip, #(1 << 30) + mov ip, r1 + strne r1, [r0], #4 + +3: subs r2, r2, #64 + stmgeia r0!, {r1, r3-r7, ip, lr} + stmgeia r0!, {r1, r3-r7, ip, lr} + bgt 3b + ldmeqfd sp!, {r4-r7, pc} + + tst r2, #32 + stmneia r0!, {r1, r3-r7, ip, lr} + tst r2, #16 + stmneia r0!, {r4-r7} + ldmfd sp!, {r4-r7, lr} + +#endif + +4: tst r2, #8 + stmneia r0!, {r1, r3} + tst r2, #4 + strne r1, [r0], #4 +/* + * When we get here, we've got less than 4 bytes to zero. We + * may have an unaligned pointer as well. + */ +5: tst r2, #2 + strneb r1, [r0], #1 + strneb r1, [r0], #1 + tst r2, #1 + strneb r1, [r0], #1 + mov pc, lr diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 1121ca1cc2..9488c49132 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -23,7 +23,7 @@ CROSS_COMPILE ?= avr32-linux- -STANDALONE_LOAD_ADDR = 0x00000000 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax PLATFORM_LDFLAGS += --relax diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index f4503eacb9..f0909e95d2 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -23,8 +23,15 @@ CROSS_COMPILE ?= bfin-uclinux- -STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin +CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin +ifeq ($(CONFIG_BFIN_CPU),) +CONFIG_BFIN_CPU := \ + $(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \ + $(src)include/configs/$(BOARD).h) +else +CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) +endif CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic @@ -34,7 +41,6 @@ LDFLAGS_FINAL += --gc-sections LDFLAGS += -m elf32bfin PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -PLATFORM_CPPFLAGS += -DBFIN_CPU='"$(CONFIG_BFIN_CPU)"' PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) @@ -67,6 +73,13 @@ endif LDR_FLAGS += $(LDR_FLAGS-y) +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) + ifeq ($(wildcard $(TOPDIR)/board/$(BOARD)/u-boot.lds*),) LDSCRIPT = $(obj)arch/$(ARCH)/lib/u-boot.lds.S endif + +ifneq ($(CONFIG_SYS_TEXT_BASE),) +$(error do not set CONFIG_SYS_TEXT_BASE for Blackfin boards) +endif diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index 4a9e577a87..df10f1bc65 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -18,7 +18,6 @@ CEXTRA := initcode.o SEXTRA := start.o SOBJS := interrupt.o cache.o COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o -COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o COBJS-y += cpu.o COBJS-y += gpio.o COBJS-y += interrupts.o diff --git a/arch/blackfin/cpu/cmd_gpio.c b/arch/blackfin/cpu/cmd_gpio.c deleted file mode 100644 index e96413b639..0000000000 --- a/arch/blackfin/cpu/cmd_gpio.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Control GPIO pins on the fly - * - * Copyright (c) 2008-2010 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <command.h> -#include <linux/ctype.h> - -#include <asm/blackfin.h> -#include <asm/gpio.h> - -enum { - GPIO_INPUT, - GPIO_SET, - GPIO_CLEAR, - GPIO_TOGGLE, -}; - -int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc == 2 && !strcmp(argv[1], "status")) { - bfin_gpio_labels(); - return 0; - } - - if (argc != 3) - show_usage: - return cmd_usage(cmdtp); - - /* parse the behavior */ - ulong sub_cmd; - switch (argv[1][0]) { - case 'i': sub_cmd = GPIO_INPUT; break; - case 's': sub_cmd = GPIO_SET; break; - case 'c': sub_cmd = GPIO_CLEAR; break; - case 't': sub_cmd = GPIO_TOGGLE; break; - default: goto show_usage; - } - - /* parse the pin with format: [p][port]<#> */ - const char *str_pin = argv[2]; - - /* grab the [p]<port> portion */ - ulong port_base; - if (tolower(*str_pin) == 'p') ++str_pin; - switch (tolower(*str_pin)) { -#ifdef GPIO_PA0 - case 'a': port_base = GPIO_PA0; break; -#endif -#ifdef GPIO_PB0 - case 'b': port_base = GPIO_PB0; break; -#endif -#ifdef GPIO_PC0 - case 'c': port_base = GPIO_PC0; break; -#endif -#ifdef GPIO_PD0 - case 'd': port_base = GPIO_PD0; break; -#endif -#ifdef GPIO_PE0 - case 'e': port_base = GPIO_PE0; break; -#endif -#ifdef GPIO_PF0 - case 'f': port_base = GPIO_PF0; break; -#endif -#ifdef GPIO_PG0 - case 'g': port_base = GPIO_PG0; break; -#endif -#ifdef GPIO_PH0 - case 'h': port_base = GPIO_PH0; break; -#endif -#ifdef GPIO_PI0 - case 'i': port_base = GPIO_PI0; break; -#endif -#ifdef GPIO_PJ - case 'j': port_base = GPIO_PJ0; break; -#endif - default: goto show_usage; - } - - /* grab the <#> portion */ - ulong pin = simple_strtoul(str_pin + 1, NULL, 10); - if (pin > 15) - goto show_usage; - - /* grab the pin before we tweak it */ - ulong gpio = port_base + pin; - gpio_request(gpio, "cmd_gpio"); - - /* finally, let's do it: set direction and exec command */ - ulong value; - if (sub_cmd == GPIO_INPUT) { - gpio_direction_input(gpio); - value = gpio_get_value(gpio); - } else { - switch (sub_cmd) { - case GPIO_SET: value = 1; break; - case GPIO_CLEAR: value = 0; break; - case GPIO_TOGGLE: value = !gpio_get_value(gpio); break; - default: goto show_usage; - } - gpio_direction_output(gpio, value); - } - printf("gpio: pin %lu on port %c (gpio %lu) value is %lu\n", - pin, *str_pin, gpio, value); - - gpio_free(gpio); - - return value; -} - -U_BOOT_CMD(gpio, 3, 0, do_gpio, - "input/set/clear/toggle gpio output pins", - "<input|set|clear|toggle> <port><pin>\n" - " - input/set/clear/toggle the specified pin (e.g. PF10)"); diff --git a/arch/blackfin/cpu/cpu.h b/arch/blackfin/cpu/cpu.h index ba85e0b9a5..e70560f4de 100644 --- a/arch/blackfin/cpu/cpu.h +++ b/arch/blackfin/cpu/cpu.h @@ -28,7 +28,6 @@ #include <command.h> void board_reset(void) __attribute__((__weak__)); -void bfin_reset_or_hang(void) __attribute__((__noreturn__)); void bfin_dump(struct pt_regs *reg); void bfin_panic(struct pt_regs *reg); void dump(struct pt_regs *regs); diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index 488ca11bb0..cb96721cf4 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -45,7 +45,7 @@ static struct gpio_port_t * const gpio_array[] = { #if defined(BF533_FAMILY) (struct gpio_port_t *) FIO_FLAG_D, #elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \ - || defined(BF538_FAMILY) + || defined(BF538_FAMILY) || defined(CONFIG_BF50x) (struct gpio_port_t *) PORTFIO, # if !defined(BF538_FAMILY) (struct gpio_port_t *) PORTGIO, @@ -71,7 +71,8 @@ static struct gpio_port_t * const gpio_array[] = { #endif }; -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) +#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \ + defined(CONFIG_BF50x) static unsigned short * const port_fer[] = { (unsigned short *) PORTF_FER, (unsigned short *) PORTG_FER, @@ -202,7 +203,8 @@ static void port_setup(unsigned gpio, unsigned short usage) if (check_gpio(gpio)) return; -#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) +#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \ + defined(CONFIG_BF50x) if (usage == GPIO_USAGE) *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); else diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 433d477ddf..750add06bc 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -341,13 +341,13 @@ maybe_self_refresh(ADI_BOOT_DATA *bs) return false; /* If external memory is enabled, put it into self refresh first. */ -#ifdef EBIU_RSTCTL +#if defined(EBIU_RSTCTL) if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) { serial_putc('b'); bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ); return true; } -#else +#elif defined(EBIU_SDGCTL) if (bfin_read_EBIU_SDBCTL() & EBE) { serial_putc('b'); bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); @@ -373,12 +373,15 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs) /* If we're entering self refresh, make sure it has happened. */ if (put_into_srfs) -#ifdef EBIU_RSTCTL +#if defined(EBIU_RSTCTL) while (!(bfin_read_EBIU_RSTCTL() & SRACK)) -#else + continue; +#elif defined(EBIU_SDGCTL) while (!(bfin_read_EBIU_SDSTAT() & SDSRA)) -#endif continue; +#else + ; +#endif serial_putc('c'); @@ -536,7 +539,7 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) /* Program the external memory controller before we come out of * self-refresh. This only works with our SDRAM controller. */ -#ifndef EBIU_RSTCTL +#ifdef EBIU_SDGCTL # ifdef CONFIG_EBIU_SDRRC_VAL bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL); # endif @@ -552,9 +555,9 @@ program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs) /* Now that we've reprogrammed, take things out of self refresh. */ if (put_into_srfs) -#ifdef EBIU_RSTCTL +#if defined(EBIU_RSTCTL) bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); -#else +#elif defined(EBIU_SDGCTL) bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS)); #endif @@ -646,10 +649,10 @@ program_async_controller(ADI_BOOT_DATA *bs) serial_putc('b'); /* Not all parts have these additional MMRs. */ -#ifdef EBIU_MODE -# ifdef CONFIG_EBIU_MBSCTL_VAL +#ifdef EBIU_MBSCTL bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); -# endif +#endif +#ifdef EBIU_MODE # ifdef CONFIG_EBIU_MODE_VAL bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); # endif diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c index 164afde331..9307e9f9e2 100644 --- a/arch/blackfin/cpu/reset.c +++ b/arch/blackfin/cpu/reset.c @@ -80,27 +80,11 @@ static void bfin_reset(void) * PC relative call with a 25 bit immediate. This is not enough * to get us from the top of SDRAM into L1. */ -__attribute__ ((__noreturn__)) -static inline void bfin_reset_trampoline(void) +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (board_reset) board_reset(); while (1) asm("jump (%0);" : : "a" (bfin_reset)); -} - -__attribute__ ((__noreturn__)) -void bfin_reset_or_hang(void) -{ -#ifdef CONFIG_PANIC_HANG - hang(); -#else - bfin_reset_trampoline(); -#endif -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - bfin_reset_trampoline(); return 0; } diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h index f9e311f3ee..7999a19333 100644 --- a/arch/blackfin/cpu/serial.h +++ b/arch/blackfin/cpu/serial.h @@ -31,13 +31,19 @@ #define LOB(x) ((x) & 0xFF) #define HIB(x) (((x) >> 8) & 0xFF) +#if defined(__ADSPBF50x__) || defined(__ADSPBF54x__) +# define BFIN_UART_HW_VER 2 +#else +# define BFIN_UART_HW_VER 1 +#endif + /* * All Blackfin system MMRs are padded to 32bits even if the register * itself is only 16bits. So use a helper macro to streamline this. */ #define __BFP(m) u16 m; u16 __pad_##m struct bfin_mmr_serial { -#ifdef __ADSPBF54x__ +#if BFIN_UART_HW_VER == 2 __BFP(dll); __BFP(dlh); __BFP(gctl); @@ -74,25 +80,21 @@ struct bfin_mmr_serial { }; #undef __BFP -#ifndef UART_LSR -# if (CONFIG_UART_CONSOLE == 3) -# define UART_BASE UART3_DLL -# elif (CONFIG_UART_CONSOLE == 2) -# define UART_BASE UART2_DLL -# elif (CONFIG_UART_CONSOLE == 1) -# define UART_BASE UART1_DLL -# elif (CONFIG_UART_CONSOLE == 0) -# define UART_BASE UART0_DLL -# endif +#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx +#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx) +#define MMR_UART(mmr) _PASTE_UART(CONFIG_UART_CONSOLE, UART, DLL) +#define P_UART(pin) _PASTE_UART(CONFIG_UART_CONSOLE, P_UART, pin) + +#ifndef UART_DLL +# define UART_DLL MMR_UART(DLL) #else # if CONFIG_UART_CONSOLE != 0 # error CONFIG_UART_CONSOLE must be 0 on parts with only one UART # endif -# define UART_BASE UART_DLL #endif -#define pUART ((volatile struct bfin_mmr_serial *)UART_BASE) +#define pUART ((volatile struct bfin_mmr_serial *)UART_DLL) -#ifdef __ADSPBF54x__ +#if BFIN_UART_HW_VER == 2 # define ACCESS_LATCH() # define ACCESS_PORT_IER() #else @@ -106,23 +108,21 @@ __attribute__((always_inline)) static inline void serial_do_portmux(void) { if (!BFIN_DEBUG_EARLY_SERIAL) { - const unsigned short pins[] = { -#if CONFIG_UART_CONSOLE == 0 - P_UART0_TX, P_UART0_RX, -#elif CONFIG_UART_CONSOLE == 1 - P_UART1_TX, P_UART1_RX, -#elif CONFIG_UART_CONSOLE == 2 - P_UART2_TX, P_UART2_RX, -#elif CONFIG_UART_CONSOLE == 3 - P_UART3_TX, P_UART3_RX, -#endif - 0, - }; + const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, }; peripheral_request_list(pins, "bfin-uart"); return; } -#if defined(__ADSPBF51x__) +#if defined(__ADSPBF50x__) +# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ + bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_1 | PORT_x_MUX_##mux_rx##_FUNC_1); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + switch (CONFIG_UART_CONSOLE) { + case 0: DO_MUX(G, 7, 7, 12, 13); break; /* Port G; mux 7; PG12 and PG13 */ + case 1: DO_MUX(F, 3, 3, 6, 7); break; /* Port F; mux 3; PF6 and PF7 */ + } + SSYNC(); +#elif defined(__ADSPBF51x__) # define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \ bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); @@ -141,13 +141,11 @@ static inline void serial_do_portmux(void) } SSYNC(); #elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) -# define DO_MUX(func, tx, rx) \ - bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~(func)); \ - bfin_write_PORTF_FER(bfin_read_PORTF_FER() | PF##tx | PF##rx); - switch (CONFIG_UART_CONSOLE) { - case 0: DO_MUX(PFDE, 0, 1); break; - case 1: DO_MUX(PFTE, 2, 3); break; - } + const uint16_t func[] = { PFDE, PFTE, }; + bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]); + bfin_write_PORTF_FER(bfin_read_PORTF_FER() | + (1 << P_IDENT(P_UART(RX))) | + (1 << P_IDENT(P_UART(TX)))); SSYNC(); #elif defined(__ADSPBF54x__) # define DO_MUX(port, tx, rx) \ @@ -160,6 +158,12 @@ static inline void serial_do_portmux(void) case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */ } SSYNC(); +#elif defined(__ADSPBF561__) + /* UART pins could be GPIO, but they aren't pin muxed. */ +#else +# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) +# error "missing portmux logic for UART" +# endif #endif } diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index 7a3abba21c..15ecb1e8eb 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -52,6 +52,19 @@ ENTRY(_start) sp.l = LO(L1_SRAM_SCRATCH_END - 20); sp.h = HI(L1_SRAM_SCRATCH_END - 20); + /* Optimization register tricks: keep a base value in the + * reserved P registers so we use the load/store with an + * offset syntax. R0 = [P5 + <constant>]; + * P4 - system MMR base + * P5 - core MMR base + */ +#ifdef CONFIG_HW_WATCHDOG + p4.l = 0; + p4.h = HI(SYSMMR_BASE); +#endif + p5.l = 0; + p5.h = HI(COREMMR_BASE); + #ifdef CONFIG_HW_WATCHDOG # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START # define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000 @@ -60,13 +73,11 @@ ENTRY(_start) * That should be long enough to bootstrap ourselves up and * then the common u-boot code can take over. */ - P0.L = LO(WDOG_CNT); - P0.H = HI(WDOG_CNT); - R0.L = 0; - R0.H = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START)); - [P0] = R0; + r0 = 0; + r0.h = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START)); + [p4 + (WDOG_CNT - SYSMMR_BASE)] = r0; /* fire up the watchdog - R0.L above needs to be 0x0000 */ - W[P0 + (WDOG_CTL - WDOG_CNT)] = R0; + W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0; #endif /* Turn on the serial for debugging the init process */ @@ -121,6 +132,18 @@ ENTRY(_start) if cc jump .Lnorelocate; r6 = 0 (x); + /* Turn off caches as they require CPLBs and a CPLB miss requires + * a software exception handler to process it. But we're about to + * clobber any previous executing software (like U-Boot that just + * launched a new U-Boot via 'go'), so any handler state will be + * unreliable after the memcpy below. + */ + serial_early_puts("Kill Caches"); + r0 = 0; + [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r0; + [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r0; + ssync; + /* In bypass mode, we don't have an LDR with an init block * so we need to explicitly call it ourselves. This will * reprogram our clocks, memory, and setup our async banks. @@ -204,17 +227,15 @@ ENTRY(_start) serial_early_puts("Lower to 15"); r0 = r7; r1 = r6; - p0.l = LO(EVT15); - p0.h = HI(EVT15); p1.l = .Lenable_nested; p1.h = .Lenable_nested; - [p0] = p1; + [p5 + (EVT15 - COREMMR_BASE)] = p1; r7 = EVT_IVG15 (z); sti r7; raise 15; - p4.l = .LWAIT_HERE; - p4.h = .LWAIT_HERE; - reti = p4; + p3.l = .LWAIT_HERE; + p3.h = .LWAIT_HERE; + reti = p3; rti; /* Enable nested interrupts before continuing with cpu init */ diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c index 09388aa3d5..0cb833a0e4 100644 --- a/arch/blackfin/cpu/traps.c +++ b/arch/blackfin/cpu/traps.c @@ -426,5 +426,5 @@ void bfin_panic(struct pt_regs *regs) unsigned long tflags; trace_buffer_save(tflags); bfin_dump(regs); - bfin_reset_or_hang(); + panic("PANIC: Blackfin internal error"); } diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h index 952444ed09..a19f0f74e6 100644 --- a/arch/blackfin/include/asm/blackfin_cdef.h +++ b/arch/blackfin/include/asm/blackfin_cdef.h @@ -6,6 +6,12 @@ #ifndef __MACH_CDEF_BLACKFIN__ #define __MACH_CDEF_BLACKFIN__ +#ifdef __ADSPBF504__ +# include "mach-bf506/BF504_cdef.h" +#endif +#ifdef __ADSPBF506__ +# include "mach-bf506/BF506_cdef.h" +#endif #ifdef __ADSPBF512__ # include "mach-bf518/BF512_cdef.h" #endif diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h index 385966a00b..f06d1f12cc 100644 --- a/arch/blackfin/include/asm/blackfin_def.h +++ b/arch/blackfin/include/asm/blackfin_def.h @@ -6,6 +6,16 @@ #ifndef __MACH_DEF_BLACKFIN__ #define __MACH_DEF_BLACKFIN__ +#ifdef __ADSPBF504__ +# include "mach-bf506/BF504_def.h" +# include "mach-bf506/anomaly.h" +# include "mach-bf506/def_local.h" +#endif +#ifdef __ADSPBF506__ +# include "mach-bf506/BF506_def.h" +# include "mach-bf506/anomaly.h" +# include "mach-bf506/def_local.h" +#endif #ifdef __ADSPBF512__ # include "mach-bf518/BF512_def.h" # include "mach-bf518/anomaly.h" diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 04372525cc..89814cd585 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -12,6 +12,11 @@ /* Some of our defines use this (like CONFIG_SYS_GBL_DATA_ADDR) */ #include <asm-offsets.h> +/* Sanity check CONFIG_BFIN_CPU */ +#ifndef CONFIG_BFIN_CPU +# error CONFIG_BFIN_CPU: your board config needs to define this +#endif + #ifndef CONFIG_BFIN_SCRATCH_REG # define CONFIG_BFIN_SCRATCH_REG retn #endif @@ -104,8 +109,11 @@ #ifndef CONFIG_SYS_GBL_DATA_ADDR # define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE) #endif +#ifndef CONFIG_SYS_BD_INFO_ADDR +# define CONFIG_SYS_BD_INFO_ADDR (CONFIG_SYS_GBL_DATA_ADDR - GENERATED_BD_INFO_SIZE) +#endif #ifndef CONFIG_STACKBASE -# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4) +# define CONFIG_STACKBASE (CONFIG_SYS_BD_INFO_ADDR - 4) #endif #ifndef CONFIG_SYS_MEMTEST_START # define CONFIG_SYS_MEMTEST_START 0 diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index b650ef0800..9c0e5d1954 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -196,6 +196,59 @@ static inline int gpio_is_valid(int number) return number >= 0 && number < MAX_BLACKFIN_GPIOS; } +#include <linux/ctype.h> + +static inline int name_to_gpio(const char *name) +{ + int port_base; + + if (tolower(*name) == 'p') { + ++name; + + switch (tolower(*name)) { +#ifdef GPIO_PA0 + case 'a': port_base = GPIO_PA0; break; +#endif +#ifdef GPIO_PB0 + case 'b': port_base = GPIO_PB0; break; +#endif +#ifdef GPIO_PC0 + case 'c': port_base = GPIO_PC0; break; +#endif +#ifdef GPIO_PD0 + case 'd': port_base = GPIO_PD0; break; +#endif +#ifdef GPIO_PE0 + case 'e': port_base = GPIO_PE0; break; +#endif +#ifdef GPIO_PF0 + case 'f': port_base = GPIO_PF0; break; +#endif +#ifdef GPIO_PG0 + case 'g': port_base = GPIO_PG0; break; +#endif +#ifdef GPIO_PH0 + case 'h': port_base = GPIO_PH0; break; +#endif +#ifdef GPIO_PI0 + case 'i': port_base = GPIO_PI0; break; +#endif +#ifdef GPIO_PJ + case 'j': port_base = GPIO_PJ0; break; +#endif + default: return -1; + } + + ++name; + } else + port_base = 0; + + return port_base + simple_strtoul(name, NULL, 10); +} +#define name_to_gpio(n) name_to_gpio(n) + +#define gpio_status() bfin_gpio_labels() + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_BLACKFIN_GPIO_H__ */ diff --git a/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h b/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h new file mode 100644 index 0000000000..27864e5b3e --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/BF504_cdef.h @@ -0,0 +1,1782 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF504_proc__ +#define __BFIN_CDEF_ADSP_BF504_proc__ + +#include "../mach-common/ADSP-EDN-core_cdef.h" + +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) +#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) +#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) +#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) +#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) +#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) +#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) +#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) +#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) +#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) +#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) +#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) +#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) +#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) +#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) +#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) +#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) +#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) +#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) +#define bfin_read_PORTFIO() bfin_read16(PORTFIO) +#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) +#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) +#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) +#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) +#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) +#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) +#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) +#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) +#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) +#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) +#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) +#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) +#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) +#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) +#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) +#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) +#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) +#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) +#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) +#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) +#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) +#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) +#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) +#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) +#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) +#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) +#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) +#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) +#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) +#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) +#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) +#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) +#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_MODE() bfin_read16(EBIU_MODE) +#define bfin_write_EBIU_MODE(val) bfin_write16(EBIU_MODE, val) +#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL) +#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) +#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) +#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) +#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) +#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) +#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) +#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) +#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) +#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) +#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) +#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) +#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) +#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) +#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) +#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) +#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) +#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) +#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) +#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) +#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) +#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) +#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) +#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) +#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) +#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) +#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) +#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) +#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) +#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) +#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) +#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) +#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) +#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) +#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) +#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) +#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) +#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) +#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) +#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) +#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) +#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) +#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) +#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) +#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) +#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) +#define bfin_read_PORTGIO() bfin_read16(PORTGIO) +#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) +#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) +#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) +#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) +#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) +#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) +#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) +#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) +#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) +#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) +#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) +#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) +#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) +#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) +#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) +#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) +#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) +#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) +#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) +#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) +#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) +#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) +#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) +#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) +#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) +#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) +#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) +#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) +#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) +#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) +#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) +#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) +#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) +#define bfin_read_PORTHIO() bfin_read16(PORTHIO) +#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) +#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) +#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) +#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) +#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) +#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) +#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) +#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) +#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) +#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) +#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) +#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) +#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) +#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) +#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) +#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) +#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) +#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) +#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) +#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) +#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) +#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) +#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) +#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) +#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) +#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) +#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) +#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) +#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) +#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) +#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) +#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) +#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) +#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) +#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) +#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) +#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) +#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) +#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) +#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) +#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val) +#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) +#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val) +#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) +#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val) +#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) +#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val) +#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) +#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val) +#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) +#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val) +#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) +#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val) +#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) +#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val) +#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) +#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val) +#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) +#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val) +#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) +#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val) +#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) +#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val) +#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) +#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val) +#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) +#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val) +#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) +#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val) +#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) +#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val) +#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) +#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val) +#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) +#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val) +#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) +#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val) +#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) +#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val) +#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) +#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val) +#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) +#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val) +#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) +#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val) +#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) +#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val) +#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) +#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val) +#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) +#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val) +#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) +#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val) +#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) +#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val) +#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) +#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val) +#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) +#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val) +#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) +#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val) +#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) +#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val) +#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) +#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val) +#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) +#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val) +#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) +#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val) +#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION) +#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val) +#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) +#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val) +#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) +#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val) +#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) +#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val) +#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) +#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val) +#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) +#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val) +#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) +#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val) +#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) +#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val) +#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2) +#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val) +#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) +#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val) +#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) +#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val) +#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) +#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val) +#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) +#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val) +#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) +#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val) +#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) +#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val) +#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) +#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val) +#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) +#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val) +#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) +#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val) +#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) +#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val) +#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) +#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val) +#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) +#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val) +#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) +#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val) +#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) +#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val) +#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) +#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val) +#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) +#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val) +#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) +#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val) +#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) +#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val) +#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) +#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val) +#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) +#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val) +#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) +#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val) +#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) +#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val) +#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) +#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val) +#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) +#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val) +#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) +#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val) +#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) +#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val) +#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) +#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val) +#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) +#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val) +#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) +#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val) +#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) +#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val) +#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) +#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val) +#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) +#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val) +#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) +#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val) +#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) +#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val) +#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) +#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val) +#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) +#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val) +#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) +#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val) +#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) +#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val) +#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) +#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val) +#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) +#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val) +#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) +#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val) +#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) +#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val) +#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) +#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val) +#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) +#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val) +#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) +#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val) +#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) +#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val) +#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) +#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val) +#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) +#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val) +#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) +#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val) +#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) +#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val) +#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) +#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val) +#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) +#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val) +#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) +#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val) +#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) +#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val) +#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) +#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val) +#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) +#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val) +#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) +#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val) +#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) +#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val) +#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) +#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val) +#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) +#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val) +#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) +#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val) +#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) +#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val) +#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) +#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val) +#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) +#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val) +#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) +#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val) +#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) +#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val) +#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) +#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val) +#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) +#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val) +#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) +#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val) +#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) +#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val) +#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) +#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val) +#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) +#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val) +#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) +#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val) +#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) +#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val) +#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) +#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val) +#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) +#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val) +#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) +#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val) +#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) +#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val) +#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) +#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val) +#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) +#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val) +#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) +#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val) +#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) +#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val) +#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) +#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val) +#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) +#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val) +#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) +#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val) +#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) +#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val) +#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) +#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val) +#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) +#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val) +#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) +#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val) +#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) +#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val) +#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) +#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val) +#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) +#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val) +#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) +#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val) +#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) +#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val) +#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) +#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val) +#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) +#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val) +#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) +#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val) +#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) +#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val) +#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) +#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val) +#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) +#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val) +#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) +#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val) +#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) +#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val) +#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) +#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val) +#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) +#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val) +#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) +#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val) +#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) +#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val) +#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) +#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val) +#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) +#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val) +#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) +#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val) +#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) +#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val) +#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) +#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val) +#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) +#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val) +#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) +#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val) +#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) +#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val) +#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) +#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val) +#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) +#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val) +#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) +#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val) +#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) +#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val) +#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) +#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val) +#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) +#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val) +#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) +#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val) +#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) +#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val) +#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) +#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val) +#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) +#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val) +#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) +#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val) +#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) +#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val) +#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) +#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val) +#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) +#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val) +#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) +#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val) +#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) +#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val) +#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) +#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val) +#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) +#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val) +#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) +#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val) +#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) +#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val) +#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) +#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val) +#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) +#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val) +#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) +#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val) +#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) +#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val) +#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) +#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val) +#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) +#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val) +#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) +#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val) +#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) +#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val) +#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) +#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val) +#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) +#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val) +#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) +#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val) +#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) +#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val) +#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) +#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val) +#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) +#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val) +#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) +#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val) +#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) +#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val) +#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) +#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val) +#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) +#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val) +#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) +#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val) +#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) +#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val) +#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) +#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val) +#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) +#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val) +#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) +#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val) +#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) +#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val) +#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) +#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val) +#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) +#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val) +#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) +#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val) +#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) +#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val) +#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) +#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val) +#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) +#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val) +#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) +#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val) +#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) +#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val) +#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) +#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val) +#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) +#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val) +#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) +#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val) +#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) +#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val) +#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) +#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val) +#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) +#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val) +#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) +#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val) +#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) +#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val) +#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) +#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val) +#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) +#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val) +#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) +#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val) +#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) +#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val) +#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) +#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val) +#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) +#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val) +#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) +#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val) +#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) +#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val) +#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) +#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val) +#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) +#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val) +#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) +#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val) +#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) +#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val) +#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) +#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val) +#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) +#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val) +#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) +#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val) +#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) +#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val) +#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) +#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val) +#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) +#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val) +#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) +#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val) +#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) +#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val) +#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) +#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val) +#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) +#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val) +#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) +#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val) +#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) +#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val) +#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) +#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val) +#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) +#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val) +#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) +#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val) +#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) +#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val) +#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) +#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val) +#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) +#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val) +#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) +#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val) +#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) +#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val) +#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) +#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val) +#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) +#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val) +#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) +#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val) +#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) +#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val) +#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) +#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val) +#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) +#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val) +#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) +#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val) +#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) +#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val) +#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) +#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val) +#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) +#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val) +#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) +#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val) +#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) +#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val) +#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) +#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val) +#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) +#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val) +#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) +#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val) +#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) +#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val) +#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) +#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val) +#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) +#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val) +#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) +#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val) +#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) +#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val) +#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) +#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val) +#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) +#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val) +#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) +#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val) +#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) +#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val) +#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) +#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val) +#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) +#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val) +#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) +#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val) +#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) +#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val) +#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) +#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val) +#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) +#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val) +#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) +#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val) +#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) +#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val) +#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) +#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val) +#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) +#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val) +#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) +#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val) +#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) +#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val) +#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) +#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val) +#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) +#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val) +#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) +#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val) +#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) +#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val) +#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) +#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val) +#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) +#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val) +#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) +#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val) +#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) +#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val) +#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) +#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val) +#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) +#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val) +#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) +#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val) +#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) +#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val) +#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) +#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val) +#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) +#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val) +#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) +#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val) +#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) +#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val) +#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) +#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val) +#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) +#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val) +#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) +#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val) +#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) +#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val) +#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) +#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val) +#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) +#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val) +#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) +#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val) +#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) +#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val) +#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) +#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val) +#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) +#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val) +#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) +#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val) +#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) +#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val) +#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) +#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val) +#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) +#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val) +#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) +#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val) +#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) +#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val) +#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) +#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val) +#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) +#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val) +#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) +#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val) +#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) +#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val) +#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) +#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val) +#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) +#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val) +#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) +#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val) +#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) +#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val) +#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) +#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val) +#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) +#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val) +#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) +#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val) +#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) +#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val) +#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) +#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val) +#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) +#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val) +#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) +#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val) +#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) +#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val) +#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) +#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val) +#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) +#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val) +#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) +#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val) +#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) +#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val) +#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) +#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val) +#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) +#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val) +#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) +#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val) +#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) +#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val) +#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) +#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val) +#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) +#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val) +#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) +#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val) +#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) +#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val) +#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) +#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val) +#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) +#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val) +#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) +#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val) +#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) +#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val) +#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) +#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val) +#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) +#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val) +#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) +#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val) +#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) +#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val) +#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) +#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val) +#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) +#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val) +#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) +#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val) +#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) +#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val) +#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) +#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val) +#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) +#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val) +#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) +#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val) +#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) +#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val) +#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) +#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val) +#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) +#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) +#define bfin_read_PWM1_CTRL() bfin_read16(PWM1_CTRL) +#define bfin_write_PWM1_CTRL(val) bfin_write16(PWM1_CTRL, val) +#define bfin_read_PWM1_STAT() bfin_read16(PWM1_STAT) +#define bfin_write_PWM1_STAT(val) bfin_write16(PWM1_STAT, val) +#define bfin_read_PWM1_TM() bfin_read16(PWM1_TM) +#define bfin_write_PWM1_TM(val) bfin_write16(PWM1_TM, val) +#define bfin_read_PWM1_DT() bfin_read16(PWM1_DT) +#define bfin_write_PWM1_DT(val) bfin_write16(PWM1_DT, val) +#define bfin_read_PWM1_GATE() bfin_read16(PWM1_GATE) +#define bfin_write_PWM1_GATE(val) bfin_write16(PWM1_GATE, val) +#define bfin_read_PWM1_CHA() bfin_read16(PWM1_CHA) +#define bfin_write_PWM1_CHA(val) bfin_write16(PWM1_CHA, val) +#define bfin_read_PWM1_CHB() bfin_read16(PWM1_CHB) +#define bfin_write_PWM1_CHB(val) bfin_write16(PWM1_CHB, val) +#define bfin_read_PWM1_CHC() bfin_read16(PWM1_CHC) +#define bfin_write_PWM1_CHC(val) bfin_write16(PWM1_CHC, val) +#define bfin_read_PWM1_SEG() bfin_read16(PWM1_SEG) +#define bfin_write_PWM1_SEG(val) bfin_write16(PWM1_SEG, val) +#define bfin_read_PWM1_SYNCWT() bfin_read16(PWM1_SYNCWT) +#define bfin_write_PWM1_SYNCWT(val) bfin_write16(PWM1_SYNCWT, val) +#define bfin_read_PWM1_CHAL() bfin_read16(PWM1_CHAL) +#define bfin_write_PWM1_CHAL(val) bfin_write16(PWM1_CHAL, val) +#define bfin_read_PWM1_CHBL() bfin_read16(PWM1_CHBL) +#define bfin_write_PWM1_CHBL(val) bfin_write16(PWM1_CHBL, val) +#define bfin_read_PWM1_CHCL() bfin_read16(PWM1_CHCL) +#define bfin_write_PWM1_CHCL(val) bfin_write16(PWM1_CHCL, val) +#define bfin_read_PWM1_LSI() bfin_read16(PWM1_LSI) +#define bfin_write_PWM1_LSI(val) bfin_write16(PWM1_LSI, val) +#define bfin_read_PWM1_STAT2() bfin_read16(PWM1_STAT2) +#define bfin_write_PWM1_STAT2(val) bfin_write16(PWM1_STAT2, val) +#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) +#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) +#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) +#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) +#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) +#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) +#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) +#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) +#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) +#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) +#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) +#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) +#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) +#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) +#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) +#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) +#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) +#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) +#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) +#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) +#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) +#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) +#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) +#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) +#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE) +#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val) +#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS) +#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val) +#define bfin_read_FLASH_CONTROL() bfin_read16(FLASH_CONTROL) +#define bfin_write_FLASH_CONTROL(val) bfin_write16(FLASH_CONTROL, val) +#define bfin_read_FLASH_CONTROL_SET() bfin_read16(FLASH_CONTROL_SET) +#define bfin_write_FLASH_CONTROL_SET(val) bfin_write16(FLASH_CONTROL_SET, val) +#define bfin_read_FLASH_CONTROL_CLEAR() bfin_read16(FLASH_CONTROL_CLEAR) +#define bfin_write_FLASH_CONTROL_CLEAR(val) bfin_write16(FLASH_CONTROL_CLEAR, val) +#define bfin_read_CNT1_CONFIG() bfin_read16(CNT1_CONFIG) +#define bfin_write_CNT1_CONFIG(val) bfin_write16(CNT1_CONFIG, val) +#define bfin_read_CNT1_IMASK() bfin_read16(CNT1_IMASK) +#define bfin_write_CNT1_IMASK(val) bfin_write16(CNT1_IMASK, val) +#define bfin_read_CNT1_STATUS() bfin_read16(CNT1_STATUS) +#define bfin_write_CNT1_STATUS(val) bfin_write16(CNT1_STATUS, val) +#define bfin_read_CNT1_COMMAND() bfin_read16(CNT1_COMMAND) +#define bfin_write_CNT1_COMMAND(val) bfin_write16(CNT1_COMMAND, val) +#define bfin_read_CNT1_DEBOUNCE() bfin_read16(CNT1_DEBOUNCE) +#define bfin_write_CNT1_DEBOUNCE(val) bfin_write16(CNT1_DEBOUNCE, val) +#define bfin_read_CNT1_COUNTER() bfin_read32(CNT1_COUNTER) +#define bfin_write_CNT1_COUNTER(val) bfin_write32(CNT1_COUNTER, val) +#define bfin_read_CNT1_MAX() bfin_read32(CNT1_MAX) +#define bfin_write_CNT1_MAX(val) bfin_write32(CNT1_MAX, val) +#define bfin_read_CNT1_MIN() bfin_read32(CNT1_MIN) +#define bfin_write_CNT1_MIN(val) bfin_write32(CNT1_MIN, val) +#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) +#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) +#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) +#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) +#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) +#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) +#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) +#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) +#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) +#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) +#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) +#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) +#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) +#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) +#define bfin_read_CNT0_CONFIG() bfin_read16(CNT0_CONFIG) +#define bfin_write_CNT0_CONFIG(val) bfin_write16(CNT0_CONFIG, val) +#define bfin_read_CNT0_IMASK() bfin_read16(CNT0_IMASK) +#define bfin_write_CNT0_IMASK(val) bfin_write16(CNT0_IMASK, val) +#define bfin_read_CNT0_STATUS() bfin_read16(CNT0_STATUS) +#define bfin_write_CNT0_STATUS(val) bfin_write16(CNT0_STATUS, val) +#define bfin_read_CNT0_COMMAND() bfin_read16(CNT0_COMMAND) +#define bfin_write_CNT0_COMMAND(val) bfin_write16(CNT0_COMMAND, val) +#define bfin_read_CNT0_DEBOUNCE() bfin_read16(CNT0_DEBOUNCE) +#define bfin_write_CNT0_DEBOUNCE(val) bfin_write16(CNT0_DEBOUNCE, val) +#define bfin_read_CNT0_COUNTER() bfin_read32(CNT0_COUNTER) +#define bfin_write_CNT0_COUNTER(val) bfin_write32(CNT0_COUNTER, val) +#define bfin_read_CNT0_MAX() bfin_read32(CNT0_MAX) +#define bfin_write_CNT0_MAX(val) bfin_write32(CNT0_MAX, val) +#define bfin_read_CNT0_MIN() bfin_read32(CNT0_MIN) +#define bfin_write_CNT0_MIN(val) bfin_write32(CNT0_MIN, val) +#define bfin_read_PWM0_CTRL() bfin_read16(PWM0_CTRL) +#define bfin_write_PWM0_CTRL(val) bfin_write16(PWM0_CTRL, val) +#define bfin_read_PWM0_STAT() bfin_read16(PWM0_STAT) +#define bfin_write_PWM0_STAT(val) bfin_write16(PWM0_STAT, val) +#define bfin_read_PWM0_TM() bfin_read16(PWM0_TM) +#define bfin_write_PWM0_TM(val) bfin_write16(PWM0_TM, val) +#define bfin_read_PWM0_DT() bfin_read16(PWM0_DT) +#define bfin_write_PWM0_DT(val) bfin_write16(PWM0_DT, val) +#define bfin_read_PWM0_GATE() bfin_read16(PWM0_GATE) +#define bfin_write_PWM0_GATE(val) bfin_write16(PWM0_GATE, val) +#define bfin_read_PWM0_CHA() bfin_read16(PWM0_CHA) +#define bfin_write_PWM0_CHA(val) bfin_write16(PWM0_CHA, val) +#define bfin_read_PWM0_CHB() bfin_read16(PWM0_CHB) +#define bfin_write_PWM0_CHB(val) bfin_write16(PWM0_CHB, val) +#define bfin_read_PWM0_CHC() bfin_read16(PWM0_CHC) +#define bfin_write_PWM0_CHC(val) bfin_write16(PWM0_CHC, val) +#define bfin_read_PWM0_SEG() bfin_read16(PWM0_SEG) +#define bfin_write_PWM0_SEG(val) bfin_write16(PWM0_SEG, val) +#define bfin_read_PWM0_SYNCWT() bfin_read16(PWM0_SYNCWT) +#define bfin_write_PWM0_SYNCWT(val) bfin_write16(PWM0_SYNCWT, val) +#define bfin_read_PWM0_CHAL() bfin_read16(PWM0_CHAL) +#define bfin_write_PWM0_CHAL(val) bfin_write16(PWM0_CHAL, val) +#define bfin_read_PWM0_CHBL() bfin_read16(PWM0_CHBL) +#define bfin_write_PWM0_CHBL(val) bfin_write16(PWM0_CHBL, val) +#define bfin_read_PWM0_CHCL() bfin_read16(PWM0_CHCL) +#define bfin_write_PWM0_CHCL(val) bfin_write16(PWM0_CHCL, val) +#define bfin_read_PWM0_LSI() bfin_read16(PWM0_LSI) +#define bfin_write_PWM0_LSI(val) bfin_write16(PWM0_LSI, val) +#define bfin_read_PWM0_STAT2() bfin_read16(PWM0_STAT2) +#define bfin_write_PWM0_STAT2(val) bfin_write16(PWM0_STAT2, val) +#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL) +#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val) +#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL) +#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val) +#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) +#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) +#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) +#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) +#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) +#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) +#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) +#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) +#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) +#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) +#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) +#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) +#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) +#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) +#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) +#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) +#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) +#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) +#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL) +#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val) +#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) +#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) +#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) +#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) +#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL) +#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val) +#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) +#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) +#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) +#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) +#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) +#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) +#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL) +#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val) +#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) +#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) +#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT) +#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val) +#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK) +#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val) +#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG) +#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val) +#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) +#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) +#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) +#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) +#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) +#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) +#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) +#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) +#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) +#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) +#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) +#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) +#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) +#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) + +#endif /* __BFIN_CDEF_ADSP_BF504_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf506/BF504_def.h b/arch/blackfin/include/asm/mach-bf506/BF504_def.h new file mode 100644 index 0000000000..8b0345f313 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/BF504_def.h @@ -0,0 +1,944 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF504_proc__ +#define __BFIN_DEF_ADSP_BF504_proc__ + +#include "../mach-common/ADSP-EDN-core_def.h" + +#define PLL_CTL 0xFFC00000 /* PLL Control Register */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ +#define PLL_STAT 0xFFC0000C /* PLL Status Register */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ +#define CHIPID 0xFFC00014 +#define SWRST 0xFFC00100 /* Software Reset Register */ +#define SYSCR 0xFFC00104 /* System Configuration register */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ +#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ +#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ +#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ +#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ +#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ +#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */ +#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ +#define UART0_DLL 0xFFC00400 /* Divisor Latch Low Byte */ +#define UART0_DLH 0xFFC00404 /* Divisor Latch High Byte */ +#define UART0_GCTL 0xFFC00408 /* Global Control Register */ +#define UART0_LCR 0xFFC0040C /* Line Control Register */ +#define UART0_MCR 0xFFC00410 /* Modem Control Register */ +#define UART0_LSR 0xFFC00414 /* Line Status Register */ +#define UART0_MSR 0xFFC00418 /* Modem Status Register */ +#define UART0_SCR 0xFFC0041C /* Scratch Register */ +#define UART0_IER_SET 0xFFC00420 /* Interrupt Enable Register Set */ +#define UART0_IER_CLEAR 0xFFC00424 /* Interrupt Enable Register Clear */ +#define UART0_THR 0xFFC00428 /* Transmit Hold Register */ +#define UART0_RBR 0xFFC0042C /* Receive Buffer Register */ +#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ +#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ +#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ +#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ +#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ +#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ +#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ +#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ +#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ +#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ +#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ +#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ +#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ +#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ +#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ +#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ +#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ +#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ +#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ +#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ +#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ +#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ +#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ +#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ +#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ +#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ +#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ +#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ +#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ +#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ +#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ +#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ +#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ +#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ +#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ +#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ +#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ +#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ +#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ +#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ +#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ +#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ +#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ +#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ +#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ +#define EBIU_MODE 0xFFC00A20 /* Asynchronous Memory Mode Control Register */ +#define EBIU_FCTL 0xFFC00A24 /* Asynchronous Memory Parameter Control Register */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ +#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ +#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ +#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ +#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ +#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ +#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ +#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ +#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ +#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ +#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ +#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ +#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ +#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ +#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ +#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ +#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ +#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ +#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ +#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ +#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ +#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ +#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ +#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ +#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ +#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ +#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ +#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ +#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ +#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ +#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ +#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ +#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ +#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ +#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ +#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ +#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ +#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ +#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ +#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ +#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ +#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ +#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ +#define UART1_DLL 0xFFC02000 /* Divisor Latch Low Byte */ +#define UART1_DLH 0xFFC02004 /* Divisor Latch High Byte */ +#define UART1_GCTL 0xFFC02008 /* Global Control Register */ +#define UART1_LCR 0xFFC0200C /* Line Control Register */ +#define UART1_MCR 0xFFC02010 /* Modem Control Register */ +#define UART1_LSR 0xFFC02014 /* Line Status Register */ +#define UART1_MSR 0xFFC02018 /* Modem Status Register */ +#define UART1_SCR 0xFFC0201C /* Scratch Register */ +#define UART1_IER_SET 0xFFC02020 /* Interrupt Enable Register Set */ +#define UART1_IER_CLEAR 0xFFC02024 /* Interrupt Enable Register Clear */ +#define UART1_THR 0xFFC02028 /* Transmit Hold Register */ +#define UART1_RBR 0xFFC0202C /* Receive Buffer Register */ +#define CAN_MC1 0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */ +#define CAN_MD1 0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */ +#define CAN_TRS1 0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */ +#define CAN_TRR1 0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */ +#define CAN_TA1 0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */ +#define CAN_AA1 0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */ +#define CAN_RMP1 0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */ +#define CAN_RML1 0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */ +#define CAN_MBTIF1 0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ +#define CAN_MBRIF1 0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ +#define CAN_MBIM1 0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ +#define CAN_RFH1 0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ +#define CAN_OPSS1 0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ +#define CAN_MC2 0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */ +#define CAN_MD2 0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */ +#define CAN_TRS2 0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */ +#define CAN_TRR2 0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */ +#define CAN_TA2 0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */ +#define CAN_AA2 0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */ +#define CAN_RMP2 0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */ +#define CAN_RML2 0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */ +#define CAN_MBTIF2 0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ +#define CAN_MBRIF2 0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ +#define CAN_MBIM2 0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ +#define CAN_RFH2 0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ +#define CAN_OPSS2 0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ +#define CAN_CLOCK 0xFFC02A80 /* CAN Controller 0 Clock Register */ +#define CAN_TIMING 0xFFC02A84 /* CAN Controller 0 Timing Register */ +#define CAN_DEBUG 0xFFC02A88 /* CAN Controller 0 Debug Register */ +#define CAN_STATUS 0xFFC02A8C /* CAN Controller 0 Global Status Register */ +#define CAN_CEC 0xFFC02A90 /* CAN Controller 0 Error Counter Register */ +#define CAN_GIS 0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */ +#define CAN_GIM 0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */ +#define CAN_GIF 0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */ +#define CAN_CONTROL 0xFFC02AA0 /* CAN Controller 0 Master Control Register */ +#define CAN_INTR 0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */ +#define CAN_MBTD 0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */ +#define CAN_EWR 0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */ +#define CAN_ESR 0xFFC02AB4 /* CAN Controller 0 Error Status Register */ +#define CAN_UCCNT 0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */ +#define CAN_UCRC 0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */ +#define CAN_UCCNF 0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */ +#define CAN_AM00L 0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ +#define CAN_AM00H 0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ +#define CAN_AM01L 0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ +#define CAN_AM01H 0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ +#define CAN_AM02L 0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ +#define CAN_AM02H 0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ +#define CAN_AM03L 0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ +#define CAN_AM03H 0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ +#define CAN_AM04L 0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ +#define CAN_AM04H 0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ +#define CAN_AM05L 0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ +#define CAN_AM05H 0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ +#define CAN_AM06L 0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ +#define CAN_AM06H 0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ +#define CAN_AM07L 0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ +#define CAN_AM07H 0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ +#define CAN_AM08L 0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ +#define CAN_AM08H 0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ +#define CAN_AM09L 0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ +#define CAN_AM09H 0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ +#define CAN_AM10L 0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ +#define CAN_AM10H 0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ +#define CAN_AM11L 0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ +#define CAN_AM11H 0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ +#define CAN_AM12L 0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ +#define CAN_AM12H 0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ +#define CAN_AM13L 0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ +#define CAN_AM13H 0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ +#define CAN_AM14L 0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ +#define CAN_AM14H 0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ +#define CAN_AM15L 0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ +#define CAN_AM15H 0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ +#define CAN_AM16L 0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ +#define CAN_AM16H 0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ +#define CAN_AM17L 0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ +#define CAN_AM17H 0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ +#define CAN_AM18L 0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ +#define CAN_AM18H 0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ +#define CAN_AM19L 0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ +#define CAN_AM19H 0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ +#define CAN_AM20L 0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ +#define CAN_AM20H 0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ +#define CAN_AM21L 0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ +#define CAN_AM21H 0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ +#define CAN_AM22L 0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ +#define CAN_AM22H 0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ +#define CAN_AM23L 0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ +#define CAN_AM23H 0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ +#define CAN_AM24L 0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ +#define CAN_AM24H 0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ +#define CAN_AM25L 0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ +#define CAN_AM25H 0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ +#define CAN_AM26L 0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ +#define CAN_AM26H 0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ +#define CAN_AM27L 0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ +#define CAN_AM27H 0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ +#define CAN_AM28L 0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ +#define CAN_AM28H 0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ +#define CAN_AM29L 0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ +#define CAN_AM29H 0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ +#define CAN_AM30L 0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ +#define CAN_AM30H 0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ +#define CAN_AM31L 0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ +#define CAN_AM31H 0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ +#define CAN_MB00_DATA0 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */ +#define CAN_MB00_DATA1 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */ +#define CAN_MB00_DATA2 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */ +#define CAN_MB00_DATA3 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */ +#define CAN_MB00_LENGTH 0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */ +#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */ +#define CAN_MB00_ID0 0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */ +#define CAN_MB00_ID1 0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */ +#define CAN_MB01_DATA0 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */ +#define CAN_MB01_DATA1 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */ +#define CAN_MB01_DATA2 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */ +#define CAN_MB01_DATA3 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */ +#define CAN_MB01_LENGTH 0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */ +#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */ +#define CAN_MB01_ID0 0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */ +#define CAN_MB01_ID1 0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */ +#define CAN_MB02_DATA0 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */ +#define CAN_MB02_DATA1 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */ +#define CAN_MB02_DATA2 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */ +#define CAN_MB02_DATA3 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */ +#define CAN_MB02_LENGTH 0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */ +#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */ +#define CAN_MB02_ID0 0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */ +#define CAN_MB02_ID1 0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */ +#define CAN_MB03_DATA0 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */ +#define CAN_MB03_DATA1 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */ +#define CAN_MB03_DATA2 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */ +#define CAN_MB03_DATA3 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */ +#define CAN_MB03_LENGTH 0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */ +#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */ +#define CAN_MB03_ID0 0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */ +#define CAN_MB03_ID1 0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */ +#define CAN_MB04_DATA0 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */ +#define CAN_MB04_DATA1 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */ +#define CAN_MB04_DATA2 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */ +#define CAN_MB04_DATA3 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */ +#define CAN_MB04_LENGTH 0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */ +#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */ +#define CAN_MB04_ID0 0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */ +#define CAN_MB04_ID1 0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */ +#define CAN_MB05_DATA0 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */ +#define CAN_MB05_DATA1 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */ +#define CAN_MB05_DATA2 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */ +#define CAN_MB05_DATA3 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */ +#define CAN_MB05_LENGTH 0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */ +#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */ +#define CAN_MB05_ID0 0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */ +#define CAN_MB05_ID1 0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */ +#define CAN_MB06_DATA0 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */ +#define CAN_MB06_DATA1 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */ +#define CAN_MB06_DATA2 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */ +#define CAN_MB06_DATA3 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */ +#define CAN_MB06_LENGTH 0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */ +#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */ +#define CAN_MB06_ID0 0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */ +#define CAN_MB06_ID1 0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */ +#define CAN_MB07_DATA0 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */ +#define CAN_MB07_DATA1 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */ +#define CAN_MB07_DATA2 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */ +#define CAN_MB07_DATA3 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */ +#define CAN_MB07_LENGTH 0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */ +#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */ +#define CAN_MB07_ID0 0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */ +#define CAN_MB07_ID1 0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */ +#define CAN_MB08_DATA0 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */ +#define CAN_MB08_DATA1 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */ +#define CAN_MB08_DATA2 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */ +#define CAN_MB08_DATA3 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */ +#define CAN_MB08_LENGTH 0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */ +#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */ +#define CAN_MB08_ID0 0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */ +#define CAN_MB08_ID1 0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */ +#define CAN_MB09_DATA0 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */ +#define CAN_MB09_DATA1 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */ +#define CAN_MB09_DATA2 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */ +#define CAN_MB09_DATA3 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */ +#define CAN_MB09_LENGTH 0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */ +#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */ +#define CAN_MB09_ID0 0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */ +#define CAN_MB09_ID1 0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */ +#define CAN_MB10_DATA0 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */ +#define CAN_MB10_DATA1 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */ +#define CAN_MB10_DATA2 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */ +#define CAN_MB10_DATA3 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */ +#define CAN_MB10_LENGTH 0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */ +#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */ +#define CAN_MB10_ID0 0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */ +#define CAN_MB10_ID1 0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */ +#define CAN_MB11_DATA0 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */ +#define CAN_MB11_DATA1 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */ +#define CAN_MB11_DATA2 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */ +#define CAN_MB11_DATA3 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */ +#define CAN_MB11_LENGTH 0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */ +#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */ +#define CAN_MB11_ID0 0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */ +#define CAN_MB11_ID1 0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */ +#define CAN_MB12_DATA0 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */ +#define CAN_MB12_DATA1 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */ +#define CAN_MB12_DATA2 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */ +#define CAN_MB12_DATA3 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */ +#define CAN_MB12_LENGTH 0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */ +#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */ +#define CAN_MB12_ID0 0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */ +#define CAN_MB12_ID1 0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */ +#define CAN_MB13_DATA0 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */ +#define CAN_MB13_DATA1 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */ +#define CAN_MB13_DATA2 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */ +#define CAN_MB13_DATA3 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */ +#define CAN_MB13_LENGTH 0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */ +#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */ +#define CAN_MB13_ID0 0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */ +#define CAN_MB13_ID1 0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */ +#define CAN_MB14_DATA0 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */ +#define CAN_MB14_DATA1 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */ +#define CAN_MB14_DATA2 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */ +#define CAN_MB14_DATA3 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */ +#define CAN_MB14_LENGTH 0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */ +#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */ +#define CAN_MB14_ID0 0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */ +#define CAN_MB14_ID1 0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */ +#define CAN_MB15_DATA0 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */ +#define CAN_MB15_DATA1 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */ +#define CAN_MB15_DATA2 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */ +#define CAN_MB15_DATA3 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */ +#define CAN_MB15_LENGTH 0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */ +#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */ +#define CAN_MB15_ID0 0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */ +#define CAN_MB15_ID1 0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */ +#define CAN_MB16_DATA0 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */ +#define CAN_MB16_DATA1 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */ +#define CAN_MB16_DATA2 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */ +#define CAN_MB16_DATA3 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */ +#define CAN_MB16_LENGTH 0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */ +#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */ +#define CAN_MB16_ID0 0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */ +#define CAN_MB16_ID1 0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */ +#define CAN_MB17_DATA0 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */ +#define CAN_MB17_DATA1 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */ +#define CAN_MB17_DATA2 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */ +#define CAN_MB17_DATA3 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */ +#define CAN_MB17_LENGTH 0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */ +#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */ +#define CAN_MB17_ID0 0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */ +#define CAN_MB17_ID1 0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */ +#define CAN_MB18_DATA0 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */ +#define CAN_MB18_DATA1 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */ +#define CAN_MB18_DATA2 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */ +#define CAN_MB18_DATA3 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */ +#define CAN_MB18_LENGTH 0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */ +#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */ +#define CAN_MB18_ID0 0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */ +#define CAN_MB18_ID1 0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */ +#define CAN_MB19_DATA0 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */ +#define CAN_MB19_DATA1 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */ +#define CAN_MB19_DATA2 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */ +#define CAN_MB19_DATA3 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */ +#define CAN_MB19_LENGTH 0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */ +#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */ +#define CAN_MB19_ID0 0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */ +#define CAN_MB19_ID1 0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */ +#define CAN_MB20_DATA0 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */ +#define CAN_MB20_DATA1 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */ +#define CAN_MB20_DATA2 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */ +#define CAN_MB20_DATA3 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */ +#define CAN_MB20_LENGTH 0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */ +#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */ +#define CAN_MB20_ID0 0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */ +#define CAN_MB20_ID1 0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */ +#define CAN_MB21_DATA0 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */ +#define CAN_MB21_DATA1 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */ +#define CAN_MB21_DATA2 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */ +#define CAN_MB21_DATA3 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */ +#define CAN_MB21_LENGTH 0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */ +#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */ +#define CAN_MB21_ID0 0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */ +#define CAN_MB21_ID1 0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */ +#define CAN_MB22_DATA0 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */ +#define CAN_MB22_DATA1 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */ +#define CAN_MB22_DATA2 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */ +#define CAN_MB22_DATA3 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */ +#define CAN_MB22_LENGTH 0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */ +#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */ +#define CAN_MB22_ID0 0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */ +#define CAN_MB22_ID1 0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */ +#define CAN_MB23_DATA0 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */ +#define CAN_MB23_DATA1 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */ +#define CAN_MB23_DATA2 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */ +#define CAN_MB23_DATA3 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */ +#define CAN_MB23_LENGTH 0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */ +#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */ +#define CAN_MB23_ID0 0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */ +#define CAN_MB23_ID1 0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */ +#define CAN_MB24_DATA0 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */ +#define CAN_MB24_DATA1 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */ +#define CAN_MB24_DATA2 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */ +#define CAN_MB24_DATA3 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */ +#define CAN_MB24_LENGTH 0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */ +#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */ +#define CAN_MB24_ID0 0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */ +#define CAN_MB24_ID1 0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */ +#define CAN_MB25_DATA0 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */ +#define CAN_MB25_DATA1 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */ +#define CAN_MB25_DATA2 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */ +#define CAN_MB25_DATA3 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */ +#define CAN_MB25_LENGTH 0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */ +#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */ +#define CAN_MB25_ID0 0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */ +#define CAN_MB25_ID1 0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */ +#define CAN_MB26_DATA0 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */ +#define CAN_MB26_DATA1 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */ +#define CAN_MB26_DATA2 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */ +#define CAN_MB26_DATA3 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */ +#define CAN_MB26_LENGTH 0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */ +#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */ +#define CAN_MB26_ID0 0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */ +#define CAN_MB26_ID1 0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */ +#define CAN_MB27_DATA0 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */ +#define CAN_MB27_DATA1 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */ +#define CAN_MB27_DATA2 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */ +#define CAN_MB27_DATA3 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */ +#define CAN_MB27_LENGTH 0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */ +#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */ +#define CAN_MB27_ID0 0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */ +#define CAN_MB27_ID1 0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */ +#define CAN_MB28_DATA0 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */ +#define CAN_MB28_DATA1 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */ +#define CAN_MB28_DATA2 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */ +#define CAN_MB28_DATA3 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */ +#define CAN_MB28_LENGTH 0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */ +#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */ +#define CAN_MB28_ID0 0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */ +#define CAN_MB28_ID1 0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */ +#define CAN_MB29_DATA0 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */ +#define CAN_MB29_DATA1 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */ +#define CAN_MB29_DATA2 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */ +#define CAN_MB29_DATA3 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */ +#define CAN_MB29_LENGTH 0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */ +#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */ +#define CAN_MB29_ID0 0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */ +#define CAN_MB29_ID1 0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */ +#define CAN_MB30_DATA0 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */ +#define CAN_MB30_DATA1 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */ +#define CAN_MB30_DATA2 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */ +#define CAN_MB30_DATA3 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */ +#define CAN_MB30_LENGTH 0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */ +#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */ +#define CAN_MB30_ID0 0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */ +#define CAN_MB30_ID1 0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */ +#define CAN_MB31_DATA0 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */ +#define CAN_MB31_DATA1 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */ +#define CAN_MB31_DATA2 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */ +#define CAN_MB31_DATA3 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */ +#define CAN_MB31_LENGTH 0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */ +#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */ +#define CAN_MB31_ID0 0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */ +#define CAN_MB31_ID1 0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */ +#define PWM1_CTRL 0xFFC03000 /* PWM1 Control Register */ +#define PWM1_STAT 0xFFC03004 /* PWM1 Status Register */ +#define PWM1_TM 0xFFC03008 /* PWM1 Period Register */ +#define PWM1_DT 0xFFC0300C /* PWM1 Dead Time Register */ +#define PWM1_GATE 0xFFC03010 /* PWM1 Chopping Control */ +#define PWM1_CHA 0xFFC03014 /* PWM1 Channel A Duty Control */ +#define PWM1_CHB 0xFFC03018 /* PWM1 Channel B Duty Control */ +#define PWM1_CHC 0xFFC0301C /* PWM1 Channel C Duty Control */ +#define PWM1_SEG 0xFFC03020 /* PWM1 Crossover and Output Enable */ +#define PWM1_SYNCWT 0xFFC03024 /* PWM1 Sync pulse width control */ +#define PWM1_CHAL 0xFFC03028 /* PWM1 Channel AL Duty Control (SR mode only) */ +#define PWM1_CHBL 0xFFC0302C /* PWM1 Channel BL Duty Control (SR mode only) */ +#define PWM1_CHCL 0xFFC03030 /* PWM1 Channel CL Duty Control (SR mode only) */ +#define PWM1_LSI 0xFFC03034 /* Low Side Invert (SR mode only) */ +#define PWM1_STAT2 0xFFC03038 /* PWM1 Status Register */ +#define ACM_CTL 0xFFC03100 /* ACM Control Register */ +#define ACM_TC0 0xFFC03104 /* ACM Timing Configuration 0 Register */ +#define ACM_TC1 0xFFC03108 /* ACM Timing Configuration 1 Register */ +#define ACM_STAT 0xFFC0310C /* ACM Status Register */ +#define ACM_ES 0xFFC03110 /* ACM Event Status Register */ +#define ACM_IMSK 0xFFC03114 /* ACM Interrupt Mask Register */ +#define ACM_MS 0xFFC03118 /* ACM Missed Event Status Register */ +#define ACM_EMSK 0xFFC0311C /* ACM Missed Event Interrupt Mask Register */ +#define ACM_ER0 0xFFC03120 /* ACM Event 0 Control Register */ +#define ACM_ER1 0xFFC03124 /* ACM Event 1 Control Register */ +#define ACM_ER2 0xFFC03128 /* ACM Event 2 Control Register */ +#define ACM_ER3 0xFFC0312C /* ACM Event 3 Control Register */ +#define ACM_ER4 0xFFC03130 /* ACM Event 4 Control Register */ +#define ACM_ER5 0xFFC03134 /* ACM Event 5 Control Register */ +#define ACM_ER6 0xFFC03138 /* ACM Event 6 Control Register */ +#define ACM_ER7 0xFFC0313C /* ACM Event 7 Control Register */ +#define ACM_ER8 0xFFC03140 /* ACM Event 8 Control Register */ +#define ACM_ER9 0xFFC03144 /* ACM Event 9 Control Register */ +#define ACM_ER10 0xFFC03148 /* ACM Event 10 Control Register */ +#define ACM_ER11 0xFFC0314C /* ACM Event 11 Control Register */ +#define ACM_ER12 0xFFC03150 /* ACM Event 12 Control Register */ +#define ACM_ER13 0xFFC03154 /* ACM Event 13 Control Register */ +#define ACM_ER14 0xFFC03158 /* ACM Event 14 Control Register */ +#define ACM_ER15 0xFFC0315C /* ACM Event 15 Control Register */ +#define ACM_ET0 0xFFC03180 /* ACM Event 0 Time Register */ +#define ACM_ET1 0xFFC03184 /* ACM Event 1 Time Register */ +#define ACM_ET2 0xFFC03188 /* ACM Event 2 Time Register */ +#define ACM_ET3 0xFFC0318C /* ACM Event 3 Time Register */ +#define ACM_ET4 0xFFC03190 /* ACM Event 4 Time Register */ +#define ACM_ET5 0xFFC03194 /* ACM Event 5 Time Register */ +#define ACM_ET6 0xFFC03198 /* ACM Event 6 Time Register */ +#define ACM_ET7 0xFFC0319C /* ACM Event 7 Time Register */ +#define ACM_ET8 0xFFC031A0 /* ACM Event 8 Time Register */ +#define ACM_ET9 0xFFC031A4 /* ACM Event 9 Time Register */ +#define ACM_ET10 0xFFC031A8 /* ACM Event 10 Time Register */ +#define ACM_ET11 0xFFC031AC /* ACM Event 11 Time Register */ +#define ACM_ET12 0xFFC031B0 /* ACM Event 12 Time Register */ +#define ACM_ET13 0xFFC031B4 /* ACM Event 13 Time Register */ +#define ACM_ET14 0xFFC031B8 /* ACM Event 14 Time Register */ +#define ACM_ET15 0xFFC031BC /* ACM Event 15 Time Register */ +#define ACM_TMR0 0xFFC031C0 /* ACM Timer 0 Registers */ +#define ACM_TMR1 0xFFC031C4 /* ACM Timer 1 Registers */ +#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ +#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ +#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ +#define PORTF_MUX 0xFFC03210 /* Port F mux control */ +#define PORTG_MUX 0xFFC03214 /* Port G mux control */ +#define PORTH_MUX 0xFFC03218 /* Port H mux control */ +#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ +#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ +#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ +#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ +#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ +#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ +#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */ +#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */ +#define FLASH_CONTROL 0xFFC0328C /* Stacked flash control register */ +#define FLASH_CONTROL_SET 0xFFC03290 /* Stacked flash control set register */ +#define FLASH_CONTROL_CLEAR 0xFFC03294 /* Stacked flash control clear register */ +#define CNT1_CONFIG 0xFFC03300 /* Counter 1 Configuration Register */ +#define CNT1_IMASK 0xFFC03304 /* Counter 1 Interrupt Mask Register */ +#define CNT1_STATUS 0xFFC03308 /* Counter 1 Status Register */ +#define CNT1_COMMAND 0xFFC0330C /* Counter 1 Command Register */ +#define CNT1_DEBOUNCE 0xFFC03310 /* Counter 1 Debounce Register */ +#define CNT1_COUNTER 0xFFC03314 /* Counter 1 Counter Register */ +#define CNT1_MAX 0xFFC03318 /* Counter 1 Boundry Value Register - max count */ +#define CNT1_MIN 0xFFC0331C /* Counter 1 Boundry Value Register - min count */ +#define SPI1_CTL 0xFFC03400 /* SPI1 Control */ +#define SPI1_FLG 0xFFC03404 /* SPI1 Flag Register */ +#define SPI1_STAT 0xFFC03408 /* SPI1 Status Register */ +#define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer */ +#define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer */ +#define SPI1_BAUD 0xFFC03414 /* SPI1 Baud Rate */ +#define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */ +#define CNT0_CONFIG 0xFFC03500 /* Configuration/Control Register */ +#define CNT0_IMASK 0xFFC03504 /* Interrupt Mask Register */ +#define CNT0_STATUS 0xFFC03508 /* Status Register */ +#define CNT0_COMMAND 0xFFC0350C /* Command Register */ +#define CNT0_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */ +#define CNT0_COUNTER 0xFFC03514 /* Counter Register */ +#define CNT0_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */ +#define CNT0_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */ +#define PWM0_CTRL 0xFFC03700 /* PWM Control Register */ +#define PWM0_STAT 0xFFC03704 /* PWM Status Register */ +#define PWM0_TM 0xFFC03708 /* PWM Period Register */ +#define PWM0_DT 0xFFC0370C /* PWM Dead Time Register */ +#define PWM0_GATE 0xFFC03710 /* PWM Chopping Control */ +#define PWM0_CHA 0xFFC03714 /* PWM Channel A Duty Control */ +#define PWM0_CHB 0xFFC03718 /* PWM Channel B Duty Control */ +#define PWM0_CHC 0xFFC0371C /* PWM Channel C Duty Control */ +#define PWM0_SEG 0xFFC03720 /* PWM Crossover and Output Enable */ +#define PWM0_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */ +#define PWM0_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */ +#define PWM0_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */ +#define PWM0_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */ +#define PWM0_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */ +#define PWM0_STAT2 0xFFC03738 /* PWM Status Register */ +#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ +#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ +#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ +#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ +#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ +#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ +#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ +#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ +#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ +#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ +#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ +#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ +#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ +#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ +#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ +#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ +#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ +#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ +#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ +#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ +#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ +#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ +#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ +#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ +#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ +#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ +#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ +#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ +#define DMA_TC_CNT 0xFFC00B0C +#define DMA_TC_PER 0xFFC00B10 + +#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ +#define L1_DATA_A_SRAM_SIZE 0x8000 +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ +#define L1_INST_SRAM_SIZE 0x8000 +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) + +#endif /* __BFIN_DEF_ADSP_BF504_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h b/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h new file mode 100644 index 0000000000..4c5baac395 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/BF506_cdef.h @@ -0,0 +1,11 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF506_proc__ +#define __BFIN_CDEF_ADSP_BF506_proc__ + +#include "BF504_cdef.h" + +#endif /* __BFIN_CDEF_ADSP_BF506_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf506/BF506_def.h b/arch/blackfin/include/asm/mach-bf506/BF506_def.h new file mode 100644 index 0000000000..1f91397ea4 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/BF506_def.h @@ -0,0 +1,11 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF506_proc__ +#define __BFIN_DEF_ADSP_BF506_proc__ + +#include "BF504_def.h" + +#endif /* __BFIN_DEF_ADSP_BF506_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf506/anomaly.h b/arch/blackfin/include/asm/mach-bf506/anomaly.h new file mode 100644 index 0000000000..e767233227 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/anomaly.h @@ -0,0 +1,128 @@ +/* + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE + * + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + */ + +/* This file should be up to date with: + */ + +#if __SILICON_REVISION__ < 0 +# error will not work on BF506 silicon version +#endif + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ +#define ANOMALY_05000254 (1) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) +/* UART IrDA Receiver Fails on Extended Bit Pulses */ +#define ANOMALY_05000447 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* PLL Latches Incorrect Settings During Reset */ +#define ANOMALY_05000469 (1) +/* Incorrect Default MSEL Value in PLL_CTL */ +#define ANOMALY_05000472 (1) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ +#define ANOMALY_05000473 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) +#define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) +#define ANOMALY_05000158 (0) +#define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000227 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) +#define ANOMALY_05000242 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) +#define ANOMALY_05000261 (0) +#define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) +#define ANOMALY_05000285 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000301 (0) +#define ANOMALY_05000305 (0) +#define ANOMALY_05000307 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (0) +#define ANOMALY_05000357 (0) +#define ANOMALY_05000362 (1) +#define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) +#define ANOMALY_05000371 (0) +#define ANOMALY_05000380 (0) +#define ANOMALY_05000386 (0) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000402 (0) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000440 (0) +#define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000475 (0) +#define ANOMALY_05000485 (0) + +#endif diff --git a/arch/blackfin/include/asm/mach-bf506/def_local.h b/arch/blackfin/include/asm/mach-bf506/def_local.h new file mode 100644 index 0000000000..e7a416db8e --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/def_local.h @@ -0,0 +1,5 @@ +#include "gpio.h" +#include "portmux.h" +#include "ports.h" + +#define CONFIG_BF50x 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf506/gpio.h b/arch/blackfin/include/asm/mach-bf506/gpio.h new file mode 100644 index 0000000000..08a82f4001 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/gpio.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 35 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PG0 16 +#define GPIO_PG1 17 +#define GPIO_PG2 18 +#define GPIO_PG3 19 +#define GPIO_PG4 20 +#define GPIO_PG5 21 +#define GPIO_PG6 22 +#define GPIO_PG7 23 +#define GPIO_PG8 24 +#define GPIO_PG9 25 +#define GPIO_PG10 26 +#define GPIO_PG11 27 +#define GPIO_PG12 28 +#define GPIO_PG13 29 +#define GPIO_PG14 30 +#define GPIO_PG15 31 +#define GPIO_PH0 32 +#define GPIO_PH1 33 +#define GPIO_PH2 34 + +#define PORT_F GPIO_PF0 +#define PORT_G GPIO_PG0 +#define PORT_H GPIO_PH0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf506/portmux.h b/arch/blackfin/include/asm/mach-bf506/portmux.h new file mode 100644 index 0000000000..086186d075 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/portmux.h @@ -0,0 +1,148 @@ +/* + * Copyright 2008-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +/* PPI Port Mux */ +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) + +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1)) + +/* SPI Port Mux */ +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) + +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) + +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) + +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) + +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF13 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1 + +/* SPORT Port Mux */ +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) + +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) + +/* UART Port Mux */ +#ifdef CONFIG_BF506_UART0_PORTF +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#else +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#endif +#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) +#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) + +#ifdef CONFIG_BF506_UART1_PORTG +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#else +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#endif +#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) + +/* Timer */ +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) + +/* CAN */ +#define P_CAN_TX (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) +#define P_CAN_RX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) + +/* PWM */ +#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) +#define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PWM0_TRIP (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) + +#define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2)) +#define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2)) +#define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2)) +#define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) +#define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) +#define P_PWM1_TRIP (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) + +/* RSI */ +#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) +#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) +#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) +#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) + +/* ACM */ +#define P_ACM_SE_DIFF (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_ACM_RANGE (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_ACM_A0 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_ACM_A1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_ACM_A2 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf506/ports.h b/arch/blackfin/include/asm/mach-bf506/ports.h new file mode 100644 index 0000000000..f1e9cc00d4 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf506/ports.h @@ -0,0 +1,59 @@ +/* + * Port Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT__ +#define __BFIN_PERIPHERAL_PORT__ + +/* PORTx_MUX Masks */ +#define PORT_x_MUX_0_MASK 0x0003 +#define PORT_x_MUX_1_MASK 0x000C +#define PORT_x_MUX_2_MASK 0x0030 +#define PORT_x_MUX_3_MASK 0x00C0 +#define PORT_x_MUX_4_MASK 0x0300 +#define PORT_x_MUX_5_MASK 0x0C00 +#define PORT_x_MUX_6_MASK 0x3000 +#define PORT_x_MUX_7_MASK 0xC000 + +#define PORT_x_MUX_FUNC_1 (0x0) +#define PORT_x_MUX_FUNC_2 (0x1) +#define PORT_x_MUX_FUNC_3 (0x2) +#define PORT_x_MUX_FUNC_4 (0x3) +#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0) +#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0) +#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0) +#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0) +#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2) +#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2) +#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2) +#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2) +#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4) +#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4) +#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4) +#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4) +#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6) +#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6) +#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6) +#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6) +#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8) +#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8) +#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8) +#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8) +#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10) +#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10) +#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10) +#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10) +#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12) +#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12) +#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12) +#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12) +#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) +#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) +#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) +#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) + +#include "../mach-common/bits/ports-f.h" +#include "../mach-common/bits/ports-g.h" +#include "../mach-common/bits/ports-h.h" + +#endif diff --git a/arch/blackfin/include/asm/mach-bf518/BF512_def.h b/arch/blackfin/include/asm/mach-bf518/BF512_def.h index abc88ca6d3..bbaf22fa95 100644 --- a/arch/blackfin/include/asm/mach-bf518/BF512_def.h +++ b/arch/blackfin/include/asm/mach-bf518/BF512_def.h @@ -513,11 +513,5 @@ #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF512_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h deleted file mode 100644 index 5381bf0af7..0000000000 --- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h +++ /dev/null @@ -1,994 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF52x_extended__ - -#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) -#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) -#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) -#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) -#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) -#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) -#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) -#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) -#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) -#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) -#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) -#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) -#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) -#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) -#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) -#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) -#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) -#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) -#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) -#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) -#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) -#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) -#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) -#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) -#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) -#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) -#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) -#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) -#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) -#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) -#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) -#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) -#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) -#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) -#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) -#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE) -#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val) -#define bfin_read_NONGPIO_SLEW() bfin_read16(NONGPIO_SLEW) -#define bfin_write_NONGPIO_SLEW(val) bfin_write16(NONGPIO_SLEW, val) -#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS) -#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val) -#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) -#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) -#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) -#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) -#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) -#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) -#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) -#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) -#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) -#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) -#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) -#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) -#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) -#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) -#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) -#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) -#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) -#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) -#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) -#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) -#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) -#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) -#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) -#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) -#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) -#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) -#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) -#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) -#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) -#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) -#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) -#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define bfin_read_NFC_RST() bfin_read16(NFC_RST) -#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) -#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define bfin_read_NFC_READ() bfin_read16(NFC_READ) -#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) -#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) -#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) -#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) -#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF52x_extended__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h deleted file mode 100644 index 7b97aee57d..0000000000 --- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h +++ /dev/null @@ -1,503 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF52x_extended__ -#define __BFIN_DEF_ADSP_EDN_BF52x_extended__ - -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ -#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ -#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ -#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ -#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ -#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ -#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */ -#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ -#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ -#define PORTF_MUX 0xFFC03210 /* Port F mux control */ -#define PORTG_MUX 0xFFC03214 /* Port G mux control */ -#define PORTH_MUX 0xFFC03218 /* Port H mux control */ -#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ -#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ -#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ -#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ -#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ -#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ -#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ -#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ -#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ -#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */ -#define NONGPIO_SLEW 0xFFC03284 /* Non-GPIO Port slew control */ -#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */ -#define HOST_CONTROL 0xFFC03400 /* HOST Control Register */ -#define HOST_STATUS 0xFFC03404 /* HOST Status Register */ -#define HOST_TIMEOUT 0xFFC03408 /* HOST Acknowledge Mode Timeout Register */ -#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */ -#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */ -#define CNT_STATUS 0xFFC03508 /* Status Register */ -#define CNT_COMMAND 0xFFC0350C /* Command Register */ -#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */ -#define CNT_COUNTER 0xFFC03514 /* Counter Register */ -#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */ -#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */ -#define OTP_CONTROL 0xFFC03600 /* OTP/Fuse Control Register */ -#define OTP_BEN 0xFFC03604 /* OTP/Fuse Byte Enable */ -#define OTP_STATUS 0xFFC03608 /* OTP/Fuse Status */ -#define OTP_TIMING 0xFFC0360C /* OTP/Fuse Access Timing */ -#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */ -#define SECURE_CONTROL 0xFFC03624 /* Secure Control */ -#define SECURE_STATUS 0xFFC03628 /* Secure Status */ -#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ -#define NFC_CTL 0xFFC03700 /* NAND Control Register */ -#define NFC_STAT 0xFFC03704 /* NAND Status Register */ -#define NFC_IRQSTAT 0xFFC03708 /* NAND Interrupt Status Register */ -#define NFC_IRQMASK 0xFFC0370C /* NAND Interrupt Mask Register */ -#define NFC_ECC0 0xFFC03710 /* NAND ECC Register 0 */ -#define NFC_ECC1 0xFFC03714 /* NAND ECC Register 1 */ -#define NFC_ECC2 0xFFC03718 /* NAND ECC Register 2 */ -#define NFC_ECC3 0xFFC0371C /* NAND ECC Register 3 */ -#define NFC_COUNT 0xFFC03720 /* NAND ECC Count Register */ -#define NFC_RST 0xFFC03724 /* NAND ECC Reset Register */ -#define NFC_PGCTL 0xFFC03728 /* NAND Page Control Register */ -#define NFC_READ 0xFFC0372C /* NAND Read Data Register */ -#define NFC_ADDR 0xFFC03740 /* NAND Address Register */ -#define NFC_CMD 0xFFC03744 /* NAND Command Register */ -#define NFC_DATA_WR 0xFFC03748 /* NAND Data Write Register */ -#define NFC_DATA_RD 0xFFC0374C /* NAND Data Read Register */ -#define DMA_TC_CNT 0xFFC00B0C -#define DMA_TC_PER 0xFFC00B10 - -#endif /* __BFIN_DEF_ADSP_EDN_BF52x_extended__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h index 9ce41b16df..49a60afac6 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h @@ -8,8 +8,6 @@ #include "../mach-common/ADSP-EDN-core_cdef.h" -#include "ADSP-EDN-BF52x-extended_cdef.h" - #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) @@ -26,5 +24,989 @@ #define bfin_write_SWRST(val) bfin_write16(SWRST, val) #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define bfin_read_UART0_IER() bfin_read16(UART0_IER) +#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) +#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) +#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) +#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) +#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) +#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) +#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) +#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) +#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) +#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) +#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) +#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) +#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) +#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) +#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) +#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) +#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) +#define bfin_read_PORTFIO() bfin_read16(PORTFIO) +#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) +#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) +#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) +#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) +#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) +#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) +#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) +#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) +#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) +#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) +#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) +#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) +#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) +#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) +#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) +#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) +#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) +#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) +#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) +#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) +#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) +#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) +#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) +#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) +#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) +#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) +#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) +#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) +#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) +#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) +#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) +#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) +#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) +#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) +#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) +#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) +#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) +#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) +#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) +#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) +#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) +#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) +#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) +#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) +#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) +#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) +#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) +#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) +#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) +#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) +#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) +#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) +#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) +#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) +#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) +#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) +#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) +#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) +#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) +#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) +#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) +#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) +#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) +#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) +#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) +#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) +#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) +#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) +#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) +#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) +#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) +#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) +#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) +#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) +#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) +#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) +#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) +#define bfin_read_PORTGIO() bfin_read16(PORTGIO) +#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) +#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) +#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) +#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) +#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) +#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) +#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) +#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) +#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) +#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) +#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) +#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) +#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) +#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) +#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) +#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) +#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) +#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) +#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) +#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) +#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) +#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) +#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) +#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) +#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) +#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) +#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) +#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) +#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) +#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) +#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) +#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) +#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) +#define bfin_read_PORTHIO() bfin_read16(PORTHIO) +#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) +#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) +#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) +#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) +#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) +#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) +#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) +#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) +#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) +#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) +#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) +#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) +#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) +#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) +#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) +#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) +#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) +#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) +#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) +#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) +#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) +#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) +#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) +#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) +#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) +#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) +#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) +#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) +#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) +#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) +#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) +#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) +#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define bfin_read_UART1_IER() bfin_read16(UART1_IER) +#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) +#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) +#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) +#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) +#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) +#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) +#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) +#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) +#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) +#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) +#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) +#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) +#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) +#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) +#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) +#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) +#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) +#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) +#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) +#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) +#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) +#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) +#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) +#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) +#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) +#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) +#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) +#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) +#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) +#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) +#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) +#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) +#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) +#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE) +#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val) +#define bfin_read_NONGPIO_SLEW() bfin_read16(NONGPIO_SLEW) +#define bfin_write_NONGPIO_SLEW(val) bfin_write16(NONGPIO_SLEW, val) +#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS) +#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val) +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) +#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) +#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) +#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) +#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) +#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) +#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) +#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) +#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) +#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) +#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) +#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) +#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) +#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) +#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) +#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) +#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) +#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) +#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) +#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) +#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) +#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) +#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) +#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) +#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) +#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) +#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) +#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) +#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) +#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) +#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) +#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) +#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) +#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) +#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) +#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) +#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) +#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) +#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) +#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) +#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) +#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) +#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) +#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) +#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) +#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) +#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) +#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) +#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) +#define bfin_read_NFC_RST() bfin_read16(NFC_RST) +#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) +#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) +#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) +#define bfin_read_NFC_READ() bfin_read16(NFC_READ) +#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) +#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) +#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) +#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) +#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) +#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) +#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) +#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) +#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) +#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) +#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) +#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) +#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) #endif /* __BFIN_CDEF_ADSP_BF522_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h index a6b0787807..075c6970b5 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF522_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF522_def.h @@ -8,8 +8,6 @@ #include "../mach-common/ADSP-EDN-core_def.h" -#include "ADSP-EDN-BF52x-extended_def.h" - #define PLL_CTL 0xFFC00000 /* PLL Control Register */ #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ @@ -18,5 +16,498 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ +#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ +#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ +#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ +#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ +#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ +#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */ +#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ +#define UART0_THR 0xFFC00400 /* Transmit Holding register */ +#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART0_LCR 0xFFC0040C /* Line Control Register */ +#define UART0_MCR 0xFFC00410 /* Modem Control Register */ +#define UART0_LSR 0xFFC00414 /* Line Status Register */ +#define UART0_MSR 0xFFC00418 /* Modem Status Register */ +#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART0_GCTL 0xFFC00424 /* Global Control Register */ +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ +#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ +#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ +#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ +#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ +#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ +#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ +#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ +#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ +#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ +#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ +#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ +#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ +#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ +#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ +#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ +#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ +#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ +#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ +#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ +#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ +#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ +#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ +#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ +#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ +#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ +#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ +#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ +#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ +#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ +#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ +#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ +#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ +#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ +#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ +#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ +#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ +#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ +#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ +#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ +#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ +#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ +#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ +#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ +#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ +#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ +#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ +#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ +#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ +#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ +#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ +#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ +#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ +#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ +#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ +#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ +#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ +#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ +#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ +#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ +#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ +#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ +#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ +#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ +#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ +#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ +#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ +#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ +#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ +#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ +#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ +#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ +#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ +#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ +#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ +#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ +#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ +#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ +#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ +#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ +#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ +#define UART1_THR 0xFFC02000 /* Transmit Holding register */ +#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ +#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ +#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ +#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ +#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ +#define UART1_LCR 0xFFC0200C /* Line Control Register */ +#define UART1_MCR 0xFFC02010 /* Modem Control Register */ +#define UART1_LSR 0xFFC02014 /* Line Status Register */ +#define UART1_MSR 0xFFC02018 /* Modem Status Register */ +#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ +#define UART1_GCTL 0xFFC02024 /* Global Control Register */ +#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ +#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ +#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ +#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ +#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ +#define PORTF_MUX 0xFFC03210 /* Port F mux control */ +#define PORTG_MUX 0xFFC03214 /* Port G mux control */ +#define PORTH_MUX 0xFFC03218 /* Port H mux control */ +#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ +#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ +#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ +#define PORTF_SLEW 0xFFC03230 /* Port F slew control */ +#define PORTG_SLEW 0xFFC03234 /* Port G slew control */ +#define PORTH_SLEW 0xFFC03238 /* Port H slew control */ +#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ +#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ +#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ +#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */ +#define NONGPIO_SLEW 0xFFC03284 /* Non-GPIO Port slew control */ +#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */ +#define HOST_CONTROL 0xFFC03400 /* HOST Control Register */ +#define HOST_STATUS 0xFFC03404 /* HOST Status Register */ +#define HOST_TIMEOUT 0xFFC03408 /* HOST Acknowledge Mode Timeout Register */ +#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */ +#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */ +#define CNT_STATUS 0xFFC03508 /* Status Register */ +#define CNT_COMMAND 0xFFC0350C /* Command Register */ +#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */ +#define CNT_COUNTER 0xFFC03514 /* Counter Register */ +#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */ +#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */ +#define OTP_CONTROL 0xFFC03600 /* OTP/Fuse Control Register */ +#define OTP_BEN 0xFFC03604 /* OTP/Fuse Byte Enable */ +#define OTP_STATUS 0xFFC03608 /* OTP/Fuse Status */ +#define OTP_TIMING 0xFFC0360C /* OTP/Fuse Access Timing */ +#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */ +#define SECURE_CONTROL 0xFFC03624 /* Secure Control */ +#define SECURE_STATUS 0xFFC03628 /* Secure Status */ +#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define NFC_CTL 0xFFC03700 /* NAND Control Register */ +#define NFC_STAT 0xFFC03704 /* NAND Status Register */ +#define NFC_IRQSTAT 0xFFC03708 /* NAND Interrupt Status Register */ +#define NFC_IRQMASK 0xFFC0370C /* NAND Interrupt Mask Register */ +#define NFC_ECC0 0xFFC03710 /* NAND ECC Register 0 */ +#define NFC_ECC1 0xFFC03714 /* NAND ECC Register 1 */ +#define NFC_ECC2 0xFFC03718 /* NAND ECC Register 2 */ +#define NFC_ECC3 0xFFC0371C /* NAND ECC Register 3 */ +#define NFC_COUNT 0xFFC03720 /* NAND ECC Count Register */ +#define NFC_RST 0xFFC03724 /* NAND ECC Reset Register */ +#define NFC_PGCTL 0xFFC03728 /* NAND Page Control Register */ +#define NFC_READ 0xFFC0372C /* NAND Read Data Register */ +#define NFC_ADDR 0xFFC03740 /* NAND Address Register */ +#define NFC_CMD 0xFFC03744 /* NAND Command Register */ +#define NFC_DATA_WR 0xFFC03748 /* NAND Data Write Register */ +#define NFC_DATA_RD 0xFFC0374C /* NAND Data Read Register */ +#define DMA_TC_CNT 0xFFC00B0C +#define DMA_TC_PER 0xFFC00B10 #endif /* __BFIN_DEF_ADSP_BF522_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h index 25612bfdda..060dce31a2 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h @@ -6,26 +6,8 @@ #ifndef __BFIN_CDEF_ADSP_BF524_proc__ #define __BFIN_CDEF_ADSP_BF524_proc__ -#include "../mach-common/ADSP-EDN-core_cdef.h" +#include "BF522_cdef.h" -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) #define bfin_read_USB_POWER() bfin_read16(USB_POWER) diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_def.h b/arch/blackfin/include/asm/mach-bf527/BF524_def.h index 0a0056adb0..f0e77166a7 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF524_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF524_def.h @@ -6,18 +6,8 @@ #ifndef __BFIN_DEF_ADSP_BF524_proc__ #define __BFIN_DEF_ADSP_BF524_proc__ -#include "../mach-common/ADSP-EDN-core_def.h" +#include "BF522_def.h" -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ #define USB_FADDR 0xFFC03800 /* Function address register */ #define USB_POWER 0xFFC03804 /* Power management register */ #define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h index aa320ac8c4..515acd3285 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h @@ -6,26 +6,8 @@ #ifndef __BFIN_CDEF_ADSP_BF526_proc__ #define __BFIN_CDEF_ADSP_BF526_proc__ -#include "../mach-common/ADSP-EDN-core_cdef.h" +#include "BF524_cdef.h" -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) #define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) @@ -184,343 +166,5 @@ #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) #endif /* __BFIN_CDEF_ADSP_BF526_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_def.h b/arch/blackfin/include/asm/mach-bf527/BF526_def.h index 935d11ee65..40b5b01f11 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF526_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF526_def.h @@ -6,18 +6,8 @@ #ifndef __BFIN_DEF_ADSP_BF526_proc__ #define __BFIN_DEF_ADSP_BF526_proc__ -#include "../mach-common/ADSP-EDN-core_def.h" +#include "BF524_def.h" -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ @@ -97,174 +87,5 @@ #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ -#define USB_FADDR 0xFFC03800 /* Function address register */ -#define USB_POWER 0xFFC03804 /* Power management register */ -#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03820 /* USB frame number */ -#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ #endif /* __BFIN_DEF_ADSP_BF526_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h index 5d61972176..3b61aafcc9 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF531_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF531_def.h @@ -438,12 +438,6 @@ #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif #endif /* __BFIN_DEF_ADSP_BF531_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_def.h b/arch/blackfin/include/asm/mach-bf533/BF532_def.h index f7378b70a7..64f55f50c7 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF532_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF532_def.h @@ -12,12 +12,6 @@ #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif #endif /* __BFIN_DEF_ADSP_BF532_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_def.h b/arch/blackfin/include/asm/mach-bf533/BF533_def.h index b77efe0a2c..3c0595f50b 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF533_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF533_def.h @@ -17,11 +17,5 @@ #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF533_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h deleted file mode 100644 index bfe6d9f414..0000000000 --- a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h +++ /dev/null @@ -1,1624 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_BF534_extended__ -#define __BFIN_CDEF_ADSP_EDN_BF534_extended__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) -#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) -#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) -#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) -#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) -#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define bfin_read_UART0_THR() bfin_read16(UART0_THR) -#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) -#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) -#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define bfin_read_UART0_IER() bfin_read16(UART0_IER) -#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) -#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) -#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) -#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) -#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) -#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) -#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) -#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) -#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) -#define bfin_read_PORTFIO() bfin_read16(PORTFIO) -#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) -#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) -#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) -#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) -#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) -#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) -#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) -#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) -#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) -#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) -#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) -#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) -#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) -#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) -#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) -#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) -#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) -#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) -#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) -#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) -#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) -#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) -#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) -#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) -#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) -#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) -#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) -#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) -#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) -#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) -#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) -#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) -#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) -#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) -#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) -#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) -#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) -#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) -#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) -#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) -#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) -#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) -#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) -#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) -#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) -#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) -#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) -#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) -#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) -#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) -#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) -#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) -#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) -#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) -#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) -#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) -#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) -#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) -#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) -#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) -#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) -#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) -#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) -#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) -#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) -#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) -#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) -#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) -#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) -#define bfin_read_PORTGIO() bfin_read16(PORTGIO) -#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) -#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) -#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) -#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) -#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) -#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) -#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) -#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) -#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) -#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) -#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) -#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) -#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) -#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) -#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) -#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) -#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) -#define bfin_read_PORTHIO() bfin_read16(PORTHIO) -#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) -#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) -#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) -#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) -#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) -#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) -#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) -#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) -#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) -#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) -#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) -#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) -#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) -#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) -#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) -#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) -#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) -#define bfin_read_UART1_THR() bfin_read16(UART1_THR) -#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) -#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) -#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define bfin_read_UART1_IER() bfin_read16(UART1_IER) -#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) -#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) -#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) -#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) -#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) -#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) -#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) -#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) -#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) -#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) -#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) -#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val) -#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) -#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val) -#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) -#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val) -#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) -#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val) -#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) -#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val) -#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) -#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val) -#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) -#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val) -#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) -#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val) -#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) -#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val) -#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) -#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val) -#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) -#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val) -#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) -#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val) -#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) -#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val) -#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) -#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val) -#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) -#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val) -#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) -#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val) -#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) -#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val) -#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) -#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val) -#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) -#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val) -#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) -#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val) -#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) -#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val) -#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) -#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val) -#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) -#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val) -#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) -#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val) -#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) -#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val) -#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) -#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val) -#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) -#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val) -#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) -#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val) -#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) -#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val) -#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) -#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val) -#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) -#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val) -#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) -#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val) -#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) -#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val) -#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) -#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val) -#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) -#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val) -#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION) -#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val) -#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) -#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val) -#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) -#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val) -#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) -#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val) -#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) -#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val) -#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) -#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val) -#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) -#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val) -#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) -#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val) -#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2) -#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val) -#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) -#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val) -#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) -#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val) -#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) -#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val) -#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) -#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val) -#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) -#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val) -#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) -#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val) -#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) -#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val) -#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) -#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val) -#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) -#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val) -#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) -#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val) -#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) -#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val) -#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) -#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val) -#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) -#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val) -#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) -#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val) -#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) -#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val) -#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) -#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val) -#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) -#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val) -#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) -#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val) -#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) -#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val) -#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) -#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val) -#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) -#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val) -#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) -#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val) -#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) -#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val) -#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) -#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val) -#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) -#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val) -#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) -#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val) -#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) -#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val) -#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) -#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val) -#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) -#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val) -#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) -#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val) -#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) -#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val) -#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) -#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val) -#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) -#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val) -#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) -#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val) -#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) -#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val) -#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) -#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val) -#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) -#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val) -#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) -#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val) -#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) -#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val) -#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) -#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val) -#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) -#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val) -#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) -#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val) -#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) -#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val) -#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) -#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val) -#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) -#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val) -#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) -#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val) -#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) -#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val) -#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) -#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val) -#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) -#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val) -#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) -#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val) -#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) -#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val) -#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) -#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val) -#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) -#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val) -#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) -#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val) -#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) -#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val) -#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) -#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val) -#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) -#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val) -#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) -#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val) -#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) -#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val) -#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) -#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val) -#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) -#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val) -#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) -#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val) -#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) -#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val) -#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) -#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val) -#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) -#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val) -#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) -#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val) -#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) -#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val) -#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) -#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val) -#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) -#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val) -#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) -#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val) -#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) -#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val) -#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) -#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val) -#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) -#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val) -#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) -#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val) -#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) -#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val) -#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) -#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val) -#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) -#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val) -#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) -#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val) -#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) -#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val) -#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) -#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val) -#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) -#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val) -#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) -#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val) -#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) -#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val) -#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) -#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val) -#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) -#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val) -#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) -#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val) -#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) -#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val) -#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) -#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val) -#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) -#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val) -#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) -#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val) -#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) -#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val) -#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) -#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val) -#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) -#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val) -#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) -#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val) -#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) -#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val) -#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) -#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val) -#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) -#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val) -#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) -#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val) -#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) -#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val) -#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) -#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val) -#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) -#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val) -#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) -#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val) -#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) -#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val) -#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) -#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val) -#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) -#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val) -#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) -#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val) -#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) -#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val) -#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) -#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val) -#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) -#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val) -#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) -#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val) -#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) -#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val) -#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) -#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val) -#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) -#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val) -#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) -#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val) -#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) -#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val) -#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) -#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val) -#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) -#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val) -#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) -#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val) -#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) -#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val) -#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) -#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val) -#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) -#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val) -#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) -#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val) -#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) -#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val) -#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) -#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val) -#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) -#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val) -#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) -#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val) -#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) -#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val) -#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) -#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val) -#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) -#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val) -#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) -#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val) -#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) -#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val) -#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) -#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val) -#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) -#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val) -#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) -#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val) -#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) -#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val) -#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) -#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val) -#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) -#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val) -#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) -#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val) -#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) -#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val) -#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) -#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val) -#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) -#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val) -#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) -#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val) -#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) -#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val) -#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) -#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val) -#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) -#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val) -#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) -#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val) -#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) -#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val) -#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) -#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val) -#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) -#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val) -#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) -#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val) -#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) -#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val) -#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) -#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val) -#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) -#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val) -#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) -#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val) -#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) -#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val) -#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) -#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val) -#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) -#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val) -#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) -#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val) -#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) -#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val) -#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) -#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val) -#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) -#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val) -#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) -#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val) -#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) -#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val) -#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) -#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val) -#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) -#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val) -#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) -#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val) -#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) -#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val) -#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) -#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val) -#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) -#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val) -#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) -#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val) -#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) -#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val) -#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) -#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val) -#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) -#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val) -#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) -#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val) -#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) -#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val) -#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) -#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val) -#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) -#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val) -#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) -#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val) -#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) -#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val) -#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) -#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val) -#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) -#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val) -#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) -#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val) -#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) -#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val) -#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) -#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val) -#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) -#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val) -#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) -#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val) -#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) -#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val) -#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) -#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val) -#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) -#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val) -#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) -#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val) -#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) -#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val) -#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) -#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val) -#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) -#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val) -#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) -#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val) -#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) -#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val) -#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) -#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val) -#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) -#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val) -#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) -#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val) -#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) -#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val) -#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) -#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val) -#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) -#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val) -#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) -#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val) -#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) -#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val) -#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) -#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val) -#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) -#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val) -#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) -#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val) -#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) -#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val) -#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) -#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val) -#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) -#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val) -#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) -#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val) -#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) -#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val) -#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) -#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val) -#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) -#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val) -#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) -#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val) -#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) -#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val) -#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) -#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val) -#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) -#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val) -#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) -#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val) -#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) -#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val) -#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) -#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val) -#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) -#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val) -#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) -#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val) -#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) -#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val) -#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) -#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val) -#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) -#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val) -#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) -#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val) -#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) -#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val) -#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) -#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val) -#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) -#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val) -#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) -#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val) -#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) -#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val) -#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) -#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val) -#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) -#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val) -#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) -#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val) -#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) -#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val) -#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) -#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val) -#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) -#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val) -#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) -#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val) -#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) -#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val) -#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) -#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val) -#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) -#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val) -#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) -#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val) -#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) -#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val) -#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) -#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val) -#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) -#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val) -#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) -#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val) -#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) -#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val) -#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) -#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val) -#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) -#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val) -#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) -#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val) -#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) -#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val) -#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) -#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val) -#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) -#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val) -#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) -#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val) -#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) -#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val) -#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) -#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val) -#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) -#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val) -#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) -#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val) -#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) -#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val) -#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) -#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val) -#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) -#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val) -#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) -#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val) -#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) -#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val) -#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) -#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val) -#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) -#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val) -#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) -#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val) -#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) -#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val) -#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) -#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val) -#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) -#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val) -#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) -#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val) -#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) -#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val) -#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) -#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val) -#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) -#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val) -#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) -#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val) -#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) -#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val) -#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) -#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val) -#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) -#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val) -#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) -#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val) -#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) -#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val) -#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) -#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val) -#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) -#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val) -#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) -#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val) -#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) -#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val) -#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) -#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val) -#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) -#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val) -#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) -#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val) -#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) -#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val) -#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) -#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val) -#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) -#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val) -#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) -#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val) -#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) -#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val) -#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) -#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val) -#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) -#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val) -#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) -#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val) -#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) -#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val) -#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) -#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val) -#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) -#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val) -#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) -#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val) -#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) -#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val) -#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) -#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val) -#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) -#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val) -#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) -#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val) -#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) -#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val) -#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) -#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val) -#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) -#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val) -#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) -#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val) -#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) -#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val) -#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) -#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val) -#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) -#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val) -#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) -#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val) -#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) -#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val) -#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) -#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val) -#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) -#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val) -#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) -#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val) -#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) -#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val) -#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) -#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val) -#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) -#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val) -#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) -#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val) -#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) -#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val) -#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) -#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) -#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) -#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) -#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) -#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) -#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) -#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) -#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) -#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) -#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) -#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) -#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) -#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) -#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) -#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) -#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) -#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) -#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) -#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) -#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) -#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_BF534_extended__ */ diff --git a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h deleted file mode 100644 index 81b158e374..0000000000 --- a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h +++ /dev/null @@ -1,819 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_BF534_extended__ -#define __BFIN_DEF_ADSP_EDN_BF534_extended__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration Register */ -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define RTC_STAT 0xFFC00300 /* RTC Status Register */ -#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ -#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ -#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ -#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ -#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ -#define UART0_THR 0xFFC00400 /* Transmit Holding register */ -#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ -#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ -#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ -#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ -#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ -#define UART0_LCR 0xFFC0040C /* Line Control Register */ -#define UART0_MCR 0xFFC00410 /* Modem Control Register */ -#define UART0_LSR 0xFFC00414 /* Line Status Register */ -#define UART0_MSR 0xFFC00418 /* Modem Status Register */ -#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ -#define UART0_GCTL 0xFFC00424 /* Global Control Register */ -#define SPI_CTL 0xFFC00500 /* SPI Control Register */ -#define SPI_FLG 0xFFC00504 /* SPI Flag register */ -#define SPI_STAT 0xFFC00508 /* SPI Status register */ -#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ -#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ -#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ -#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ -#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ -#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ -#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ -#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ -#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ -#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ -#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ -#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ -#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ -#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ -#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ -#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ -#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ -#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ -#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ -#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ -#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ -#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ -#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ -#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ -#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ -#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ -#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ -#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ -#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ -#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ -#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ -#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ -#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ -#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ -#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ -#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ -#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ -#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ -#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ -#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ -#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ -#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ -#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ -#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ -#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ -#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ -#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ -#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ -#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ -#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ -#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ -#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ -#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ -#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ -#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ -#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ -#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ -#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ -#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ -#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ -#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ -#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ -#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ -#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ -#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ -#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ -#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ -#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ -#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ -#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ -#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ -#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ -#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ -#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ -#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ -#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ -#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ -#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ -#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ -#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ -#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ -#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ -#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ -#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ -#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ -#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ -#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ -#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ -#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ -#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ -#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ -#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ -#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ -#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ -#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ -#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ -#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ -#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ -#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ -#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ -#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ -#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ -#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ -#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ -#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ -#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ -#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ -#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ -#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ -#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ -#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ -#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ -#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ -#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ -#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ -#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ -#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ -#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ -#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ -#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ -#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ -#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ -#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ -#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ -#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ -#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ -#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ -#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ -#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ -#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ -#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ -#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ -#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ -#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ -#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ -#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ -#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ -#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ -#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ -#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ -#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ -#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ -#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ -#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ -#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ -#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ -#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ -#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ -#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ -#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ -#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ -#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ -#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ -#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ -#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ -#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ -#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ -#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ -#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ -#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ -#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ -#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ -#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ -#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ -#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ -#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ -#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ -#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ -#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ -#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ -#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ -#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ -#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ -#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ -#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ -#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ -#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ -#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ -#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ -#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ -#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ -#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ -#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ -#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ -#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ -#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ -#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ -#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ -#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ -#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ -#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ -#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ -#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ -#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ -#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ -#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ -#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ -#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ -#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ -#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ -#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ -#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ -#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ -#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ -#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ -#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ -#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ -#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ -#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ -#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ -#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ -#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ -#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ -#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ -#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ -#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ -#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ -#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ -#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ -#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ -#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ -#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ -#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ -#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ -#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ -#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ -#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ -#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ -#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ -#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ -#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ -#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ -#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ -#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ -#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ -#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ -#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ -#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ -#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ -#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ -#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ -#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ -#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ -#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ -#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ -#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ -#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ -#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ -#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ -#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ -#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ -#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ -#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ -#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ -#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ -#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ -#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ -#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ -#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ -#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ -#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ -#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ -#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ -#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ -#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ -#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ -#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ -#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ -#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ -#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ -#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ -#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ -#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ -#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ -#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ -#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ -#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ -#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ -#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ -#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ -#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ -#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ -#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ -#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ -#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ -#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ -#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ -#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ -#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ -#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ -#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ -#define UART1_THR 0xFFC02000 /* Transmit Holding register */ -#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ -#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ -#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ -#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ -#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ -#define UART1_LCR 0xFFC0200C /* Line Control Register */ -#define UART1_MCR 0xFFC02010 /* Modem Control Register */ -#define UART1_LSR 0xFFC02014 /* Line Status Register */ -#define UART1_MSR 0xFFC02018 /* Modem Status Register */ -#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ -#define UART1_GCTL 0xFFC02024 /* Global Control Register */ -#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ -#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ -#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ -#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ -#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ -#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ -#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ -#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ -#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ -#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ -#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ -#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ -#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ -#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ -#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ -#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ -#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ -#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ -#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ -#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ -#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ -#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ -#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ -#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ -#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ -#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ -#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ -#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ -#define CAN_DEBUG 0xFFC02A88 /* Config register */ -#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ -#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ -#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ -#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ -#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ -#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ -#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ -#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */ -#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ -#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ -#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ -#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ -#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ -#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ -#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ -#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */ -#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ -#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ -#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ -#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ -#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ -#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ -#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ -#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ -#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ -#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ -#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ -#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ -#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ -#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ -#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ -#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ -#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ -#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ -#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ -#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ -#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ -#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ -#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ -#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ -#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ -#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ -#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ -#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ -#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ -#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ -#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ -#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ -#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ -#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ -#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ -#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ -#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ -#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ -#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ -#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ -#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ -#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ -#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ -#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ -#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ -#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ -#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ -#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ -#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ -#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ -#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ -#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ -#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ -#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ -#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ -#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ -#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ -#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ -#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ -#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ -#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ -#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ -#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ -#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ -#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ -#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ -#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ -#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ -#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ -#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ -#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ -#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ -#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ -#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ -#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ -#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ -#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ -#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ -#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ -#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ -#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ -#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ -#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ -#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ -#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ -#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ -#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ -#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ -#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ -#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ -#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ -#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ -#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ -#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ -#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ -#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ -#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ -#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ -#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ -#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ -#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ -#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ -#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ -#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ -#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ -#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ -#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ -#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ -#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ -#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ -#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ -#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ -#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ -#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ -#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ -#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ -#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ -#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ -#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ -#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ -#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ -#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ -#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ -#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ -#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ -#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ -#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ -#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ -#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ -#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ -#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ -#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ -#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ -#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ -#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ -#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ -#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ -#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ -#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ -#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ -#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ -#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ -#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ -#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ -#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ -#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ -#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ -#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ -#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ -#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ -#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ -#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ -#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ -#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ -#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ -#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ -#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ -#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ -#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ -#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ -#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ -#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ -#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ -#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ -#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ -#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ -#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ -#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ -#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ -#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ -#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ -#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ -#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ -#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ -#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ -#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ -#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ -#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ -#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ -#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ -#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ -#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ -#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ -#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ -#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ -#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ -#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ -#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ -#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ -#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ -#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ -#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ -#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ -#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ -#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ -#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ -#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ -#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ -#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ -#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ -#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ -#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ -#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ -#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ -#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ -#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ -#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ -#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ -#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ -#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ -#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ -#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ -#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ -#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ -#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ -#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ -#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ -#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ -#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ -#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ -#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ -#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ -#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ -#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ -#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ -#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ -#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ -#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ -#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ -#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ -#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ -#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ -#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ -#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ -#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ -#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ -#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ -#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ -#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ -#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ -#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ -#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ -#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ -#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ -#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ -#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ -#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ -#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ -#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ -#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ -#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ -#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ -#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ -#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ -#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ -#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ -#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ -#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ -#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ -#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ -#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ -#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ -#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ -#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ -#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ -#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ -#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ -#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ -#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ -#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ -#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ -#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ -#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ -#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ -#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ -#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ -#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ -#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ -#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ -#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ -#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ -#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ -#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ -#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ -#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ -#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ -#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ -#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ -#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ -#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ -#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ -#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ -#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ -#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ -#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ -#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ -#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ -#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ -#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ -#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ -#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ -#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ -#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ -#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ -#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ -#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ -#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ -#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ -#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ -#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ -#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ -#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ -#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ -#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ -#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ -#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ -#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ -#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ -#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ -#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ -#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ -#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ -#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ -#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ -#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ -#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ -#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ -#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ -#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ -#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ -#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ -#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ -#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ -#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ -#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ -#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ -#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ -#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ -#define CHIPID 0xFFC00014 -#define DMA_TC_CNT 0xFFC00B0C -#define DMA_TC_PER 0xFFC00B10 - -#endif /* __BFIN_DEF_ADSP_EDN_BF534_extended__ */ diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h index 27842cc954..3d9412d181 100644 --- a/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h +++ b/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h @@ -8,7 +8,1617 @@ #include "../mach-common/ADSP-EDN-core_cdef.h" -#include "ADSP-EDN-BF534-extended_cdef.h" - +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) +#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) +#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) +#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) +#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) +#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) +#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define bfin_read_UART0_IER() bfin_read16(UART0_IER) +#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) +#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) +#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) +#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) +#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) +#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) +#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) +#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) +#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) +#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) +#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) +#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) +#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) +#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) +#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) +#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) +#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) +#define bfin_read_PORTFIO() bfin_read16(PORTFIO) +#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) +#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) +#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) +#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) +#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) +#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) +#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) +#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) +#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) +#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) +#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) +#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) +#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) +#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) +#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) +#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) +#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) +#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) +#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) +#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) +#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) +#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) +#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) +#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) +#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) +#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) +#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) +#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) +#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) +#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) +#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) +#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) +#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) +#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) +#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) +#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) +#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) +#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) +#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) +#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) +#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) +#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) +#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) +#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) +#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) +#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) +#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) +#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) +#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) +#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) +#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) +#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) +#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) +#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) +#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) +#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) +#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) +#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) +#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) +#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) +#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) +#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) +#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) +#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) +#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) +#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) +#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) +#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) +#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) +#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) +#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) +#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) +#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) +#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) +#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) +#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) +#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) +#define bfin_read_PORTGIO() bfin_read16(PORTGIO) +#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) +#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) +#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) +#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) +#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) +#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) +#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) +#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) +#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) +#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) +#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) +#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) +#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) +#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) +#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) +#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) +#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) +#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) +#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) +#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) +#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) +#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) +#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) +#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) +#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) +#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) +#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) +#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) +#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) +#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) +#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) +#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) +#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) +#define bfin_read_PORTHIO() bfin_read16(PORTHIO) +#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) +#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) +#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) +#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) +#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) +#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) +#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) +#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) +#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) +#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) +#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) +#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) +#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) +#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) +#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) +#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) +#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) +#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) +#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) +#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) +#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) +#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) +#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) +#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) +#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) +#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) +#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) +#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) +#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) +#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) +#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) +#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) +#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define bfin_read_UART1_IER() bfin_read16(UART1_IER) +#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) +#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) +#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) +#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) +#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) +#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) +#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val) +#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) +#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val) +#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) +#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val) +#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) +#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val) +#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) +#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val) +#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) +#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val) +#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) +#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val) +#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) +#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val) +#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) +#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val) +#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) +#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val) +#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) +#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val) +#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) +#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val) +#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) +#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val) +#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) +#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val) +#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) +#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val) +#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) +#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val) +#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) +#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val) +#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) +#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val) +#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) +#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val) +#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) +#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val) +#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) +#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val) +#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) +#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val) +#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) +#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val) +#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) +#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val) +#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) +#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val) +#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) +#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val) +#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) +#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val) +#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) +#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val) +#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) +#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val) +#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) +#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val) +#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) +#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val) +#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) +#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val) +#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) +#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val) +#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) +#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val) +#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) +#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val) +#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION) +#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val) +#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) +#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val) +#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) +#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val) +#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) +#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val) +#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) +#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val) +#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) +#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val) +#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) +#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val) +#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) +#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val) +#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2) +#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val) +#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) +#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val) +#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) +#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val) +#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) +#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val) +#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) +#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val) +#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) +#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val) +#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) +#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val) +#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) +#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val) +#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) +#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val) +#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) +#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val) +#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) +#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val) +#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) +#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val) +#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) +#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val) +#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) +#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val) +#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) +#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val) +#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) +#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val) +#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) +#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val) +#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) +#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val) +#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) +#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val) +#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) +#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val) +#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) +#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val) +#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) +#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val) +#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) +#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val) +#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) +#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val) +#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) +#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val) +#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) +#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val) +#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) +#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val) +#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) +#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val) +#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) +#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val) +#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) +#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val) +#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) +#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val) +#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) +#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val) +#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) +#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val) +#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) +#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val) +#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) +#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val) +#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) +#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val) +#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) +#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val) +#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) +#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val) +#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) +#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val) +#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) +#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val) +#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) +#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val) +#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) +#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val) +#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) +#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val) +#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) +#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val) +#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) +#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val) +#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) +#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val) +#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) +#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val) +#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) +#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val) +#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) +#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val) +#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) +#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val) +#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) +#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val) +#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) +#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val) +#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) +#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val) +#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) +#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val) +#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) +#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val) +#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) +#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val) +#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) +#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val) +#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) +#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val) +#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) +#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val) +#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) +#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val) +#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) +#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val) +#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) +#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val) +#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) +#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val) +#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) +#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val) +#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) +#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val) +#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) +#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val) +#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) +#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val) +#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) +#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val) +#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) +#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val) +#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) +#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val) +#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) +#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val) +#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) +#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val) +#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) +#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val) +#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) +#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val) +#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) +#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val) +#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) +#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val) +#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) +#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val) +#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) +#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val) +#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) +#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val) +#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) +#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val) +#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) +#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val) +#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) +#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val) +#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) +#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val) +#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) +#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val) +#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) +#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val) +#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) +#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val) +#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) +#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val) +#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) +#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val) +#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) +#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val) +#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) +#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val) +#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) +#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val) +#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) +#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val) +#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) +#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val) +#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) +#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val) +#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) +#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val) +#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) +#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val) +#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) +#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val) +#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) +#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val) +#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) +#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val) +#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) +#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val) +#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) +#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val) +#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) +#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val) +#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) +#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val) +#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) +#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val) +#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) +#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val) +#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) +#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val) +#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) +#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val) +#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) +#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val) +#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) +#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val) +#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) +#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val) +#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) +#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val) +#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) +#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val) +#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) +#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val) +#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) +#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val) +#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) +#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val) +#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) +#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val) +#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) +#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val) +#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) +#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val) +#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) +#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val) +#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) +#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val) +#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) +#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val) +#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) +#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val) +#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) +#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val) +#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) +#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val) +#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) +#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val) +#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) +#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val) +#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) +#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val) +#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) +#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val) +#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) +#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val) +#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) +#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val) +#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) +#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val) +#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) +#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val) +#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) +#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val) +#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) +#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val) +#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) +#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val) +#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) +#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val) +#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) +#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val) +#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) +#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val) +#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) +#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val) +#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) +#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val) +#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) +#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val) +#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) +#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val) +#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) +#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val) +#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) +#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val) +#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) +#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val) +#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) +#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val) +#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) +#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val) +#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) +#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val) +#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) +#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val) +#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) +#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val) +#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) +#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val) +#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) +#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val) +#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) +#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val) +#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) +#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val) +#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) +#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val) +#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) +#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val) +#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) +#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val) +#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) +#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val) +#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) +#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val) +#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) +#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val) +#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) +#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val) +#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) +#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val) +#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) +#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val) +#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) +#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val) +#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) +#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val) +#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) +#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val) +#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) +#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val) +#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) +#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val) +#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) +#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val) +#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) +#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val) +#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) +#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val) +#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) +#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val) +#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) +#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val) +#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) +#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val) +#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) +#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val) +#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) +#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val) +#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) +#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val) +#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) +#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val) +#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) +#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val) +#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) +#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val) +#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) +#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val) +#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) +#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val) +#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) +#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val) +#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) +#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val) +#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) +#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val) +#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) +#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val) +#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) +#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val) +#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) +#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val) +#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) +#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val) +#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) +#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val) +#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) +#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val) +#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) +#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val) +#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) +#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val) +#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) +#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val) +#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) +#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val) +#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) +#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val) +#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) +#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val) +#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) +#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val) +#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) +#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val) +#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) +#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val) +#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) +#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val) +#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) +#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val) +#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) +#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val) +#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) +#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val) +#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) +#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val) +#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) +#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val) +#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) +#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val) +#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) +#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val) +#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) +#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val) +#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) +#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val) +#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) +#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val) +#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) +#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val) +#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) +#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val) +#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) +#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val) +#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) +#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val) +#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) +#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val) +#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) +#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val) +#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) +#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val) +#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) +#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val) +#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) +#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val) +#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) +#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val) +#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) +#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val) +#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) +#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val) +#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) +#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val) +#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) +#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val) +#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) +#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val) +#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) +#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val) +#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) +#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val) +#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) +#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val) +#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) +#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val) +#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) +#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val) +#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) +#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val) +#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) +#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val) +#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) +#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val) +#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) +#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val) +#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) +#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val) +#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) +#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val) +#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) +#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val) +#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) +#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val) +#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) +#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val) +#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) +#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val) +#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) +#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val) +#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) +#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val) +#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) +#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val) +#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) +#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val) +#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) +#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val) +#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) +#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val) +#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) +#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val) +#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) +#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val) +#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) +#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val) +#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) +#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val) +#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) +#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val) +#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) +#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val) +#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) +#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val) +#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) +#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val) +#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) +#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val) +#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) +#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val) +#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) +#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val) +#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) +#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val) +#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) +#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val) +#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) +#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val) +#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) +#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val) +#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) +#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val) +#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) +#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val) +#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) +#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val) +#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) +#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val) +#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) +#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val) +#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) +#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val) +#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) +#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val) +#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) +#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val) +#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) +#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val) +#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) +#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val) +#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) +#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val) +#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) +#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val) +#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) +#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val) +#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) +#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val) +#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) +#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val) +#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) +#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val) +#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) +#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val) +#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) +#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val) +#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) +#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val) +#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) +#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val) +#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) +#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val) +#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) +#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val) +#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) +#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val) +#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) +#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val) +#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) +#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val) +#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) +#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val) +#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) +#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val) +#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) +#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val) +#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) +#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val) +#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) +#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val) +#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) +#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val) +#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) +#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val) +#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) +#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val) +#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) +#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val) +#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) +#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val) +#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) +#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val) +#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) +#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val) +#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) +#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val) +#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) +#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val) +#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) +#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val) +#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) +#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val) +#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) +#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val) +#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) +#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val) +#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) +#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val) +#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) +#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val) +#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) +#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val) +#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) +#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val) +#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) +#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val) +#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) +#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val) +#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) +#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val) +#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) +#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val) +#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) +#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val) +#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) +#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val) +#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) +#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val) +#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) +#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val) +#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) +#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val) +#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) +#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val) +#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) +#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val) +#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) +#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) +#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) +#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) +#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) +#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) +#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) +#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) +#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) +#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) +#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) +#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) +#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) +#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) #endif /* __BFIN_CDEF_ADSP_BF534_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_def.h b/arch/blackfin/include/asm/mach-bf537/BF534_def.h index e04676c14a..cb6a543d56 100644 --- a/arch/blackfin/include/asm/mach-bf537/BF534_def.h +++ b/arch/blackfin/include/asm/mach-bf537/BF534_def.h @@ -8,9 +8,815 @@ #include "../mach-common/ADSP-EDN-core_def.h" -#include "ADSP-EDN-BF534-extended_def.h" +#define PLL_CTL 0xFFC00000 /* PLL Control Register */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ +#define PLL_STAT 0xFFC0000C /* PLL Status Register */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ +#define SWRST 0xFFC00100 /* Software Reset Register */ +#define SYSCR 0xFFC00104 /* System Configuration Register */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ +#define UART0_THR 0xFFC00400 /* Transmit Holding register */ +#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART0_LCR 0xFFC0040C /* Line Control Register */ +#define UART0_MCR 0xFFC00410 /* Modem Control Register */ +#define UART0_LSR 0xFFC00414 /* Line Status Register */ +#define UART0_MSR 0xFFC00418 /* Modem Status Register */ +#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART0_GCTL 0xFFC00424 /* Global Control Register */ +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ +#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ +#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ +#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ +#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ +#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ +#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ +#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ +#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ +#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ +#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ +#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ +#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ +#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ +#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ +#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ +#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ +#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ +#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ +#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ +#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ +#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ +#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ +#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ +#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ +#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ +#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ +#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ +#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ +#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ +#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ +#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ +#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ +#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ +#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ +#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ +#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ +#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ +#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ +#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ +#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ +#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ +#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ +#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ +#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ +#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ +#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ +#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ +#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ +#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ +#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ +#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ +#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ +#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ +#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ +#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ +#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ +#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ +#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ +#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ +#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ +#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ +#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ +#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ +#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ +#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ +#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ +#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ +#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ +#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ +#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ +#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ +#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ +#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ +#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ +#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ +#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ +#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ +#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ +#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ +#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ +#define UART1_THR 0xFFC02000 /* Transmit Holding register */ +#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ +#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ +#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ +#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ +#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ +#define UART1_LCR 0xFFC0200C /* Line Control Register */ +#define UART1_MCR 0xFFC02010 /* Modem Control Register */ +#define UART1_LSR 0xFFC02014 /* Line Status Register */ +#define UART1_MSR 0xFFC02018 /* Modem Status Register */ +#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ +#define UART1_GCTL 0xFFC02024 /* Global Control Register */ +#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ +#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ +#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ +#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ +#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ +#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ +#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ +#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ +#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ +#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ +#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ +#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ +#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ +#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ +#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ +#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ +#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ +#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ +#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ +#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ +#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ +#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ +#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ +#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ +#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ +#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ +#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ +#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ +#define CAN_DEBUG 0xFFC02A88 /* Config register */ +#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ +#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ +#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ +#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ +#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ +#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ +#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ +#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */ +#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ +#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ +#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ +#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ +#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ +#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ +#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ +#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */ +#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ +#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ +#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ +#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ +#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ +#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ +#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ +#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ +#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ +#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ +#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ +#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ +#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ +#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ +#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ +#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ +#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ +#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ +#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ +#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ +#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ +#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ +#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ +#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ +#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ +#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ +#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ +#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ +#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ +#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ +#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ +#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ +#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ +#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ +#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ +#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ +#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ +#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ +#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ +#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ +#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ +#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ +#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ +#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ +#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ +#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ +#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ +#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ +#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ +#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ +#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ +#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ +#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ +#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ +#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ +#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ +#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ +#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ +#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ +#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ +#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ +#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ +#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ +#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ +#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ +#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ +#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ +#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ +#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ +#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ +#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ +#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ +#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ +#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ +#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ +#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ +#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ +#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ +#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ +#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ +#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ +#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ +#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ +#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ +#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ +#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ +#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ +#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ +#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ +#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ +#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ +#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ +#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ +#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ +#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ +#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ +#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ +#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ +#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ +#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ +#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ +#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ +#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ +#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ +#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ +#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ +#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ +#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ +#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ +#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ +#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ +#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ +#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ +#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ +#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ +#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ +#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ +#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ +#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ +#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ +#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ +#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ +#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ +#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ +#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ +#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ +#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ +#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ +#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ +#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ +#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ +#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ +#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ +#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ +#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ +#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ +#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ +#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ +#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ +#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ +#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ +#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ +#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ +#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ +#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ +#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ +#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ +#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ +#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ +#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ +#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ +#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ +#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ +#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ +#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ +#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ +#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ +#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ +#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ +#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ +#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ +#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ +#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ +#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ +#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ +#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ +#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ +#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ +#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ +#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ +#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ +#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ +#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ +#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ +#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ +#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ +#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ +#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ +#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ +#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ +#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ +#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ +#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ +#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ +#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ +#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ +#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ +#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ +#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ +#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ +#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ +#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ +#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ +#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ +#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ +#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ +#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ +#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ +#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ +#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ +#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ +#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ +#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ +#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ +#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ +#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ +#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ +#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ +#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ +#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ +#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ +#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ +#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ +#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ +#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ +#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ +#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ +#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ +#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ +#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ +#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ +#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ +#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ +#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ +#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ +#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ +#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ +#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ +#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ +#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ +#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ +#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ +#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ +#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ +#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ +#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ +#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ +#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ +#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ +#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ +#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ +#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ +#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ +#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ +#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ +#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ +#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ +#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ +#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ +#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ +#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ +#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ +#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ +#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ +#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ +#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ +#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ +#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ +#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ +#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ +#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ +#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ +#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ +#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ +#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ +#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ +#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ +#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ +#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ +#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ +#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ +#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ +#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ +#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ +#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ +#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ +#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ +#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ +#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ +#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ +#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ +#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ +#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ +#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ +#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ +#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ +#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ +#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ +#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ +#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ +#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ +#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ +#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ +#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ +#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ +#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ +#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ +#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ +#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ +#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ +#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ +#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ +#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ +#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ +#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ +#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ +#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ +#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ +#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ +#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ +#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ +#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ +#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ +#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ +#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ +#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ +#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ +#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ +#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ +#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ +#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ +#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ +#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ +#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */ +#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ +#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ +#define CHIPID 0xFFC00014 +#define DMA_TC_CNT 0xFFC00B0C +#define DMA_TC_PER 0xFFC00B10 -#if defined(__BFIN_DEF_ADSP_BF537_proc__) || !defined(__BFIN_DEF_ADSP_BF536_proc__) +#if !defined(__ADSPBF536__) #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) @@ -21,11 +827,5 @@ #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF534_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf538/BF538_def.h b/arch/blackfin/include/asm/mach-bf538/BF538_def.h index eae8e8178e..1736dabf09 100644 --- a/arch/blackfin/include/asm/mach-bf538/BF538_def.h +++ b/arch/blackfin/include/asm/mach-bf538/BF538_def.h @@ -1021,11 +1021,5 @@ #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF538_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h index 1aae565fe7..46925f8c07 100644 --- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h +++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h @@ -708,14 +708,9 @@ #define EBIU_SDBCTL 0xFFC00A14 #define EBIU_SDRRC 0xFFC00A18 #define EBIU_SDSTAT 0xFFC00A1C + #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF561_proc__ */ diff --git a/arch/blackfin/include/asm/mach-common/bits/bootrom.h b/arch/blackfin/include/asm/mach-common/bits/bootrom.h index f537e93f70..0e2cacb393 100644 --- a/arch/blackfin/include/asm/mach-common/bits/bootrom.h +++ b/arch/blackfin/include/asm/mach-common/bits/bootrom.h @@ -229,33 +229,65 @@ static uint32_t (* const bfrom_NandBoot)(int32_t dNandAddress, int32_t dFlags, i #endif /* __ASSEMBLY__ */ +/* Bit defines for BF53x block flags */ +#define BFLAG_53X_ZEROFILL 0x0001 +#define BFLAG_53X_RESVECT 0x0002 +#define BFLAG_53X_INIT 0x0008 +#define BFLAG_53X_IGNORE 0x0010 +#define BFLAG_53X_PFLAG_MASK 0x01E0 +#define BFLAG_53X_PFLAG_SHIFT 5 +#define BFLAG_53X_PPORT_MASK 0x0600 +#define BFLAG_53X_PPORT_SHIFT 9 +#define BFLAG_53X_COMPRESSED 0x2000 +#define BFLAG_53X_FINAL 0x8000 + +/* Bit defines for BF56x global header */ +#define GFLAG_56X_16BIT_FLASH 0x00000001 +#define GFLAG_56X_WAIT_MASK 0x0000001E +#define GFLAG_56X_WAIT_SHIFT 1 +#define GFLAG_56X_HOLD_MASK 0x000000C0 +#define GFLAG_56X_HOLD_SHIFT 6 +#define GFLAG_56X_SPI_MASK 0x00000700 +#define GFLAG_56X_SPI_SHIFT 8 +#define GFLAG_56X_SPI_500K 0x0 +#define GFLAG_56X_SPI_1M 0x1 +#define GFLAG_56X_SPI_2M 0x2 +#define GFLAG_56X_SIGN_MASK 0xFF000000 +#define GFLAG_56X_SIGN_SHIFT 28 +#define GFLAG_56X_SIGN_MAGIC 0xA + /* Bit defines for ADI_BOOT_DATA->dFlags */ -#define BFLAG_DMACODE_MASK 0x0000000F -#define BFLAG_SAFE 0x00000010 -#define BFLAG_AUX 0x00000020 -#define BFLAG_FILL 0x00000100 -#define BFLAG_QUICKBOOT 0x00000200 -#define BFLAG_CALLBACK 0x00000400 -#define BFLAG_INIT 0x00000800 -#define BFLAG_IGNORE 0x00001000 -#define BFLAG_INDIRECT 0x00002000 -#define BFLAG_FIRST 0x00004000 -#define BFLAG_FINAL 0x00008000 -#define BFLAG_HOOK 0x00400000 -#define BFLAG_HDRINDIRECT 0x00800000 -#define BFLAG_TYPE_MASK 0x00300000 -#define BFLAG_TYPE_1 0x00000000 -#define BFLAG_TYPE_2 0x00100000 -#define BFLAG_TYPE_3 0x00200000 -#define BFLAG_TYPE_4 0x00300000 -#define BFLAG_FASTREAD 0x00400000 -#define BFLAG_NOAUTO 0x01000000 -#define BFLAG_PERIPHERAL 0x02000000 -#define BFLAG_SLAVE 0x04000000 -#define BFLAG_WAKEUP 0x08000000 -#define BFLAG_NEXTDXE 0x10000000 -#define BFLAG_RETURN 0x20000000 -#define BFLAG_RESET 0x40000000 -#define BFLAG_NONRESTORE 0x80000000 +#define BFLAG_DMACODE_MASK 0x0000000F +#define BFLAG_SAFE 0x00000010 +#define BFLAG_AUX 0x00000020 +#define BFLAG_FILL 0x00000100 +#define BFLAG_QUICKBOOT 0x00000200 +#define BFLAG_CALLBACK 0x00000400 +#define BFLAG_INIT 0x00000800 +#define BFLAG_IGNORE 0x00001000 +#define BFLAG_INDIRECT 0x00002000 +#define BFLAG_FIRST 0x00004000 +#define BFLAG_FINAL 0x00008000 +#define BFLAG_HDRSIGN_MASK 0xFF000000 +#define BFLAG_HDRSIGN_SHIFT 24 +#define BFLAG_HDRSIGN_MAGIC 0xAD +#define BFLAG_HDRCHK_MASK 0x00FF0000 +#define BFLAG_HDRCHK_SHIFT 16 +#define BFLAG_HOOK 0x00400000 +#define BFLAG_HDRINDIRECT 0x00800000 +#define BFLAG_TYPE_MASK 0x00300000 +#define BFLAG_TYPE_1 0x00000000 +#define BFLAG_TYPE_2 0x00100000 +#define BFLAG_TYPE_3 0x00200000 +#define BFLAG_TYPE_4 0x00300000 +#define BFLAG_FASTREAD 0x00400000 +#define BFLAG_NOAUTO 0x01000000 +#define BFLAG_PERIPHERAL 0x02000000 +#define BFLAG_SLAVE 0x04000000 +#define BFLAG_WAKEUP 0x08000000 +#define BFLAG_NEXTDXE 0x10000000 +#define BFLAG_RETURN 0x20000000 +#define BFLAG_RESET 0x40000000 +#define BFLAG_NONRESTORE 0x80000000 #endif diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 8eca7d6fb6..362b8c47ea 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -207,7 +207,6 @@ extern int timer_init(void); void board_init_f(ulong bootflag) { - ulong addr; bd_t *bd; char buf[32]; @@ -244,17 +243,12 @@ void board_init_f(ulong bootflag) gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR); memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); - /* Board data initialization */ - addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t)); - - /* Align to 4 byte boundary */ - addr &= ~(4 - 1); - bd = (bd_t *) addr; + bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR); gd->bd = bd; - memset((void *)bd, 0, sizeof(bd_t)); + memset((void *)bd, 0, GENERATED_BD_INFO_SIZE); bd->bi_r_version = version_string; - bd->bi_cpu = BFIN_CPU; + bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU); bd->bi_board_name = BFIN_BOARD_NAME; bd->bi_vco = get_vco(); bd->bi_cclk = get_cclk(); @@ -283,8 +277,11 @@ void board_init_f(ulong bootflag) printf("Core: %s MHz, ", strmhz(buf, get_cclk())); printf("System: %s MHz\n", strmhz(buf, get_sclk())); - printf("RAM: "); - print_size(bd->bi_memsize, "\n"); + if (CONFIG_MEM_SIZE) { + printf("RAM: "); + print_size(bd->bi_memsize, "\n"); + } + #if defined(CONFIG_POST) post_init_f(); post_bootmode_init(); @@ -393,7 +390,7 @@ void board_init_r(gd_t * id, ulong dest_addr) post_run(NULL, POST_RAM | post_bootmode_get(0)); #endif - if (bfin_os_log_check()) { + if (CONFIG_MEM_SIZE && bfin_os_log_check()) { puts("\nLog buffer from operating system:\n"); bfin_os_log_dump(); puts("\n"); diff --git a/arch/blackfin/lib/u-boot.lds.S b/arch/blackfin/lib/u-boot.lds.S index f15c97ed0c..2b8d285e1f 100644 --- a/arch/blackfin/lib/u-boot.lds.S +++ b/arch/blackfin/lib/u-boot.lds.S @@ -40,9 +40,13 @@ * This is here in the first place so we can quickly test building * for different CPU's which may lack non-cache L1 data. */ +#ifndef L1_DATA_A_SRAM +# define L1_DATA_A_SRAM 0 +# define L1_DATA_A_SRAM_SIZE 0 +#endif #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE -# define L1_DATA_B_SRAM_SIZE 0 +# define L1_DATA_B_SRAM L1_DATA_A_SRAM +# define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE #endif /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ @@ -138,7 +142,7 @@ SECTIONS } >l1_data AT>ram_data __data_l1_lma = LOADADDR(.data_l1); __data_l1_len = SIZEOF(.data_l1); - ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!") + ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!") .bss : { diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index 749c38968a..863f3ddbc6 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -24,7 +24,7 @@ CROSS_COMPILE ?= m68k-elf- clibdir = $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) -STANDALONE_LOAD_ADDR = 0x20000 -L $(clibdir) +CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 -L $(clibdir) PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__ PLATFORM_LDFLAGS += -n diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index f824b34252..6a892db649 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -277,9 +277,13 @@ board_init_f (ulong bootflag) debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); #ifdef CONFIG_LCD +#ifdef CONFIG_FB_ADDR + gd->fb_base = CONFIG_FB_ADDR; +#else /* reserve memory for LCD display (always full pages) */ addr = lcd_setmem (addr); gd->fb_base = addr; +#endif /* CONFIG_FB_ADDR */ #endif /* CONFIG_LCD */ /* diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index 76a2fb27c1..1229ac7f25 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -71,7 +71,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima int ret; ulong cmd_start, cmd_end; - ulong bootmap_base; bd_t *kbd; void (*kernel) (bd_t *, ulong, ulong, ulong, ulong); struct lmb *lmb = &images->lmb; @@ -79,17 +78,15 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; - bootmap_base = getenv_bootm_low(); - /* allocate space and init command line */ - ret = boot_get_cmdline (lmb, &cmd_start, &cmd_end, bootmap_base); + ret = boot_get_cmdline (lmb, &cmd_start, &cmd_end); if (ret) { puts("ERROR with allocation of cmdline\n"); goto error; } /* allocate space for kernel copy of board info */ - ret = boot_get_kbd (lmb, &kbd, bootmap_base); + ret = boot_get_kbd (lmb, &kbd); if (ret) { puts("ERROR with allocation of kernel bd\n"); goto error; diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index c3c9f958c0..abea70bb0d 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -26,6 +26,6 @@ CROSS_COMPILE ?= mb- -STANDALONE_LOAD_ADDR = 0x80F00000 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ diff --git a/arch/mips/config.mk b/arch/mips/config.mk index aa06761ae3..318d34b1e6 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,7 +23,7 @@ CROSS_COMPILE ?= mips_4KC- -STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/mips32/Makefile index 06df8d17a8..e315c1bb8c 100644 --- a/arch/mips/cpu/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -29,11 +29,6 @@ START = start.o SOBJS-y = cache.o COBJS-y = cpu.o interrupts.o -SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o -COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o -COBJS-$(CONFIG_PURPLE) += asc_serial.o -COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o - SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) START := $(addprefix $(obj),$(START)) diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/cpu/mips32/au1x00/Makefile new file mode 100644 index 0000000000..dc58475f68 --- /dev/null +++ b/arch/mips/cpu/mips32/au1x00/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/mips/cpu/au1x00_eth.c b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c index c51079961c..c51079961c 100644 --- a/arch/mips/cpu/au1x00_eth.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c diff --git a/arch/mips/cpu/au1x00_serial.c b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c index c25ba5a5b3..c25ba5a5b3 100644 --- a/arch/mips/cpu/au1x00_serial.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c diff --git a/arch/mips/cpu/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c index 0bc2305d87..0bc2305d87 100644 --- a/arch/mips/cpu/au1x00_usb_ohci.c +++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c diff --git a/arch/mips/cpu/au1x00_usb_ohci.h b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h index bb9f351099..bb9f351099 100644 --- a/arch/mips/cpu/au1x00_usb_ohci.h +++ b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h diff --git a/arch/mips/cpu/mips32/au1x00/config.mk b/arch/mips/cpu/mips32/au1x00/config.mk new file mode 100644 index 0000000000..568f33356b --- /dev/null +++ b/arch/mips/cpu/mips32/au1x00/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -mtune=4kc diff --git a/arch/mips/cpu/cache.S b/arch/mips/cpu/mips32/cache.S index 4b30c89b14..296593805a 100644 --- a/arch/mips/cpu/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -311,11 +311,7 @@ LEAF(dcache_enable) * RETURNS: N/A * */ -#if defined(CONFIG_PURPLE) -# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2) -#else # define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE) -#endif .globl mips_cache_lock .ent mips_cache_lock mips_cache_lock: diff --git a/arch/mips/cpu/config.mk b/arch/mips/cpu/mips32/config.mk index a173c5480c..4d1b27379d 100644 --- a/arch/mips/cpu/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -20,13 +20,14 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) -MIPSFLAGS:=$(shell \ -if [ "$v" -lt "14" ]; then \ - echo "-mcpu=4kc"; \ -else \ - echo "-march=4kc -mtune=4kc"; \ -fi) + +# +# Default optimization level for MIPS32 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips32r2 ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) ENDIANNESS = -EL diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/mips32/cpu.c index 3ae397c8ef..3ae397c8ef 100644 --- a/arch/mips/cpu/cpu.c +++ b/arch/mips/cpu/mips32/cpu.c diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile new file mode 100644 index 0000000000..9c2b1aa86c --- /dev/null +++ b/arch/mips/cpu/mips32/incaip/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS = incaip_wdt.o +COBJS = incaip_clock.o asc_serial.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/mips/cpu/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c index be686c2ae8..7239804b9d 100644 --- a/arch/mips/cpu/asc_serial.c +++ b/arch/mips/cpu/mips32/incaip/asc_serial.c @@ -3,47 +3,10 @@ */ #include <config.h> - -#ifdef CONFIG_PURPLE -#define serial_init asc_serial_init -#define serial_putc asc_serial_putc -#define serial_puts asc_serial_puts -#define serial_getc asc_serial_getc -#define serial_tstc asc_serial_tstc -#define serial_setbrg asc_serial_setbrg -#endif - #include <common.h> #include <asm/inca-ip.h> #include "asc_serial.h" -#ifdef CONFIG_PURPLE - -#undef ASC_FIFO_PRESENT -#define TOUT_LOOP 100000 - -/* Set base address for second FPI interrupt control register bank */ -#define SFPI_INTCON_BASEADDR 0xBF0F0000 - -/* Register offset from base address */ -#define FBS_ISR 0x00000000 /* Interrupt status register */ -#define FBS_IMR 0x00000008 /* Interrupt mask register */ -#define FBS_IDIS 0x00000010 /* Interrupt disable register */ - -/* Interrupt status register bits */ -#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */ -#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ -#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */ -#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */ -#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ -#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */ - -#else - -#define ASC_FIFO_PRESENT - -#endif - #define SET_BIT(reg, mask) reg |= (mask) #define CLEAR_BIT(reg, mask) reg &= (~mask) @@ -71,10 +34,8 @@ static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC; int serial_init (void) { -#ifdef CONFIG_INCA_IP /* we have to set PMU.EN13 bit to enable an ASC device*/ INCAASC_PMU_ENABLE(13); -#endif /* and we have to set CLC register*/ CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); @@ -86,7 +47,6 @@ int serial_init (void) /* select input port */ pAsc->asc_pisel = (CONSOLE_TTY & 0x1); -#ifdef ASC_FIFO_PRESENT /* TXFIFO's filling level */ SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); @@ -98,25 +58,20 @@ int serial_init (void) ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); /* enable RXFIFO */ SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); -#endif /* enable error signals */ SET_BIT(pAsc->asc_con, ASCCON_FEN); SET_BIT(pAsc->asc_con, ASCCON_OEN); -#ifdef CONFIG_INCA_IP /* acknowledge ASC interrupts */ ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); /* disable ASC interrupts */ ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); -#endif -#ifdef ASC_FIFO_PRESENT /* set FIFOs into the transparent mode */ SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); -#endif /* set baud rate */ serial_setbrg(); @@ -132,11 +87,7 @@ void serial_setbrg (void) ulong uiReloadValue, fdv; ulong f_ASC; -#ifdef CONFIG_INCA_IP f_ASC = incaip_get_fpiclk(); -#else - f_ASC = ASC_CLOCK_RATE; -#endif #ifndef INCAASC_USE_FDV fdv = 2; @@ -261,15 +212,10 @@ static int serial_setopt (void) void serial_putc (const char c) { -#ifdef ASC_FIFO_PRESENT uint txFl = 0; -#else - uint timeout = 0; -#endif if (c == '\n') serial_putc ('\r'); -#ifdef ASC_FIFO_PRESENT /* check do we have a free space in the TX FIFO */ /* get current filling level */ do @@ -277,25 +223,9 @@ void serial_putc (const char c) txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; } while ( txFl == INCAASC_TXFIFO_FULL ); -#else - - while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & - FBS_ISR_AB)) - { - if (timeout++ > TOUT_LOOP) - { - break; - } - } -#endif pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ -#ifndef ASC_FIFO_PRESENT - *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB | - FBS_ISR_AT; -#endif - /* check for errors */ if ( pAsc->asc_con & ASCCON_OE ) { @@ -324,10 +254,6 @@ int serial_getc (void) c = (char)(pAsc->asc_rbuf & symbol_mask); -#ifndef ASC_FIFO_PRESENT - *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR; -#endif - return c; } @@ -335,19 +261,10 @@ int serial_tstc (void) { int res = 1; -#ifdef ASC_FIFO_PRESENT if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) { res = 0; } -#else - if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & - FBS_ISR_AR)) - - { - res = 0; - } -#endif else if ( pAsc->asc_con & ASCCON_FE ) { SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); diff --git a/arch/mips/cpu/asc_serial.h b/arch/mips/cpu/mips32/incaip/asc_serial.h index 7ffdcfaf8b..7ffdcfaf8b 100644 --- a/arch/mips/cpu/asc_serial.h +++ b/arch/mips/cpu/mips32/incaip/asc_serial.h diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk new file mode 100644 index 0000000000..568f33356b --- /dev/null +++ b/arch/mips/cpu/mips32/incaip/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2011 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -mtune=4kc diff --git a/arch/mips/cpu/incaip_clock.c b/arch/mips/cpu/mips32/incaip/incaip_clock.c index b65dfe0e1a..b65dfe0e1a 100644 --- a/arch/mips/cpu/incaip_clock.c +++ b/arch/mips/cpu/mips32/incaip/incaip_clock.c diff --git a/arch/mips/cpu/incaip_wdt.S b/arch/mips/cpu/mips32/incaip/incaip_wdt.S index 3ade3cd6fd..3ade3cd6fd 100644 --- a/arch/mips/cpu/incaip_wdt.S +++ b/arch/mips/cpu/mips32/incaip/incaip_wdt.S diff --git a/arch/mips/cpu/interrupts.c b/arch/mips/cpu/mips32/interrupts.c index 87f7a9f7e6..87f7a9f7e6 100644 --- a/arch/mips/cpu/interrupts.c +++ b/arch/mips/cpu/mips32/interrupts.c diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/mips32/start.S index d6bcef6b56..e661d4625f 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -67,9 +67,6 @@ _start: #if defined(CONFIG_INCA_IP) .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ .word 0x00000000 /* phase of the flash */ -#elif defined(CONFIG_PURPLE) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ #else RVECENT(romReserved,2) #endif @@ -203,30 +200,6 @@ _start: * 128 * 8 == 1024 == 0x400 * so this is address R_VEC+0x400 == 0xbfc00400 */ -#ifdef CONFIG_PURPLE -/* 0xbfc00400 */ - .word 0xdc870000 - .word 0xfca70000 - .word 0x20840008 - .word 0x20a50008 - .word 0x20c6ffff - .word 0x14c0fffa - .word 0x00000000 - .word 0x03e00008 - .word 0x00000000 - .word 0x00000000 -/* 0xbfc00428 */ - .word 0xdc870000 - .word 0xfca70000 - .word 0x20840008 - .word 0x20a50008 - .word 0x20c6ffff - .word 0x14c0fffa - .word 0x00000000 - .word 0x03e00008 - .word 0x00000000 - .word 0x00000000 -#endif /* CONFIG_PURPLE */ .align 4 reset: @@ -337,17 +310,12 @@ relocate_code: move a0, t1 /* a0 <-- destination addr */ sub a1, t2, t0 /* a1 <-- size */ - /* On the purple board we copy the code earlier in a special way - * in order to solve flash problems - */ -#ifndef CONFIG_PURPLE 1: lw t3, 0(t0) sw t3, 0(t1) addu t0, 4 ble t0, t2, 1b addu t1, 4 /* delay slot */ -#endif /* If caches were enabled, we would have to flush them here. */ diff --git a/arch/mips/include/asm/inca-ip.h b/arch/mips/include/asm/inca-ip.h index e787a1dee6..26f100290c 100644 --- a/arch/mips/include/asm/inca-ip.h +++ b/arch/mips/include/asm/inca-ip.h @@ -894,12 +894,7 @@ /* Module : EBU register address and bits */ /***********************************************************************/ -#if defined(CONFIG_INCA_IP) #define INCA_IP_EBU (0xB8000200) -#elif defined(CONFIG_PURPLE) -#define INCA_IP_EBU (0xB800D800) -#endif - /***********************************************************************/ @@ -1495,12 +1490,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not /* Module : ASC register address and bits */ /***********************************************************************/ -#if defined(CONFIG_INCA_IP) #define INCA_IP_ASC (0xB8000400) -#elif defined(CONFIG_PURPLE) -#define INCA_IP_ASC (0xBE500000) -#endif - /***********************************************************************/ diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index f317124155..623c4d7f0d 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -162,9 +162,6 @@ void board_init_f(ulong bootflag) init_fnc_t **init_fnc_ptr; ulong addr, addr_sp, len = (ulong)&uboot_end - CONFIG_SYS_MONITOR_BASE; ulong *s; -#ifdef CONFIG_PURPLE - void copy_code (ulong); -#endif /* Pointer is writable since we allocated a register for it. */ @@ -253,13 +250,6 @@ void board_init_f(ulong bootflag) memcpy (id, (void *)gd, sizeof (gd_t)); - /* On the purple board we copy the code in a special way - * in order to solve flash problems - */ -#ifdef CONFIG_PURPLE - copy_code(addr); -#endif - relocate_code (addr_sp, id, addr); /* NOTREACHED - relocate_code() does not return */ diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index d241a96e8e..e58ea24d2c 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -29,7 +29,5 @@ STANDALONE_LOAD_ADDR ?= 0x02000000 PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__ PLATFORM_CPPFLAGS += -G0 -LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds - LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 31e44160f6..a30715459d 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -23,23 +23,12 @@ CROSS_COMPILE ?= ppc_8xx- -STANDALONE_LOAD_ADDR = 0x40000 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections -PLATFORM_RELFLAGS += -mrelocatable -ffunction-sections -fdata-sections +PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n -ifdef CONFIG_SYS_LDSCRIPT -# need to strip off double quotes -LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) -else ifdef CONFIG_NAND_SPL -LDSCRIPT := $(SRCTREE)/$(CONFIG_BOARDDIR)/u-boot-nand.lds -else -ifneq ($(wildcard $(SRCTREE)/arch/powerpc/cpu/$(CPU)/u-boot.lds),) -LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/$(CPU)/u-boot.lds -endif -endif - # # When cross-compiling on NetBSD, we have to define __PPC__ or else we # will pick up a va_list declaration that is incompatible with the diff --git a/arch/powerpc/cpu/74xx_7xx/config.mk b/arch/powerpc/cpu/74xx_7xx/config.mk index df1f6acedf..fb0c7158ca 100644 --- a/arch/powerpc/cpu/74xx_7xx/config.mk +++ b/arch/powerpc/cpu/74xx_7xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/arch/powerpc/cpu/mpc512x/config.mk b/arch/powerpc/cpu/mpc512x/config.mk index baf55ccaaf..8fcededf26 100644 --- a/arch/powerpc/cpu/mpc512x/config.mk +++ b/arch/powerpc/cpu/mpc512x/config.mk @@ -20,7 +20,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ -ffixed-r2 -msoft-float -mcpu=603e diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c index c4108af336..9dc1e48256 100644 --- a/arch/powerpc/cpu/mpc512x/diu.c +++ b/arch/powerpc/cpu/mpc512x/diu.c @@ -51,20 +51,10 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); } -int platform_diu_init(unsigned int *xres, unsigned int *yres) +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) { - unsigned int pixel_format; - -#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES) - *xres = CONFIG_VIDEO_XRES; - *yres = CONFIG_VIDEO_YRES; -#else - *xres = 1024; - *yres = 768; -#endif - pixel_format = 0x88883316; + unsigned int pixel_format = 0x88883316; debug("mpc5121_diu_init\n"); - - return fsl_diu_init(*xres, pixel_format, 0); + return fsl_diu_init(xres, pixel_format, 0); } diff --git a/arch/powerpc/cpu/mpc5xx/config.mk b/arch/powerpc/cpu/mpc5xx/config.mk index 1c7df0005c..ab55040e5a 100644 --- a/arch/powerpc/cpu/mpc5xx/config.mk +++ b/arch/powerpc/cpu/mpc5xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float diff --git a/arch/powerpc/cpu/mpc5xxx/config.mk b/arch/powerpc/cpu/mpc5xxx/config.mk index 832909fbb3..fb879809c8 100644 --- a/arch/powerpc/cpu/mpc5xxx/config.mk +++ b/arch/powerpc/cpu/mpc5xxx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc8220/config.mk b/arch/powerpc/cpu/mpc8220/config.mk index 9142b91a5d..2c638b5c53 100644 --- a/arch/powerpc/cpu/mpc8220/config.mk +++ b/arch/powerpc/cpu/mpc8220/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc824x/config.mk b/arch/powerpc/cpu/mpc824x/config.mk index 65a177133a..82b8cc657d 100644 --- a/arch/powerpc/cpu/mpc824x/config.mk +++ b/arch/powerpc/cpu/mpc824x/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float diff --git a/arch/powerpc/cpu/mpc8260/config.mk b/arch/powerpc/cpu/mpc8260/config.mk index 5e4645a025..f091fa971b 100644 --- a/arch/powerpc/cpu/mpc8260/config.mk +++ b/arch/powerpc/cpu/mpc8260/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple diff --git a/arch/powerpc/cpu/mpc83xx/config.mk b/arch/powerpc/cpu/mpc83xx/config.mk index 0dced88add..a79729e019 100644 --- a/arch/powerpc/cpu/mpc83xx/config.mk +++ b/arch/powerpc/cpu/mpc83xx/config.mk @@ -20,7 +20,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \ -ffixed-r2 -msoft-float diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index daf73a6e5a..028c8f0d58 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && \ + (defined(CONFIG_QE)) #include <asm/immap_qe.h> void fdt_fixup_muram (void *blob) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index cbb0fc6bbd..d61d34c905 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -55,9 +55,13 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_P1013) += ddr-gen3.o COBJS-$(CONFIG_P1014) += ddr-gen3.o +COBJS-$(CONFIG_P1015) += ddr-gen3.o +COBJS-$(CONFIG_P1016) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P1021) += ddr-gen3.o COBJS-$(CONFIG_P1022) += ddr-gen3.o +COBJS-$(CONFIG_P1024) += ddr-gen3.o +COBJS-$(CONFIG_P1025) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o @@ -69,7 +73,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_CORENET) += liodn.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_FSL_CORENET) += portals.o +COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o @@ -87,12 +91,20 @@ COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o +COBJS-$(CONFIG_P1010) += p1010_serdes.o COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1022_serdes.o +COBJS-$(CONFIG_P1014) += p1010_serdes.o +COBJS-$(CONFIG_P1015) += p1021_serdes.o +COBJS-$(CONFIG_P1016) += p1021_serdes.o +COBJS-$(CONFIG_P1017) += p1023_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o +COBJS-$(CONFIG_P1023) += p1023_serdes.o +COBJS-$(CONFIG_P1024) += p1021_serdes.o +COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index e94975a1c6..7b9f77362c 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -44,6 +44,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) puts("Work-around for Erratum SERDES8 enabled\n"); #endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) + puts("Work-around for Erratum SERDES9 enabled\n"); +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) + puts("Work-around for Erratum SERDES-A005 enabled\n"); +#endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk index 66d1741cc1..68ac57dd0d 100644 --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 1aad2ba925..f863f4aad0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -33,6 +33,7 @@ #include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/fsl_ifc.h> #include <asm/fsl_law.h> #include <asm/fsl_lbc.h> #include <post.h> @@ -233,13 +234,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * Get timebase clock frequency */ +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif unsigned long get_tbclk (void) { -#ifdef CONFIG_FSL_CORENET - return (gd->bus_clk + 8) / 16; -#else - return (gd->bus_clk + 4UL)/8UL; -#endif + unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; + + return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; } @@ -280,7 +282,8 @@ int cpu_mmc_init(bd_t *bis) /* * Print out the state of various machine registers. - * Currently prints out LAWs, BR0/OR0, and TLBs + * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing + * parameters for IFC and TLBs */ void mpc85xx_reginfo(void) { @@ -289,11 +292,24 @@ void mpc85xx_reginfo(void) #if defined(CONFIG_FSL_LBC) print_lbc_regs(); #endif +#ifdef CONFIG_FSL_IFC + print_ifc_regs(); +#endif } /* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR) +phys_size_t initdram(int board_type) +{ +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) + return fsl_ddr_sdram_size(); +#else + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif +} +#else /* CONFIG_SYS_RAMBOOT */ phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; @@ -343,6 +359,7 @@ phys_size_t initdram(int board_type) puts("DDR: "); return dram_size; } +#endif /* CONFIG_SYS_RAMBOOT */ #endif #if CONFIG_POST & CONFIG_SYS_POST_MEMORY diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 8ece970097..b3da970d42 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,10 @@ #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include "mp.h" +#ifdef CONFIG_SYS_QE_FW_IN_NAND +#include <nand.h> +#include <errno.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -141,6 +145,22 @@ static void enable_cpc(void) for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); +#ifdef CONFIG_RAMBOOT_PBL + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { + /* find and disable LAW of SRAM */ + struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + + if (law.index == -1) { + printf("\nFatal error happened\n"); + return; + } + disable_law(law.index); + + clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); + out_be32(&cpc->cpccsr0, 0); + out_be32(&cpc->cpcsrcr0, 0); + } +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); @@ -164,6 +184,9 @@ void invalidate_cpc(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* skip CPC when it used as all SRAM */ + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) + continue; /* Flash invalidate the CPC and clear all the locks */ out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) @@ -384,12 +407,6 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE - uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ - qe_init(qe_base); - qe_reset(); -#endif - /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); @@ -419,6 +436,23 @@ int cpu_init_r(void) isync(); #endif +#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy1 = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + out_be32(&usb_phy1->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif +#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy2 = + (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; + out_be32(&usb_phy2->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif + return 0; } @@ -449,3 +483,25 @@ int sata_initialize(void) return 1; } #endif + +void cpu_secondary_init_r(void) +{ +#ifdef CONFIG_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ +#ifdef CONFIG_SYS_QE_FW_IN_NAND + int ret; + size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; + + /* load QE firmware from NAND flash to DDR first */ + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + + if (ret && ret == -EUCLEAN) { + printf ("NAND read for QE firmware at offset %x failed %d\n", + CONFIG_SYS_QE_FW_IN_NAND, ret); + } +#endif + qe_init(qe_base); + qe_reset(); +#endif +} diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 8fb27abc55..796d398426 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -33,17 +33,15 @@ void cpu_init_f(void) */ out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); -#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_NAND_OR_PRELIM); +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); #else -#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined #endif #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; - char *l2srbar; - int i; out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); @@ -54,10 +52,5 @@ void cpu_init_f(void) /* set L2E=1 & L2SRAM=001 */ out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); - - /* Initialize L2 SRAM to zero */ - l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR; - for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) - l2srbar[i] = 0; #endif } diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 00fa752996..6e909b52d0 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -338,6 +338,9 @@ void fdt_add_enet_stashing(void *fdt) do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); + do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); } #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) @@ -470,6 +473,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_portal(blob, "fsl,bman-portal", "bman-portals", (u64)CONFIG_SYS_BMAN_MEM_PHYS, CONFIG_SYS_BMAN_MEM_SIZE); + fdt_fixup_bportals(blob); #endif #if defined(CONFIG_SYS_QMAN_MEM_PHYS) @@ -483,4 +487,13 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_SRIO ft_srio_setup(blob); #endif + + /* + * system-clock = CCB clock/2 + * Here gd->bus_clk = CCB clock + * We are using the system clock as 1588 Timer reference + * clock source select + */ + do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", + "timer-frequency", gd->bus_clk/2, 1); } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 7fc00d8c6f..741a0f84aa 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -29,6 +29,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/fsl_law.h> +#include <asm/errno.h> #include "fsl_corenet_serdes.h" static u32 serdes_prtcl_map; @@ -91,7 +92,7 @@ int serdes_get_lane_idx(int lane) return lanes[lane].idx; } -int serdes_get_bank(int lane) +int serdes_get_bank_by_lane(int lane) { return lanes[lane].bank; } @@ -109,10 +110,13 @@ int serdes_lane_enabled(int lane) return 0; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (!IS_SVR_REV(get_svr(), 1, 0)) - if (bank > 0) - return !(srds_lpd_b[bank] & - (8 >> (lane - (6 + 4 * bank)))); + /* + * For banks two and three, use the srds_lpd_b[] array instead of the + * RCW, because this array contains the real values of SRDS_LPD_B2 and + * SRDS_LPD_B3. + */ + if (bank > 0) + return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); #endif return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); @@ -129,6 +133,125 @@ int is_serdes_configured(enum srds_prtcl device) return (1 << device) & serdes_prtcl_map; } +static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) +{ + int i; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(prtcl, i) == device) + return i; + } + + return -ENODEV; +} + +/* + * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given + * device. This depends on the current SERDES protocol, as defined in the RCW. + * + * Returns a negative error code if SERDES is disabled or the given device is + * not supported in the current SERDES protocol. + */ +int serdes_get_first_lane(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return -ENODEV; + + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + return __serdes_get_first_lane(prtcl, device); +} + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +/* + * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given + * SERDES protocol. + * + * Returns a negative error code if the given device is not supported for the + * given SERDES protocol. + */ +static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device) +{ + int lane; + + lane = __serdes_get_first_lane(prtcl, device); + if (unlikely(lane < 0)) + return lane; + + return serdes_get_bank_by_lane(lane); +} + +static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device, + int first) +{ + int lane; + + for (lane = first; lane < SRDS_MAX_LANES; lane++) { + if (serdes_get_prtcl(prtcl, lane) != device) + break; + } + + return lane - first; +} + +static void __serdes_reset_rx(serdes_corenet_t *regs, + uint32_t prtcl, + enum srds_prtcl device) +{ + int lane, idx, first, last; + + lane = __serdes_get_first_lane(prtcl, device); + if (unlikely(lane < 0)) + return; + first = serdes_get_lane_idx(lane); + last = first + __serdes_get_lane_count(prtcl, device, lane); + + /* + * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is + * selected as XAUI to place the lane into reset. + */ + for (idx = first; idx < last; idx++) + clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); + + /* Wait at least 250 ns */ + udelay(1); + + /* + * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is + * selected as XAUI to bring the lane out of reset. + */ + for (idx = first; idx < last; idx++) + setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); +} + +void serdes_reset_rx(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + serdes_corenet_t *regs; + + if (unlikely(device == NONE)) + return; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return; + + regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + __serdes_reset_rx(regs, prtcl, device); +} +#endif + #ifndef CONFIG_SYS_DCSRBAR_PHYS #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ #define CONFIG_SYS_DCSRBAR 0x80000000 @@ -263,6 +386,74 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, } #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +/* + * If PCIe is not selected as a protocol for any lanes driven by a given PLL, + * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. + */ +static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) +{ + enum srds_prtcl device; + + switch (cfg) { + case 0x13: + case 0x16: + /* + * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] + * to 0. + */ + clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + case 0x19: + /* + * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and + * SRDSB3PLLCR1[PLLBW_SEL] to 1. + */ + clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + } + + /* + * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI + * before XAUI is initialized. + */ + for (device = XAUI_FM1; device <= XAUI_FM2; device++) { + if (is_serdes_configured(device)) { + int bank = serdes_get_bank_by_device(cfg, device); + + clrbits_be32(®s->bank[bank].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + } + } +} +#endif + +/* + * Wait for the RSTDONE bit to get set, or a one-second timeout. + */ +static void wait_for_rstdone(unsigned int bank) +{ + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned long long end_tick; + u32 rstctl; + + /* wait for reset complete or 1-second timeout */ + end_tick = usec2ticks(1000000) + get_ticks(); + do { + rstctl = in_be32(&srds_regs->bank[bank].rstctl); + if (rstctl & SRDS_RSTCTL_RSTDONE) + break; + } while (end_tick > get_ticks()); + + if (!(rstctl & SRDS_RSTCTL_RSTDONE)) + printf("SERDES: timeout resetting bank %u\n", bank); +} + void fsl_serdes_init(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -270,7 +461,6 @@ void fsl_serdes_init(void) serdes_corenet_t *srds_regs; int lane, bank, idx; enum srds_prtcl lane_prtcl; - long long end_tick; int have_bank[SRDS_MAX_BANK] = {}; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 u32 serdes8_devdisr = 0; @@ -279,6 +469,12 @@ void fsl_serdes_init(void) const char *srds_lpd_arg; size_t arglen; #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + enum srds_prtcl device; +#endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ +#endif char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; @@ -303,60 +499,76 @@ void fsl_serdes_init(void) } #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (!IS_SVR_REV(get_svr(), 1, 0)) - for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { - sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); - srds_lpd_arg = hwconfig_subarg_f("serdes", srds_lpd_opt, - &arglen, buf); - if (srds_lpd_arg) - srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg, - NULL, 0); - } + /* + * Display a warning if banks two and three are not disabled in the RCW, + * since our work-around for SERDES8 depends on these banks being + * disabled at power-on. + */ +#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3) + if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) { + printf("Warning: SERDES8 requires banks two and " + "three to be disabled in the RCW\n"); + } + + /* + * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 + * hwconfig options into the srds_lpd_b[] array. See README.p4080ds + * for a description of these options. + */ + for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { + sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); + srds_lpd_arg = + hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf); + if (srds_lpd_arg) + srds_lpd_b[bank] = + simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; + } #endif /* Look for banks with all lanes disabled, and power down the bank. */ for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); if (serdes_lane_enabled(lane)) { - have_bank[serdes_get_bank(lane)] = 1; + have_bank[serdes_get_bank_by_lane(lane)] = 1; serdes_prtcl_map |= (1 << lane_prtcl); } } #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (IS_SVR_REV(get_svr(), 1, 0)) { - /* At least one bank must be disabled due to SERDES8. If - * no bank is found to be disabled based on lane - * disables, disable bank 3 because we can't turn off its - * lanes in the RCW without disabling MDIO due to erratum - * GEN8. - * - * This means that if you are relying on bank 3 being - * disabled to avoid SERDES8, in some cases you cannot - * also disable all lanes of another bank, or else bank - * 3 won't be disabled, leaving you with a configuration - * that isn't valid according to SERDES8 (e.g. if banks - * 2 and 3 have the same clock, and bank 1 is disabled - * instead of 3). - */ - for (bank = 0; bank < SRDS_MAX_BANK; bank++) { - if (!have_bank[bank]) - break; - } + /* + * Bank two uses the clock from bank three, so if bank two is enabled, + * then bank three must also be enabled. + */ + if (have_bank[FSL_SRDS_BANK_2]) + have_bank[FSL_SRDS_BANK_3] = 1; +#endif - if (bank == SRDS_MAX_BANK) - have_bank[FSL_SRDS_BANK_3] = 0; - } else { - if (have_bank[FSL_SRDS_BANK_2]) - have_bank[FSL_SRDS_BANK_3] = 1; - } +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * The work-aroud for erratum SERDES-A001 is needed only if bank two + * is disabled and bank three is enabled. + */ + need_serdes_a001 = + !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; #endif + /* Power down the banks we're not interested in */ for (bank = 0; bank < SRDS_MAX_BANK; bank++) { if (!have_bank[bank]) { printf("SERDES: bank %d disabled\n", bank + 1); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * Erratum SERDES-A001 says bank two needs to be powered + * down after bank three is powered up, so don't power + * down bank two here. + */ + if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) + setbits_be32(&srds_regs->bank[bank].rstctl, + SRDS_RSTCTL_SDPD); +#else setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_SDPD); +#endif } } @@ -382,6 +594,35 @@ void fsl_serdes_init(void) printf("%s ", serdes_prtcl_str[lane_prtcl]); #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + /* + * Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for + * each of the SerDes lanes selected as SGMII, XAUI, SRIO, or + * AURORA before the device is initialized. + */ + switch (lane_prtcl) { + case SGMII_FM1_DTSEC1: + case SGMII_FM1_DTSEC2: + case SGMII_FM1_DTSEC3: + case SGMII_FM1_DTSEC4: + case SGMII_FM2_DTSEC1: + case SGMII_FM2_DTSEC2: + case SGMII_FM2_DTSEC3: + case SGMII_FM2_DTSEC4: + case XAUI_FM1: + case XAUI_FM2: + case SRIO1: + case SRIO2: + case AURORA: + clrsetbits_be32(&srds_regs->lane[idx].ttlcr0, + SRDS_TTLCR0_FLT_SEL_MASK, + SRDS_TTLCR0_FLT_SEL_750PPM | + SRDS_TTLCR0_PM_DIS); + default: + break; + } +#endif + #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 switch (lane_prtcl) { case PCIE1: @@ -428,13 +669,12 @@ void fsl_serdes_init(void) FSL_CORENET_DEVDISR2_DTSEC2_4; break; case XAUI_FM1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_10GEC1; + break; case XAUI_FM2: - if (lane_prtcl == XAUI_FM1) - serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | - FSL_CORENET_DEVDISR2_10GEC1; - else - serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | - FSL_CORENET_DEVDISR2_10GEC2; + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_10GEC2; break; case AURORA: break; @@ -449,25 +689,24 @@ void fsl_serdes_init(void) puts("\n"); #endif - for (idx = 0; idx < SRDS_MAX_BANK; idx++) { - u32 rstctl; +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 + p4080_erratum_serdes_a005(srds_regs, cfg); +#endif + for (idx = 0; idx < SRDS_MAX_BANK; idx++) { bank = idx; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (!IS_SVR_REV(get_svr(), 1, 0)) { - /* - * Change bank init order to 0, 2, 1, so that the - * third bank's PLL is established before we - * start the second bank which shares the third - * bank's PLL. - */ + /* + * Change bank init order to 0, 2, 1, so that the third bank's + * PLL is established before we start the second bank. The + * second bank uses the third bank's PLL. + */ - if (idx == 1) - bank = FSL_SRDS_BANK_3; - else if (idx == 2) - bank = FSL_SRDS_BANK_2; - } + if (idx == 1) + bank = FSL_SRDS_BANK_3; + else if (idx == 2) + bank = FSL_SRDS_BANK_2; #endif /* Skip disabled banks */ @@ -475,32 +714,48 @@ void fsl_serdes_init(void) continue; #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 - if (!IS_SVR_REV(get_svr(), 1, 0)) { - if (idx == 1) { - p4080_erratum_serdes8(srds_regs, gur, - serdes8_devdisr, - serdes8_devdisr2, cfg); - } else if (idx == 2) { - enable_bank(gur, FSL_SRDS_BANK_2); - } + if (idx == 1) { + /* + * Re-enable devices on banks two and three that were + * disabled by the RCW, and then enable bank three. The + * devices need to be enabled before either bank is + * powered up. + */ + p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, + serdes8_devdisr2, cfg); + } else if (idx == 2) { + /* Eable bank two now that bank three is enabled. */ + enable_bank(gur, FSL_SRDS_BANK_2); } #endif /* reset banks for errata */ setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST); - /* wait for reset complete or 1-second timeout */ - end_tick = usec2ticks(1000000) + get_ticks(); - do { - rstctl = in_be32(&srds_regs->bank[bank].rstctl); - if (rstctl & SRDS_RSTCTL_RSTDONE) - break; - } while (end_tick > get_ticks()); - - if (!(rstctl & SRDS_RSTCTL_RSTDONE)) { - printf("SERDES: timeout resetting bank %d\n", - bank + 1); - continue; - } + wait_for_rstdone(bank); } + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + if (need_serdes_a001) { + /* + * Bank three has been enabled, so enable bank two and then + * disable it. + */ + srds_lpd_b[FSL_SRDS_BANK_2] = 0; + enable_bank(gur, FSL_SRDS_BANK_2); + + wait_for_rstdone(FSL_SRDS_BANK_2); + + /* Disable bank 2 */ + setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, + SRDS_RSTCTL_SDPD); + } +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + for (device = XAUI_FM1; device <= XAUI_FM2; device++) { + if (is_serdes_configured(device)) + __serdes_reset_rx(srds_regs, cfg, device); + } +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h index 42d771e096..f261351c8a 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -33,7 +33,7 @@ enum srds_bank { int is_serdes_prtcl_valid(u32 prtcl); int serdes_get_lane_idx(int lane); -int serdes_get_bank(int lane); +int serdes_get_bank_by_lane(int lane); int serdes_lane_enabled(int lane); enum srds_prtcl serdes_get_prtcl(int cfg, int lane); diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c new file mode 100644 index 0000000000..e8a0387ca0 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -0,0 +1,75 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, + [0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {NONE, NONE}, + [0x01] = {SATA1, SATA2}, + [0x02] = {SATA1, SATA2}, + [0x03] = {PCIE1, PCIE2}, +}; + + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c new file mode 100644 index 0000000000..c8ab5d6f33 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -0,0 +1,53 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Roy Zang <tie-fei.zang@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {PCIE1, PCIE2, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, PCIE3, NONE}, + [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2}, + [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + return ret; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + +} diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index febbee95ba..1255898483 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), - SET_PCI_LIODN(4, 196), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index df2504802a..fd155c89e0 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -44,9 +44,9 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 156), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), + SET_PCI_LIODN("fsl,p4080-pcie", 1, 193), + SET_PCI_LIODN("fsl,p4080-pcie", 2, 194), + SET_PCI_LIODN("fsl,p4080-pcie", 3, 195), SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index febbee95ba..1255898483 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -52,10 +52,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN(1, 193), - SET_PCI_LIODN(2, 194), - SET_PCI_LIODN(3, 195), - SET_PCI_LIODN(4, 196), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 01aec6e794..c014163e3c 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,18 +30,14 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> -static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR; +static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; +static ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR; void setup_portals(void) { +#ifdef CONFIG_FSL_CORENET int i; - /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ -#ifdef CONFIG_PHYS_64BIT - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); -#endif - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 fliodn = qp_info[i].fliodn; @@ -53,6 +49,13 @@ void setup_portals(void) /* set frame liodn */ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); } +#endif + + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ +#ifdef CONFIG_PHYS_64BIT + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); +#endif + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); } /* Update portal containter to match LAW setup of portal in phy map */ @@ -118,9 +121,12 @@ void fdt_portal(void *blob, const char *compat, const char *container, static int fdt_qportal(void *blob, int off, int id, char *name, enum fsl_dpaa_dev dev, int create) { - int childoff, dev_off, num, ret = 0; + int childoff, dev_off, ret = 0; uint32_t dev_handle; +#ifdef CONFIG_FSL_CORENET + int num; u32 liodns[2]; +#endif childoff = fdt_subnode_offset(blob, off, name); if (create) { @@ -154,9 +160,11 @@ static int fdt_qportal(void *blob, int off, int id, char *name, if (ret < 0) return ret; +#ifdef CONFIG_FSL_CORENET num = get_dpaa_liodn(dev, &liodns[0], id); ret = fdt_setprop(blob, childoff, "fsl,liodn", &liodns[0], sizeof(u32) * num); +#endif } else { return childoff; } @@ -184,7 +192,9 @@ void fdt_fixup_qportals(void *blob) off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); while (off != -FDT_ERR_NOTFOUND) { +#ifdef CONFIG_FSL_CORENET u32 liodns[2]; +#endif const int *ci = fdt_getprop(blob, off, "cell-index", NULL); int j, i = *ci; @@ -192,6 +202,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET liodns[0] = qp_info[i].dliodn; liodns[1] = qp_info[i].fliodn; @@ -199,6 +210,7 @@ void fdt_fixup_qportals(void *blob) &liodns, sizeof(u32) * 2); if (err < 0) goto err; +#endif i++; @@ -207,6 +219,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_DPAA_PME err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); if (err < 0) @@ -214,6 +227,8 @@ void fdt_fixup_qportals(void *blob) #else fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); #endif +#endif + #ifdef CONFIG_SYS_DPAA_FMAN for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { char name[] = "fman@0"; @@ -236,3 +251,32 @@ err: off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal"); } } + +void fdt_fixup_bportals(void *blob) +{ + int off, err; + unsigned int maj, min; + u32 rev_1 = in_be32(&bman->ip_rev_1); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + + compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1; + compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal"); + while (off != -FDT_ERR_NOTFOUND) { + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), + fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal"); + } + +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f2aa8d039d..c4c156d737 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -28,6 +28,7 @@ #include <common.h> #include <ppc_asm.tmpl> +#include <linux/compiler.h> #include <asm/processor.h> #include <asm/io.h> @@ -107,25 +108,45 @@ void get_sys_info (sys_info_t * sysInfo) #define PME_CLK_SEL 0x80000000 #define FM1_CLK_SEL 0x40000000 #define FM2_CLK_SEL 0x20000000 +#define HWA_ASYNC_DIV 0x04000000 +#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) +#define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) +#define HWA_CC_PLL 2 +#else +#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case +#endif rcw_tmp = in_be32(&gur->rcwsr[7]); #ifdef CONFIG_SYS_DPAA_PME - if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else + if (rcw_tmp & PME_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqPME = sysInfo->freqSystemBus / 2; + } #endif #ifdef CONFIG_SYS_DPAA_FMAN - if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM1_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + } #if (CONFIG_SYS_NUM_FMAN) == 2 - if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else + if (rcw_tmp & FM2_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4; + else + sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2; + } else { sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + } #endif #endif @@ -136,7 +157,7 @@ void get_sys_info (sys_info_t * sysInfo) #endif int i; #ifdef CONFIG_QE - u32 qe_ratio; + __maybe_unused u32 qe_ratio; #endif plat_ratio = (gur->porpllsr) & 0x0000003e; @@ -162,13 +183,23 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif -#endif #ifdef CONFIG_QE +#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + sysInfo->freqQE = sysInfo->freqSystemBus; +#else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + sysInfo->freqFMan[0] = sysInfo->freqSystemBus; +#endif + +#endif /* CONFIG_FSL_CORENET */ #if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) @@ -254,7 +285,8 @@ int get_clocks (void) gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_FSL_ESDHC) -#ifdef CONFIG_MPC8569 +#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ + defined(CONFIG_P1014) gd->sdhc_clk = gd->bus_clk; #else gd->sdhc_clk = gd->bus_clk / 2; diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 31143ba530..295f175bba 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -55,6 +55,7 @@ void init_tlbs(void) return ; } +#ifndef CONFIG_NAND_SPL void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { @@ -73,7 +74,6 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, #endif } -#ifndef CONFIG_NAND_SPL void print_tlbcam(void) { int i; diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk index ca2f8376ed..92ff7bf3e9 100644 --- a/arch/powerpc/cpu/mpc86xx/config.mk +++ b/arch/powerpc/cpu/mpc86xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -ffixed-r2 -mstring PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/config.mk b/arch/powerpc/cpu/mpc8xx/config.mk index f5e08a5138..aa61980bcd 100644 --- a/arch/powerpc/cpu/mpc8xx/config.mk +++ b/arch/powerpc/cpu/mpc8xx/config.mk @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 5dfd65b882..4ae26e4210 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -15,6 +15,7 @@ COBJS-y += cpu.o endif COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o COBJS-$(CONFIG_SYS_SRIO) += srio.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 4335fb4f31..39b304ae99 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -71,15 +71,27 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P1012, P1012, 1), CPU_TYPE_ENTRY(P1012, P1012_E, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), + CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1014, P1014_E, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), - CPU_TYPE_ENTRY(P1013, P1013_E, 1), + CPU_TYPE_ENTRY(P1015, P1015_E, 1), + CPU_TYPE_ENTRY(P1015, P1015, 1), + CPU_TYPE_ENTRY(P1016, P1016_E, 1), + CPU_TYPE_ENTRY(P1016, P1016, 1), + CPU_TYPE_ENTRY(P1017, P1017, 1), + CPU_TYPE_ENTRY(P1017, P1017, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), CPU_TYPE_ENTRY(P1021, P1021_E, 2), CPU_TYPE_ENTRY(P1022, P1022, 2), CPU_TYPE_ENTRY(P1022, P1022_E, 2), + CPU_TYPE_ENTRY(P1023, P1023, 2), + CPU_TYPE_ENTRY(P1023, P1023_E, 2), + CPU_TYPE_ENTRY(P1024, P1024, 2), + CPU_TYPE_ENTRY(P1024, P1024_E, 2), + CPU_TYPE_ENTRY(P1025, P1025, 2), + CPU_TYPE_ENTRY(P1025, P1025_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index cefabe769f..02d069c9ec 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -236,7 +236,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - unsigned int data_rate = fsl_ddr_get_mem_data_rate(); + unsigned int data_rate = get_ddr_freq(0); tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; @@ -1305,7 +1305,7 @@ static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) { if (popts->addr_hash) { ddr->ddr_eor = 0x40000000; /* address hash enable */ - puts("Addess hashing enabled.\n"); + puts("Address hashing enabled.\n"); } } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index c7c12c1c2f..1e866fe035 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -80,5 +80,4 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); -extern unsigned int fsl_ddr_get_mem_data_rate(void); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c index dcb37cea1f..b565e338ad 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c @@ -250,24 +250,27 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, pdimm->primary_sdram_width = spd->primw; pdimm->ec_sdram_width = spd->ecw; - /* FIXME: what about registered SO-DIMM? */ + /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ switch (spd->dimm_type) { - case 0x01: /* RDIMM */ - case 0x10: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + case DDR2_SPD_DIMMTYPE_RDIMM: + case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: + case DDR2_SPD_DIMMTYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; break; - case 0x02: /* UDIMM */ - case 0x04: /* SO-DIMM */ - case 0x08: /* Micro-DIMM */ - case 0x20: /* Mini-UDIMM */ - pdimm->registered_dimm = 0; /* unbuffered */ + case DDR2_SPD_DIMMTYPE_UDIMM: + case DDR2_SPD_DIMMTYPE_SO_DIMM: + case DDR2_SPD_DIMMTYPE_MICRO_DIMM: + case DDR2_SPD_DIMMTYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + pdimm->registered_dimm = 0; break; + case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: default: printf("unknown dimm_type 0x%02X\n", spd->dimm_type); return 1; - break; } /* SDRAM device parameters */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 29cea53266..756b15f7ab 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -128,24 +128,32 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->data_width = pdimm->primary_sdram_width + pdimm->ec_sdram_width; - switch (spd->module_type & 0xf) { - case 0x01: /* RDIMM */ - case 0x05: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + /* These are the types defined by the JEDEC DDR3 SPD spec */ + pdimm->mirrored_dimm = 0; + pdimm->registered_dimm = 0; + switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { + case DDR3_SPD_MODULETYPE_RDIMM: + case DDR3_SPD_MODULETYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; for (i = 0; i < 16; i += 2) { - pdimm->rcw[i] = spd->mod_section.registered.rcw[i/2] & 0x0F; - pdimm->rcw[i+1] = (spd->mod_section.registered.rcw[i/2] >> 4) & 0x0F; + u8 rcw = spd->mod_section.registered.rcw[i/2]; + pdimm->rcw[i] = (rcw >> 0) & 0x0F; + pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; } break; - case 0x02: /* UDIMM */ - case 0x03: /* SO-DIMM */ - case 0x04: /* Micro-DIMM */ - case 0x06: /* Mini-UDIMM */ - pdimm->registered_dimm = 0; /* unbuffered */ + + case DDR3_SPD_MODULETYPE_UDIMM: + case DDR3_SPD_MODULETYPE_SO_DIMM: + case DDR3_SPD_MODULETYPE_MICRO_DIMM: + case DDR3_SPD_MODULETYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + if (spd->mod_section.unbuffered.addr_mapping & 0x1) + pdimm->mirrored_dimm = 1; break; default: - printf("unknown dimm_type 0x%02X\n", spd->module_type); + printf("unknown module_type 0x%02X\n", spd->module_type); return 1; } @@ -303,16 +311,5 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min) * mtb_ps; - /* - * We need check the address mirror for unbuffered DIMM - * If SPD indicate the address map mirror, The DDR controller - * need care it. - */ - if ((spd->module_type == SPD_MODULETYPE_UDIMM) || - (spd->module_type == SPD_MODULETYPE_SODIMM) || - (spd->module_type == SPD_MODULETYPE_MICRODIMM) || - (spd->module_type == SPD_MODULETYPE_MINIUDIMM)) - pdimm->mirrored_dimm = spd->mod_section.unbuffered.addr_mapping & 0x1; - return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 8b31ec0cfa..00f3d6c600 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -207,10 +207,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, temp1 = temp2 = 0; for (i = 0; i < number_of_dimms; i++) { if (dimm_params[i].n_ranks) { - if (dimm_params[i].registered_dimm) + if (dimm_params[i].registered_dimm) { temp1 = 1; - if (!dimm_params[i].registered_dimm) + printf("Detected RDIMM %s\n", + dimm_params[i].mpart); + } else { temp2 = 1; + printf("Detected UDIMM %s\n", + dimm_params[i].mpart); + } } } @@ -218,10 +223,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, outpdimm->all_DIMMs_unbuffered = 0; if (temp1 && !temp2) { outpdimm->all_DIMMs_registered = 1; - printf("Detected RDIMM(s)\n"); } else if (!temp1 && temp2) { outpdimm->all_DIMMs_unbuffered = 1; - printf("Detected UDIMM(s)\n"); } else { printf("ERROR: Mix of registered buffered and unbuffered " "DIMMs detected!\n"); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index bb96d66a9d..c8fa123539 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -13,6 +13,7 @@ */ #include <common.h> +#include <i2c.h> #include <asm/fsl_ddr_sdram.h> #include "ddr.h" @@ -26,9 +27,65 @@ extern void fsl_ddr_set_lawbar( extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); -/* Board-specific functions defined in each board's ddr.c */ -extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num); +#if defined(SPD_EEPROM_ADDRESS) || \ + defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ + defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) +#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS, +}; +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ +}; +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ +}; +#endif + +static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +__attribute__((weak, alias("__get_spd"))) +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); + +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + i2c_address = spd_i2c_addr[ctrl_num][i]; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} +#else +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ +} +#endif /* SPD_EEPROM_ADDRESSx */ /* * ASSUMPTIONS: diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 1e2d921286..104d360a5f 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -8,10 +8,16 @@ #include <common.h> #include <asm/fsl_law.h> +#include <div64.h> #include "ddr.h" -unsigned int fsl_ddr_get_mem_data_rate(void); +/* To avoid 64-bit full-divides, we factor this here */ +#define ULL_2E12 2000000000000ULL +#define UL_5POW12 244140625UL +#define UL_2POW13 (1UL << 13) + +#define ULL_8FS 0xFFFFFFFFULL /* * Round mclk_ps to nearest 10 ps in memory controller code. @@ -22,35 +28,51 @@ unsigned int fsl_ddr_get_mem_data_rate(void); */ unsigned int get_memory_clk_period_ps(void) { - unsigned int mclk_ps; + unsigned int data_rate = get_ddr_freq(0); + unsigned int result; + + /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ + unsigned long long mclk_ps = ULL_2E12; + + /* Add 5*data_rate, for rounding */ + mclk_ps += 5*(unsigned long long)data_rate; - mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate(); - /* round to nearest 10 ps */ - return 10 * ((mclk_ps + 5) / 10); + /* Now perform the big divide, the result fits in 32-bits */ + do_div(mclk_ps, data_rate); + result = mclk_ps; + + /* We still need to round to 10ps */ + return 10 * (result/10); } /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ unsigned int picos_to_mclk(unsigned int picos) { - const unsigned long long ULL_2e12 = 2000000000000ULL; - const unsigned long long ULL_8Fs = 0xFFFFFFFFULL; - unsigned long long clks; - unsigned long long clks_temp; + unsigned long long clks, clks_rem; + /* Short circuit for zero picos */ if (!picos) return 0; - clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos; - clks_temp = clks; - clks = clks / ULL_2e12; - if (clks_temp % ULL_2e12) { - clks++; - } + /* First multiply the time by the data rate (32x32 => 64) */ + clks = picos * (unsigned long long)get_ddr_freq(0); - if (clks > ULL_8Fs) { - clks = ULL_8Fs; - } + /* + * Now divide by 5^12 and track the 32-bit remainder, then divide + * by 2*(2^12) using shifts (and updating the remainder). + */ + clks_rem = do_div(clks, UL_5POW12); + clks_rem <<= 13; + clks_rem |= clks & (UL_2POW13-1); + clks >>= 13; + + /* If we had a remainder, then round up */ + if (clks_rem) + clks++; + /* Clamp to the maximum representable value */ + if (clks > ULL_8FS) + clks = ULL_8FS; return (unsigned int) clks; } @@ -141,6 +163,8 @@ void board_add_ram_info(int use_default) if (sdram_cfg & SDRAM_CFG_32_BE) puts(", 32-bit"); + else if (sdram_cfg & SDRAM_CFG_16_BE) + puts(", 16-bit"); else puts(", 64-bit"); diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 0c166fd6c9..520cb90280 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -27,8 +27,8 @@ #include <libfdt.h> #include <fdt_support.h> #include <asm/mp.h> -#include <asm/fsl_enet.h> #include <asm/fsl_serdes.h> +#include <phy.h> #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -218,27 +218,10 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev) } #endif -int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { - static const char *fsl_phy_enet_if_str[] = { - [MII] = "mii", - [RMII] = "rmii", - [GMII] = "gmii", - [RGMII] = "rgmii", - [RGMII_ID] = "rgmii-id", - [RGMII_RXID] = "rgmii-rxid", - [SGMII] = "sgmii", - [TBI] = "tbi", - [RTBI] = "rtbi", - [XAUI] = "xgmii", - [FSL_ETH_IF_NONE] = "", - }; - - if (phyc > ARRAY_SIZE(fsl_phy_enet_if_str)) - return fdt_setprop_string(blob, offset, "phy-connection-type", ""); - return fdt_setprop_string(blob, offset, "phy-connection-type", - fsl_phy_enet_if_str[phyc]); + phy_string_for_interface(phyc)); } #ifdef CONFIG_SYS_SRIO diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c new file mode 100644 index 0000000000..e79482130e --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -0,0 +1,83 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_ifc.h> + +void print_ifc_regs(void) +{ + int i, j; + + printf("IFC Controller Registers\n"); + for (i = 0; i < FSL_IFC_BANK_COUNT; i++) { + printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", + i, get_ifc_cspr(i), i, get_ifc_amask(i), + i, get_ifc_csor(i)); + for (j = 0; j < 4; j++) + printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); + } +} + +void init_early_memctl_regs(void) +{ +#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); + + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); +#endif + +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); + + set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); +#endif + +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); + + set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); +#endif + +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); + + set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); +#endif +} diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk index d862bb4fb8..f5cbbbd665 100644 --- a/arch/powerpc/cpu/ppc4xx/config.mk +++ b/arch/powerpc/cpu/ppc4xx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -meabi +PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 2b6b233ba6..9aad9be1b0 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -29,6 +29,13 @@ #include <asm/config_mpc86xx.h> #endif +/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ +#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) +# ifndef CONFIG_HARD_SPI +# define CONFIG_HARD_SPI +# endif +#endif + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_SYS_BOOT_GET_CMDLINE @@ -75,8 +82,19 @@ /* Since so many PPC SOCs have a semi-common LBC, define this here */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83xx) +#if !defined(CONFIG_FSL_IFC) #define CONFIG_FSL_LBC #endif +#endif + +/* The TSEC driver uses the PHYLIB infrastructure */ +#ifndef CONFIG_PHYLIB +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_PHYLIB + +#include <config_phylib_all_drivers.h> +#endif /* TSEC_ENET */ +#endif /* !CONFIG_PHYLIB */ /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6c16681b7f..41c2d20df5 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -67,11 +67,17 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define QE_MURAM_SIZE 0x10000UL +#define MAX_QE_RISC 2 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define QE_MURAM_SIZE 0x20000UL +#define MAX_QE_RISC 4 +#define QE_NUM_OF_SNUM 46 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 @@ -82,24 +88,39 @@ #elif defined(CONFIG_P1010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +/* P1011 is single core version of P1020 */ #elif defined(CONFIG_P1011) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +/* P1012 is single core version of P1021 */ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +/* P1013 is single core version of P1022 */ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -111,9 +132,49 @@ #elif defined(CONFIG_P1014) #define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 + +/* P1015 is single core version of P1024 */ +#elif defined(CONFIG_P1015) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1016 is single core version of P1025 */ +#elif defined(CONFIG_P1016) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +/* P1017 is single core version of P1023 */ +#elif defined(CONFIG_P1017) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_QMAN_NUM_PORTALS 3 +#define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -121,6 +182,8 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 @@ -128,6 +191,11 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 @@ -138,6 +206,41 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#elif defined(CONFIG_P1023) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_QMAN_NUM_PORTALS 3 +#define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 + +/* P1024 is lower end variant of P1020 */ +#elif defined(CONFIG_P1024) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + +/* P1025 is lower end variant of P1021 */ +#elif defined(CONFIG_P1025) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_FSL_PCIE_DISABLE_ASPM +#define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +/* P2010 is single core version of P2020 */ #elif defined(CONFIG_P2010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 @@ -154,21 +257,44 @@ #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 @@ -177,6 +303,8 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -186,16 +314,40 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 +#define CONFIG_SYS_P4080_ERRATUM_SERDES9 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +/* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) #define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #else #error Processor type not defined for this platform diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 02a1f5d323..127a84039c 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -84,6 +84,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 #define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 #define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_2T_EN 0x00008000 @@ -270,7 +271,10 @@ typedef struct memctl_options_s { } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); +extern phys_size_t fsl_ddr_sdram_size(void); extern int fsl_use_spd(void); +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); /* * The 85xx boards have a common prototype for fixed_sdram so put the diff --git a/arch/powerpc/include/asm/fsl_enet.h b/arch/powerpc/include/asm/fsl_enet.h index 4fb2857f3e..8227b667cb 100644 --- a/arch/powerpc/include/asm/fsl_enet.h +++ b/arch/powerpc/include/asm/fsl_enet.h @@ -13,21 +13,18 @@ #ifndef __ASM_PPC_FSL_ENET_H #define __ASM_PPC_FSL_ENET_H -enum fsl_phy_enet_if { - MII, - RMII, - GMII, - RGMII, - RGMII_ID, - RGMII_RXID, - RGMII_TXID, - SGMII, - TBI, - RTBI, - XAUI, - FSL_ETH_IF_NONE, -}; +#include <phy.h> -int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc); +struct tsec_mii_mng { + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u32 ifstat; /* Interface Status Register */ +} __attribute__ ((packed)); + +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); #endif /* __ASM_PPC_FSL_ENET_H */ diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h new file mode 100644 index 0000000000..d4d9809055 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -0,0 +1,957 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat <dipen.dudhat@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_PPC_FSL_IFC_H +#define __ASM_PPC_FSL_IFC_H + +#include <config.h> +#include <common.h> + +/* + * CSPR - Chip Select Property Register + */ +#define CSPR_BA 0xFFFF0000 +#define CSPR_BA_SHIFT 16 +#define CSPR_PORT_SIZE 0x00000180 +#define CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define CSPR_WP 0x00000040 +#define CSPR_WP_SHIFT 6 +/* Machine Select */ +#define CSPR_MSEL 0x00000006 +#define CSPR_MSEL_SHIFT 1 +/* NOR */ +#define CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define CSPR_V 0x00000001 +#define CSPR_V_SHIFT 0 + +/* Convert an address into the right format for the CSPR Registers */ +#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (__ilog2(n) - IFC_AMASK_SHIFT)) + +/* + * Chip Select Option Register IFC_NAND Machine + */ +/* Enable ECC Encoder */ +#define CSOR_NAND_ECC_ENC_EN 0x80000000 +/* 4 bit correction per 520 Byte sector */ +#define CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define CSOR_NAND_RAL_MASK 0x01800000 +#define CSOR_NAND_RAL_SHIFT 20 +#define CSOR_NAND_RAL_1 0x00000000 +#define CSOR_NAND_RAL_2 0x00800000 +#define CSOR_NAND_RAL_3 0x01000000 +#define CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define CSOR_NAND_PGS_MASK 0x00180000 +#define CSOR_NAND_PGS_SHIFT 16 +#define CSOR_NAND_PGS_512 0x00000000 +#define CSOR_NAND_PGS_2K 0x00080000 +#define CSOR_NAND_PGS_4K 0x00100000 +/* Spare region Size */ +#define CSOR_NAND_SPRZ_MASK 0x0000E000 +#define CSOR_NAND_SPRZ_SHIFT 13 +#define CSOR_NAND_SPRZ_16 0x00000000 +#define CSOR_NAND_SPRZ_64 0x00002000 +#define CSOR_NAND_SPRZ_128 0x00004000 +#define CSOR_NAND_SPRZ_210 0x00006000 +#define CSOR_NAND_SPRZ_218 0x00008000 +#define CSOR_NAND_SPRZ_224 0x0000A000 +/* Pages Per Block */ +#define CSOR_NAND_PB_MASK 0x00000700 +#define CSOR_NAND_PB_SHIFT 8 +#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NAND_TRHZ_MASK 0x0000001C +#define CSOR_NAND_TRHZ_SHIFT 2 +#define CSOR_NAND_TRHZ_20 0x00000000 +#define CSOR_NAND_TRHZ_40 0x00000004 +#define CSOR_NAND_TRHZ_60 0x00000008 +#define CSOR_NAND_TRHZ_80 0x0000000C +#define CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NAND_BCTLD 0x00000001 + +/* + * Chip Select Option Register - NOR Flash Mode + */ +/* Enable Address shift Mode */ +#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define CSOR_NOR_ADM_MASK 0x0003E000 +#define CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NOR_TRHZ_MASK 0x0000001C +#define CSOR_NOR_TRHZ_SHIFT 2 +#define CSOR_NOR_TRHZ_20 0x00000000 +#define CSOR_NOR_TRHZ_40 0x00000004 +#define CSOR_NOR_TRHZ_60 0x00000008 +#define CSOR_NOR_TRHZ_80 0x0000000C +#define CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NOR_BCTLD 0x00000001 + +/* + * Chip Select Option Register - GPCM Mode + */ +/* GPCM Mode - Normal */ +#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 +/* GPCM Mode - GenericASIC */ +#define CSOR_GPCM_GPMODE_ASIC 0x80000000 +/* Parity Mode odd/even */ +#define CSOR_GPCM_PARITY_EVEN 0x40000000 +/* Parity Checking enable/disable */ +#define CSOR_GPCM_PAR_EN 0x20000000 +/* GPCM Timeout Count */ +#define CSOR_GPCM_GPTO_MASK 0x0F000000 +#define CSOR_GPCM_GPTO_SHIFT 24 +#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +/* GPCM External Access Termination mode for read access */ +#define CSOR_GPCM_RGETA_EXT 0x00080000 +/* GPCM External Access Termination mode for write access */ +#define CSOR_GPCM_WGETA_EXT 0x00040000 +/* Address Data Multiplexing Shift */ +#define CSOR_GPCM_ADM_MASK 0x0003E000 +#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 +#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) +/* Generic ASIC Parity error indication delay */ +#define CSOR_GPCM_GAPERRD_MASK 0x00000180 +#define CSOR_GPCM_GAPERRD_SHIFT 7 +#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_GPCM_TRHZ_MASK 0x0000001C +#define CSOR_GPCM_TRHZ_20 0x00000000 +#define CSOR_GPCM_TRHZ_40 0x00000004 +#define CSOR_GPCM_TRHZ_60 0x00000008 +#define CSOR_GPCM_TRHZ_80 0x0000000C +#define CSOR_GPCM_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_GPCM_BCTLD 0x00000001 + +/* + * Flash Timing Registers (FTIM0 - FTIM2_CSn) + */ +/* + * FTIM0 - NAND Flash Mode + */ +#define FTIM0_NAND 0x7EFF3F3F +#define FTIM0_NAND_TCCST_SHIFT 25 +#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) +#define FTIM0_NAND_TWP_SHIFT 16 +#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) +#define FTIM0_NAND_TWCHT_SHIFT 8 +#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) +#define FTIM0_NAND_TWH_SHIFT 0 +#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) +/* + * FTIM1 - NAND Flash Mode + */ +#define FTIM1_NAND 0xFFFF3FFF +#define FTIM1_NAND_TADLE_SHIFT 24 +#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) +#define FTIM1_NAND_TWBE_SHIFT 16 +#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) +#define FTIM1_NAND_TRR_SHIFT 8 +#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) +#define FTIM1_NAND_TRP_SHIFT 0 +#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) +/* + * FTIM2 - NAND Flash Mode + */ +#define FTIM2_NAND 0x1FE1F8FF +#define FTIM2_NAND_TRAD_SHIFT 21 +#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) +#define FTIM2_NAND_TREH_SHIFT 11 +#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) +#define FTIM2_NAND_TWHRE_SHIFT 0 +#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) +/* + * FTIM3 - NAND Flash Mode + */ +#define FTIM3_NAND 0xFF000000 +#define FTIM3_NAND_TWW_SHIFT 24 +#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) + +/* + * FTIM0 - NOR Flash Mode + */ +#define FTIM0_NOR 0xF03F3F3F +#define FTIM0_NOR_TACSE_SHIFT 28 +#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) +#define FTIM0_NOR_TEADC_SHIFT 16 +#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) +#define FTIM0_NOR_TAVDS_SHIFT 8 +#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) +#define FTIM0_NOR_TEAHC_SHIFT 0 +#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) +/* + * FTIM1 - NOR Flash Mode + */ +#define FTIM1_NOR 0xFF003F3F +#define FTIM1_NOR_TACO_SHIFT 24 +#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) +#define FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) +#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) +/* + * FTIM2 - NOR Flash Mode + */ +#define FTIM2_NOR 0x0F3CFCFF +#define FTIM2_NOR_TCS_SHIFT 24 +#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) +#define FTIM2_NOR_TCH_SHIFT 18 +#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) +#define FTIM2_NOR_TWPH_SHIFT 10 +#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) +#define FTIM2_NOR_TWP_SHIFT 0 +#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) + +/* + * FTIM0 - Normal GPCM Mode + */ +#define FTIM0_GPCM 0xF03F3F3F +#define FTIM0_GPCM_TACSE_SHIFT 28 +#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) +#define FTIM0_GPCM_TEADC_SHIFT 16 +#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) +#define FTIM0_GPCM_TAVDS_SHIFT 8 +#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) +#define FTIM0_GPCM_TEAHC_SHIFT 0 +#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) +/* + * FTIM1 - Normal GPCM Mode + */ +#define FTIM1_GPCM 0xFF003F00 +#define FTIM1_GPCM_TACO_SHIFT 24 +#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) +#define FTIM1_GPCM_TRAD_SHIFT 8 +#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) +/* + * FTIM2 - Normal GPCM Mode + */ +#define FTIM2_GPCM 0x0F3C00FF +#define FTIM2_GPCM_TCS_SHIFT 24 +#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) +#define FTIM2_GPCM_TCH_SHIFT 18 +#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) +#define FTIM2_GPCM_TWP_SHIFT 0 +#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) + +/* + * Ready Busy Status Register (RB_STAT) + */ +/* CSn is READY */ +#define IFC_RB_STAT_READY_CS0 0x80000000 +#define IFC_RB_STAT_READY_CS1 0x40000000 +#define IFC_RB_STAT_READY_CS2 0x20000000 +#define IFC_RB_STAT_READY_CS3 0x10000000 + +/* + * General Control Register (GCR) + */ +#define IFC_GCR_MASK 0x8000F800 +/* reset all IFC hardware */ +#define IFC_GCR_SOFT_RST_ALL 0x80000000 +/* Turnaroud Time of external buffer */ +#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 +#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 + +/* + * Common Event and Error Status Register (CM_EVTER_STAT) + */ +/* Chip select error */ +#define IFC_CM_EVTER_STAT_CSER 0x80000000 + +/* + * Common Event and Error Enable Register (CM_EVTER_EN) + */ +/* Chip select error checking enable */ +#define IFC_CM_EVTER_EN_CSEREN 0x80000000 + +/* + * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) + */ +/* Chip select error interrupt enable */ +#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 + +/* + * Common Transfer Error Attribute Register-0 (CM_ERATTR0) + */ +/* transaction type of error Read/Write */ +#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 +#define IFC_CM_ERATTR0_ERAID 0x0FF00000 +#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 + +/* + * Clock Control Register (CCR) + */ +#define IFC_CCR_MASK 0x0F0F8800 +/* Clock division ratio */ +#define IFC_CCR_CLK_DIV_MASK 0x0F000000 +#define IFC_CCR_CLK_DIV_SHIFT 24 +#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) +/* IFC Clock Delay */ +#define IFC_CCR_CLK_DLY_MASK 0x000F0000 +#define IFC_CCR_CLK_DLY_SHIFT 16 +#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) +/* Invert IFC clock before sending out */ +#define IFC_CCR_INV_CLK_EN 0x00008000 +/* Fedback IFC Clock */ +#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 + +/* + * Clock Status Register (CSR) + */ +/* Clk is stable */ +#define IFC_CSR_CLK_STAT_STABLE 0x80000000 + +/* + * IFC_NAND Machine Specific Registers + */ +/* + * NAND Configuration Register (NCFGR) + */ +/* Auto Boot Mode */ +#define IFC_NAND_NCFGR_BOOT 0x80000000 +/* Addressing Mode-ROW0+n/COL0 */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 +/* Addressing Mode-ROW0+n/COL0+n */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 +/* Number of loop iterations of FIR sequences for multi page operations */ +#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 +#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 +#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) +/* Number of wait cycles */ +#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF +#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF000000 +#define IFC_NAND_FCR0_CMD0_SHIFT 24 +#define IFC_NAND_FCR0_CMD1 0x00FF0000 +#define IFC_NAND_FCR0_CMD1_SHIFT 16 +#define IFC_NAND_FCR0_CMD2 0x0000FF00 +#define IFC_NAND_FCR0_CMD2_SHIFT 8 +#define IFC_NAND_FCR0_CMD3 0x000000FF +#define IFC_NAND_FCR0_CMD3_SHIFT 0 +#define IFC_NAND_FCR1_CMD4 0xFF000000 +#define IFC_NAND_FCR1_CMD4_SHIFT 24 +#define IFC_NAND_FCR1_CMD5 0x00FF0000 +#define IFC_NAND_FCR1_CMD5_SHIFT 16 +#define IFC_NAND_FCR1_CMD6 0x0000FF00 +#define IFC_NAND_FCR1_CMD6_SHIFT 8 +#define IFC_NAND_FCR1_CMD7 0x000000FF +#define IFC_NAND_FCR1_CMD7_SHIFT 0 + +/* + * Flash ROW and COL Address Register (ROWn, COLn) + */ +/* Main/spare region locator */ +#define IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define IFC_NAND_COL_CA_MASK 0x00000FFF + +/* + * NAND Flash Byte Count Register (NAND_BC) + */ +/* Byte Count for read/Write */ +#define IFC_NAND_BC 0x000001FF + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC000000 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F00000 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x00003F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x000000FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC000000 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F00000 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x00003F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x000000FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC000000 +#define IFC_NAND_FIR2_OP10_SHIFT 26 +#define IFC_NAND_FIR2_OP11 0x03F00000 +#define IFC_NAND_FIR2_OP11_SHIFT 20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT 14 +#define IFC_NAND_FIR2_OP13 0x00003F00 +#define IFC_NAND_FIR2_OP13_SHIFT 8 +#define IFC_NAND_FIR2_OP14 0x000000FC +#define IFC_NAND_FIR2_OP14_SHIFT 2 + +/* + * Instruction opcodes to be programmed + * in FIR registers- 6bits + */ +enum ifc_nand_fir_opcodes { + IFC_FIR_OP_NOP, + IFC_FIR_OP_CA0, + IFC_FIR_OP_CA1, + IFC_FIR_OP_CA2, + IFC_FIR_OP_CA3, + IFC_FIR_OP_RA0, + IFC_FIR_OP_RA1, + IFC_FIR_OP_RA2, + IFC_FIR_OP_RA3, + IFC_FIR_OP_CMD0, + IFC_FIR_OP_CMD1, + IFC_FIR_OP_CMD2, + IFC_FIR_OP_CMD3, + IFC_FIR_OP_CMD4, + IFC_FIR_OP_CMD5, + IFC_FIR_OP_CMD6, + IFC_FIR_OP_CMD7, + IFC_FIR_OP_CW0, + IFC_FIR_OP_CW1, + IFC_FIR_OP_CW2, + IFC_FIR_OP_CW3, + IFC_FIR_OP_CW4, + IFC_FIR_OP_CW5, + IFC_FIR_OP_CW6, + IFC_FIR_OP_CW7, + IFC_FIR_OP_WBCD, + IFC_FIR_OP_RBCD, + IFC_FIR_OP_BTRD, + IFC_FIR_OP_RDSTAT, + IFC_FIR_OP_NWAIT, + IFC_FIR_OP_WFR, + IFC_FIR_OP_SBRD, + IFC_FIR_OP_UA, + IFC_FIR_OP_RB, +}; + +/* + * NAND Chip Select Register (NAND_CSEL) + */ +#define IFC_NAND_CSEL 0x0C000000 +#define IFC_NAND_CSEL_SHIFT 26 +#define IFC_NAND_CSEL_CS0 0x00000000 +#define IFC_NAND_CSEL_CS1 0x04000000 +#define IFC_NAND_CSEL_CS2 0x08000000 +#define IFC_NAND_CSEL_CS3 0x0C000000 + +/* + * NAND Operation Sequence Start (NANDSEQ_STRT) + */ +/* NAND Flash Operation Start */ +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 +/* Automatic Erase */ +#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 +/* Automatic Program */ +#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 +/* Automatic Copyback */ +#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 +/* Automatic Read Operation */ +#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 +/* Automatic Status Read */ +#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 +/* RCW Load Done */ +#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 +/* Boot Loadr Done */ +#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 +/* Bad Block Indicator search select */ +#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 + +/* + * NAND Flash Page Read Completion Event Status Register + * (PGRDCMPL_EVT_STAT) + */ +#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 +/* Small Page 0-15 Done */ +#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) +/* Large Page(2K) 0-3 Done */ +#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) +/* Large Page(4K) 0-1 Done */ +#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) + +/* + * NAND Event and Error Enable Register (NAND_EVTER_EN) + */ +/* Operation complete event enable */ +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 + +/* + * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) + */ +/* Enable interrupt for operation complete */ +#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 +/* Enable interrupt for Page read complete */ +#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 +/* Enable interrupt for Flash timeout error */ +#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 +/* Enable interrupt for Write protect error */ +#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 +/* Enable interrupt for ECC error*/ +#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 + +/* + * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) + */ +#define IFC_NAND_ERATTR0_MASK 0x0C080000 +/* Error on CS0-3 for NAND */ +#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 +#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 +#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 +/* Transaction type of error Read/Write */ +#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 + +/* + * NAND Flash Status Register (NAND_FSR) + */ +/* First byte of data read from read status op */ +#define IFC_NAND_NFSR_RS0 0xFF000000 +/* Second byte of data read from read status op */ +#define IFC_NAND_NFSR_RS1 0x00FF0000 + +/* + * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) + */ +/* Number of ECC errors on sector n (n = 0-15) */ +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 + +/* + * NAND Control Register (NANDCR) + */ +#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 +#define IFC_NAND_NCR_FTOCNT_SHIFT 25 +#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) + +/* + * NAND_AUTOBOOT_TRGR + */ +/* Trigger RCW load */ +#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 +/* Trigget Auto Boot */ +#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 + +/* + * NAND_MDR + */ +/* 1st read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA0 0xFF000000 +/* 2nd read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA1 0x00FF0000 + +/* + * NOR Machine Specific Registers + */ +/* + * NOR Event and Error Status Register (NOR_EVTER_STAT) + */ +/* NOR Command Sequence Operation Complete */ +#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 +/* Write Protect Error */ +#define IFC_NOR_EVTER_STAT_WPER 0x04000000 +/* Command Sequence Timeout Error */ +#define IFC_NOR_EVTER_STAT_STOER 0x01000000 + +/* + * NOR Event and Error Enable Register (NOR_EVTER_EN) + */ +/* NOR Command Seq complete event enable */ +#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 +/* Write Protect Error Checking Enable */ +#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 +/* Timeout Error Enable */ +#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 + +/* + * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) + */ +/* Enable interrupt for OPC complete */ +#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 +/* Enable interrupt for write protect error */ +#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 +/* Enable interrupt for timeout error */ +#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 + +/* + * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transation */ +#define IFC_NOR_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to NOR error */ +#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 +#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 +#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 +/* Type of transaction read/write */ +#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) + */ +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 + +/* + * NOR Control Register (NORCR) + */ +#define IFC_NORCR_MASK 0x0F0F0000 +/* No. of Address/Data Phase */ +#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 +#define IFC_NORCR_NUM_PHASE_SHIFT 24 +#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) +/* Sequence Timeout Count */ +#define IFC_NORCR_STOCNT_MASK 0x000F0000 +#define IFC_NORCR_STOCNT_SHIFT 16 +#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) + +/* + * GPCM Machine specific registers + */ +/* + * GPCM Event and Error Status Register (GPCM_EVTER_STAT) + */ +/* Timeout error */ +#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 +/* Parity error */ +#define IFC_GPCM_EVTER_STAT_PER 0x01000000 + +/* + * GPCM Event and Error Enable Register (GPCM_EVTER_EN) + */ +/* Timeout error enable */ +#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 +/* Parity error enable */ +#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 + +/* + * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) + */ +/* Enable Interrupt for timeout error */ +#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 +/* Enable Interrupt for Parity error */ +#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 + +/* + * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to GPCM error */ +#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 +#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 +#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 +/* Type of transaction read/Write */ +#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) + */ +/* On which beat of address/data parity error is observed */ +#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 +/* Parity Error on byte */ +#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 +/* Parity Error reported in addr or data phase */ +#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 + +/* + * GPCM Status Register (GPCM_STAT) + */ +#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ + + +#ifndef __ASSEMBLY__ +#include <asm/io.h> + +extern void print_ifc_regs(void); +extern void init_early_memctl_regs(void); + +#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) + +#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define set_ifc_ftim(i, j, v) \ + (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + +#define FSL_IFC_BANK_COUNT 4 + +enum ifc_chip_sel { + IFC_CS0, + IFC_CS1, + IFC_CS2, + IFC_CS3, +}; + +enum ifc_ftims { + IFC_FTIM0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +}; + +/* + * IFC Controller NAND Machine registers + */ +struct fsl_ifc_nand { + u32 ncfgr; + u32 res1[0x4]; + u32 nand_fcr0; + u32 nand_fcr1; + u32 res2[0x8]; + u32 row0; + u32 res3; + u32 col0; + u32 res4; + u32 row1; + u32 res5; + u32 col1; + u32 res6; + u32 row2; + u32 res7; + u32 col2; + u32 res8; + u32 row3; + u32 res9; + u32 col3; + u32 res10[0x24]; + u32 nand_fbcr; + u32 res11; + u32 nand_fir0; + u32 nand_fir1; + u32 nand_fir2; + u32 res12[0x10]; + u32 nand_csel; + u32 res13; + u32 nandseq_strt; + u32 res14; + u32 nand_evter_stat; + u32 res15; + u32 pgrdcmpl_evt_stat; + u32 res16[0x2]; + u32 nand_evter_en; + u32 res17[0x2]; + u32 nand_evter_intr_en; + u32 res18[0x2]; + u32 nand_erattr0; + u32 nand_erattr1; + u32 res19[0x10]; + u32 nand_fsr; + u32 res20; + u32 nand_eccstat0; + u32 nand_eccstat1; + u32 nand_eccstat2; + u32 nand_eccstat3; + u32 res21[0x20]; + u32 nanndcr; + u32 res22[0x2]; + u32 nand_autoboot_trgr; + u32 res23; + u32 nand_mdr; + u32 res24[0x5C]; +}; + +/* + * IFC controller NOR Machine registers + */ +struct fsl_ifc_nor { + u32 nor_evter_stat; + u32 res1[0x2]; + u32 nor_evter_en; + u32 res2[0x2]; + u32 nor_evter_intr_en; + u32 res3[0x2]; + u32 nor_erattr0; + u32 nor_erattr1; + u32 nor_erattr2; + u32 res4[0x4]; + u32 norcr; + u32 res5[0xEF]; +}; + +/* + * IFC controller GPCM Machine registers + */ +struct fsl_ifc_gpcm { + u32 gpcm_evter_stat; + u32 res1[0x2]; + u32 gpcm_evter_en; + u32 res2[0x2]; + u32 gpcm_evter_intr_en; + u32 res3[0x2]; + u32 gpcm_erattr0; + u32 gpcm_erattr1; + u32 gpcm_erattr2; + u32 gpcm_stat; + u32 res4[0x1F3]; +}; + + +/* + * IFC Controller Registers + */ +struct fsl_ifc { + u32 ifc_rev; + u32 res1[0x3]; + struct { + u32 cspr; + u32 res2[0x2]; + } cspr_cs[FSL_IFC_BANK_COUNT]; + u32 res3[0x18]; + struct { + u32 amask; + u32 res4[0x2]; + } amask_cs[FSL_IFC_BANK_COUNT]; + u32 res5[0x18]; + struct { + u32 csor; + u32 res6[0x2]; + } csor_cs[FSL_IFC_BANK_COUNT]; + u32 res7[0x18]; + struct { + u32 ftim[4]; + u32 res8[0x8]; + } ftim_cs[FSL_IFC_BANK_COUNT]; + u32 res9[0x60]; + u32 rb_stat; + u32 res10[0x2]; + u32 ifc_gcr; + u32 res11[0x2]; + u32 cm_evter_stat; + u32 res12[0x2]; + u32 cm_evter_en; + u32 res13[0x2]; + u32 cm_evter_intr_en; + u32 res14[0x2]; + u32 cm_erattr0; + u32 cm_erattr1; + u32 res15[0x2]; + u32 ifc_ccr; + u32 ifc_csr; + u32 res16[0x2EB]; + struct fsl_ifc_nand ifc_nand; + struct fsl_ifc_nor ifc_nor; + struct fsl_ifc_gpcm ifc_gpcm; +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_PPC_FSL_IFC_H */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 6a4279ce98..13caffd96e 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -83,6 +83,7 @@ enum law_trgt_if { LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, LAW_TRGT_IF_RIO_2 = 0x0d, + LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, LAW_TRGT_IF_DDR = 0x0f, LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ }; @@ -91,6 +92,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO +#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC #ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 4c17fe232e..801571f9eb 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -70,8 +70,8 @@ extern void fdt_fixup_liodn(void *blob); SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET) -#define SET_PCI_LIODN(pciNum, liodn) \ - SET_GUTS_LIODN("fsl,p4080-pcie", liodn, pex##pciNum##liodnr,\ +#define SET_PCI_LIODN(compat, pciNum, liodn) \ + SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) /* reg nodes for DMA start @ 0x300 */ @@ -85,13 +85,13 @@ extern void fdt_fixup_liodn(void *blob); #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) + CONFIG_SYS_FSL_QMAN_OFFSET, \ + CONFIG_SYS_FSL_QMAN_OFFSET) #define SET_BMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) + CONFIG_SYS_FSL_BMAN_OFFSET, \ + CONFIG_SYS_FSL_BMAN_OFFSET) #define SET_PME_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ @@ -115,10 +115,18 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ +/* + * handle both old and new versioned SEC properties: + * "fsl,secX.Y" became "fsl,sec-vX.Y" during development + */ #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ + SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ @@ -127,6 +135,11 @@ extern void fdt_fixup_liodn(void *blob); liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 0a98bdee36..fc47a9f7ec 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -25,6 +25,9 @@ #include <asm/fsl_serdes.h> #include <pci.h> +#define PEX_IP_BLK_REV_2_2 0x02080202 +#define PEX_IP_BLK_REV_2_3 0x02080203 + int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_config_unlock(struct pci_controller *hose); @@ -73,7 +76,8 @@ typedef struct ccsr_pci { u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ u32 config; /* 0x014 - PCIE CONFIG Register */ - char res2[8]; + u32 int_status; /* 0x018 - PCIE interrupt status register */ + char res2[4]; u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ @@ -83,8 +87,11 @@ typedef struct ccsr_pci { u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ - u32 res5[64]; - pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ + u32 res5[24]; + pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */ + u32 res6[24]; + pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */ + #define PIT3 0 #define PIT2 1 #define PIT1 2 @@ -158,6 +165,11 @@ typedef struct ccsr_pci { u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ char res24[252]; } ccsr_fsl_pci_t; +#define PCIE_CONFIG_PC 0x00020000 +#define PCIE_CONFIG_OB_CK 0x00002000 +#define PCIE_CONFIG_SAC 0x00000010 +#define PCIE_CONFIG_SP 0x80000002 +#define PCIE_CONFIG_SCC 0x80000001 struct fsl_pci_info { unsigned long regs; @@ -218,7 +230,9 @@ int fsl_pcie_init_board(int busno); #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3) #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4) -#if defined(CONFIG_FSL_CORENET) +#if !defined(CONFIG_PCI) +#define FT_FSL_PCI_SETUP +#elif defined(CONFIG_FSL_CORENET) #define FSL_PCIE_COMPAT "fsl,p4080-pcie" #define FT_FSL_PCI_SETUP \ FT_FSL_PCIE1_SETUP; \ diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index cb32927a83..e1c1212c38 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -51,6 +51,7 @@ extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset); extern void setup_portals(void); extern void fdt_fixup_qportals(void *blob); +extern void fdt_fixup_bportals(void *blob); extern struct qportal_info qp_info[]; extern void fdt_portal(void *blob, const char *compat, const char *container, diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 85518eb6e7..0f31af1db3 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -53,4 +53,11 @@ enum srds_prtcl { int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); +#ifdef CONFIG_FSL_CORENET +int serdes_get_first_lane(enum srds_prtcl device); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +void serdes_reset_rx(enum srds_prtcl device); +#endif +#endif + #endif /* __FSL_SERDES_H */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 6bd83ba166..f85cee270f 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -31,6 +31,7 @@ #include <asm/types.h> #include <asm/fsl_dma.h> #include <asm/fsl_i2c.h> +#include <asm/fsl_ifc.h> #include <asm/fsl_lbc.h> #include <asm/fsl_fman.h> @@ -1864,8 +1865,13 @@ typedef struct ccsr_gur { #define MPC85xx_PORBMSR_HA_SHIFT 16 u32 porimpscr; /* POR I/O impedance status & control */ u32 pordevsr; /* POR I/O device status regsiter */ +#if defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 +#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 +#else #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 +#endif #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 @@ -1873,9 +1879,17 @@ typedef struct ccsr_gur { #if defined(CONFIG_P1013) || defined(CONFIG_P1022) #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 +#elif defined(CONFIG_P1017) || defined(CONFIG_P1023) +#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#else +#if defined(CONFIG_P1010) +#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 +#endif /* if defined(CONFIG_P1010) */ #endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 @@ -1906,10 +1920,106 @@ typedef struct ccsr_gur { u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ +#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 +#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 +#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 +#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 +#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 +#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 +#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 +#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 +#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 +#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 +#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 +#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 +#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 +#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 +#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 +#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 +#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 +#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 +#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 +#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 +#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 +#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 +#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 +#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 +#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 +#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 +#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 +#define MPC85xx_PMUXCR_LCLK_RES 0x00000040 +#define MPC85xx_PMUXCR_LCLK_USB 0x00000080 +#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 +#define MPC85xx_PMUXCR_SPI_RES 0x00000030 +#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 +#define MPC85xx_PMUXCR_CAN1_UART 0x00000004 +#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 +#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C +#define MPC85xx_PMUXCR_CAN2_UART 0x00000001 +#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 +#define MPC85xx_PMUXCR_CAN2_RES 0x00000003 +#endif #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 +#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 +#define MPC85xx_PMUXCR_TDM_ENA 0x00800000 +#define MPC85xx_PMUXCR_QE0 0x00008000 +#define MPC85xx_PMUXCR_QE1 0x00004000 +#define MPC85xx_PMUXCR_QE2 0x00002000 +#define MPC85xx_PMUXCR_QE3 0x00001000 +#define MPC85xx_PMUXCR_QE4 0x00000800 +#define MPC85xx_PMUXCR_QE5 0x00000400 +#define MPC85xx_PMUXCR_QE6 0x00000200 +#define MPC85xx_PMUXCR_QE7 0x00000100 +#define MPC85xx_PMUXCR_QE8 0x00000080 +#define MPC85xx_PMUXCR_QE9 0x00000040 +#define MPC85xx_PMUXCR_QE10 0x00000020 +#define MPC85xx_PMUXCR_QE11 0x00000010 +#define MPC85xx_PMUXCR_QE12 0x00000008 +#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 +#define MPC85xx_PMUXCR_TDM 0x00014800 +#define MPC85xx_PMUXCR_SPI_MASK 0x00600000 +#define MPC85xx_PMUXCR_SPI 0x00000000 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ +#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 +#define MPC85xx_PMUXCR2_UART_TDM 0x80000000 +#define MPC85xx_PMUXCR2_UART_RES 0xC0000000 +#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 +#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 +#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 +#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 +#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 +#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 +#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 +#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 +#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 +#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 +#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 +#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 +#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 +#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 +#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 +#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 +#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 +#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 +#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 +#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 +#endif +#if defined(CONFIG_P1013) || defined(CONFIG_P1022) +#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000 +#define MPC85xx_PMUXCR2_USB 0x00150000 +#endif u8 res6[8]; u32 devdisr; /* Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 @@ -1942,32 +2052,43 @@ typedef struct ccsr_gur { u8 res9[12]; u32 pvr; /* Processor version */ u32 svr; /* System version */ - u8 res10a[8]; + u8 res10[8]; u32 rstcr; /* Reset control */ #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) - u8 res10b[76]; + u8 res11a[76]; par_io_t qe_par_io[7]; - u8 res10c[1600]; + u8 res11b[1600]; +#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \ + defined(CONFIG_P1021) || defined(CONFIG_P1025) + u8 res11a[12]; + u32 iovselsr; + u8 res11b[60]; + par_io_t qe_par_io[3]; + u8 res11c[1496]; #else - u8 res10b[1868]; + u8 res11a[1868]; #endif u32 clkdvdr; /* Clock Divide register */ - u8 res10d[1532]; + u8 res12[1532]; u32 clkocr; /* Clock out select */ - u8 res11[12]; + u8 res13[12]; u32 ddrdllcr; /* DDR DLL control */ - u8 res12[12]; + u8 res14[12]; u32 lbcdllcr; /* LBC DLL control */ - u8 res13[248]; + u8 res15[248]; u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ u32 ddrioovcr; /* DDR IO Override Control */ u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ - u8 res15[61648]; + u8 res16[52]; + u32 sdhcdcr; /* SDHC debug control register */ + u8 res17[61592]; } ccsr_gur_t; #endif +#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */ + typedef struct serdes_corenet { struct { u32 rstctl; /* Reset Control Register */ @@ -1980,6 +2101,7 @@ typedef struct serdes_corenet { #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 @@ -2016,6 +2138,9 @@ typedef struct serdes_corenet { #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 u32 res3; u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ +#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 +#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000 +#define SRDS_TTLCR0_PM_DIS 0x00004000 u32 res4[7]; } lane[24]; u32 res6[384]; @@ -2164,6 +2289,13 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; +typedef struct ccsr_usb_phy { + u8 res0[0x18]; + u32 usb_enable_override; + u8 res[0xe4]; +} ccsr_usb_phy_t; +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2186,12 +2318,14 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET +#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 +#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 -#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 @@ -2227,6 +2361,7 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 @@ -2240,6 +2375,12 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 +#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 +#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 +#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 +#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 +#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 +#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 #endif #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 @@ -2247,10 +2388,10 @@ typedef struct ccsr_pme { #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) -#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) -#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) +#define CONFIG_SYS_FSL_QMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) +#define CONFIG_SYS_FSL_BMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ @@ -2269,6 +2410,8 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_IFC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ @@ -2299,6 +2442,10 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) +#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_FM1_ADDR \ diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index 531cfc891d..9be9dca1f7 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -3,7 +3,7 @@ * The Internal Memory Map for devices with QE on them. This * is the superset of all QE devices (8360, etc.). * - * Copyright (c) 2006-2009 Freescale Semiconductor, Inc. + * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc. * Author: Shlomi Gridih <gridish@freescale.com> * * This program is free software; you can redistribute it and/or modify it @@ -15,8 +15,19 @@ #ifndef __IMMAP_QE_H__ #define __IMMAP_QE_H__ -/* QE I-RAM -*/ +#ifdef CONFIG_MPC83xx +#if defined(CONFIG_MPC8360) +#define QE_MURAM_SIZE 0xc000UL +#define MAX_QE_RISC 2 +#define QE_NUM_OF_SNUM 28 +#elif defined(CONFIG_MPC832x) +#define QE_MURAM_SIZE 0x4000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +#endif +#endif + +/* QE I-RAM */ typedef struct qe_iram { u32 iadd; /* I-RAM Address Register */ u32 idata; /* I-RAM Data Register */ @@ -25,8 +36,7 @@ typedef struct qe_iram { u8 res1[0x70]; } __attribute__ ((packed)) qe_iram_t; -/* QE Interrupt Controller -*/ +/* QE Interrupt Controller */ typedef struct qe_ic { u32 qicr; u32 qivec; @@ -49,8 +59,7 @@ typedef struct qe_ic { u8 res3[0x1C]; } __attribute__ ((packed)) qe_ic_t; -/* Communications Processor -*/ +/* Communications Processor */ typedef struct cp_qe { u32 cecr; /* QE command register */ u32 ceccr; /* QE controller configuration register */ @@ -87,8 +96,7 @@ typedef struct cp_qe { u8 res13[0x280]; } __attribute__ ((packed)) cp_qe_t; -/* QE Multiplexer -*/ +/* QE Multiplexer */ typedef struct qe_mux { u32 cmxgcr; /* CMX general clock route register */ u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ @@ -102,8 +110,7 @@ typedef struct qe_mux { u8 res0[0x1C]; } __attribute__ ((packed)) qe_mux_t; -/* QE Timers -*/ +/* QE Timers */ typedef struct qe_timers { u8 gtcfr1; /* Timer 1 2 global configuration register */ u8 res0[0x3]; @@ -133,8 +140,7 @@ typedef struct qe_timers { u8 res2[0x46]; } __attribute__ ((packed)) qe_timers_t; -/* BRG -*/ +/* BRG */ typedef struct qe_brg { u32 brgc1; /* BRG1 configuration register */ u32 brgc2; /* BRG2 configuration register */ @@ -155,8 +161,7 @@ typedef struct qe_brg { u8 res0[0x40]; } __attribute__ ((packed)) qe_brg_t; -/* SPI -*/ +/* SPI */ typedef struct spi { u8 res0[0x20]; u32 spmode; /* SPI mode register */ @@ -174,8 +179,7 @@ typedef struct spi { u8 res7[0x8]; } __attribute__ ((packed)) spi_t; -/* SI -*/ +/* SI */ typedef struct si1 { u16 siamr1; /* SI1 TDMA mode register */ u16 sibmr1; /* SI1 TDMB mode register */ @@ -222,16 +226,14 @@ typedef struct si1 { u8 res9[0xBB]; } __attribute__ ((packed)) si1_t; -/* SI Routing Tables -*/ +/* SI Routing Tables */ typedef struct sir { u8 tx[0x400]; u8 rx[0x400]; u8 res0[0x800]; } __attribute__ ((packed)) sir_t; -/* USB Controller. -*/ +/* USB Controller. */ typedef struct usb_ctlr { u8 usb_usmod; u8 usb_usadr; @@ -253,8 +255,7 @@ typedef struct usb_ctlr { u8 res6[0x22]; } __attribute__ ((packed)) usb_t; -/* MCC -*/ +/* MCC */ typedef struct mcc { u32 mcce; /* MCC event register */ u32 mccm; /* MCC mask register */ @@ -263,8 +264,7 @@ typedef struct mcc { u8 res0[0xF0]; } __attribute__ ((packed)) mcc_t; -/* QE UCC Slow -*/ +/* QE UCC Slow */ typedef struct ucc_slow { u32 gumr_l; /* UCCx general mode register (low) */ u32 gumr_h; /* UCCx general mode register (high) */ @@ -368,8 +368,7 @@ typedef struct ucc_ethernet { u8 res5[0x200 - 0x1c4]; } __attribute__ ((packed)) uec_t; -/* QE UCC Fast -*/ +/* QE UCC Fast */ typedef struct ucc_fast { u32 gumr; /* UCCx general mode register */ u32 upsmr; /* UCCx protocol-specific mode register */ @@ -403,8 +402,7 @@ typedef struct ucc_fast { uec_t ucc_eth; } __attribute__ ((packed)) ucc_fast_t; -/* QE UCC -*/ +/* QE UCC */ typedef struct ucc_common { u8 res1[0x90]; u8 guemr; @@ -419,8 +417,7 @@ typedef struct ucc { }; } __attribute__ ((packed)) ucc_t; -/* MultiPHY UTOPIA POS Controllers (UPC) -*/ +/* MultiPHY UTOPIA POS Controllers (UPC) */ typedef struct upc { u32 upgcr; /* UTOPIA/POS general configuration register */ u32 uplpa; /* UTOPIA/POS last PHY address */ @@ -476,8 +473,7 @@ typedef struct upc { u8 res2[0x150]; } __attribute__ ((packed)) upc_t; -/* SDMA -*/ +/* SDMA */ typedef struct sdma { u32 sdsr; /* Serial DMA status register */ u32 sdmr; /* Serial DMA mode register */ @@ -497,8 +493,7 @@ typedef struct sdma { u8 res2[0x38]; } __attribute__ ((packed)) sdma_t; -/* Debug Space -*/ +/* Debug Space */ typedef struct dbg { u32 bpdcr; /* Breakpoint debug command register */ u32 bpdsr; /* Breakpoint debug status register */ @@ -582,40 +577,9 @@ typedef struct qe_immap { u8 res14[0x300]; u8 res15[0x3A00]; u8 res16[0x8000]; /* 0x108000 - 0x110000 */ -#if defined(CONFIG_MPC8568) - u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */ - u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */ -#elif defined(CONFIG_MPC8569) - u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */ - u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */ -#else - u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ - u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ - u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ -#endif + u8 muram[QE_MURAM_SIZE]; } __attribute__ ((packed)) qe_map_t; extern qe_map_t *qe_immr; -#if defined(CONFIG_MPC8568) -#define QE_MURAM_SIZE 0x10000UL -#elif defined(CONFIG_MPC8569) -#define QE_MURAM_SIZE 0x20000UL -#elif defined(CONFIG_MPC8360) -#define QE_MURAM_SIZE 0xc000UL -#elif defined(CONFIG_MPC832x) -#define QE_MURAM_SIZE 0x4000UL -#endif - -#if defined(CONFIG_MPC8323) -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 -#elif defined(CONFIG_MPC8569) -#define MAX_QE_RISC 4 -#define QE_NUM_OF_SNUM 46 -#else -#define MAX_QE_RISC 2 -#define QE_NUM_OF_SNUM 28 -#endif - #endif /* __IMMAP_QE_H__ */ diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 4ddad26e81..56ac9fe6c5 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -175,7 +175,10 @@ extern inline int in_8(const volatile unsigned char __iomem *addr) extern inline void out_8(volatile unsigned char __iomem *addr, int val) { - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sync;\n" + "stb%U0%X0 %1,%0;\n" + : "=m" (*addr) + : "r" (val)); } extern inline int in_le16(const volatile unsigned short __iomem *addr) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fcee1a2428..f5bf4dd4fd 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1048,12 +1048,24 @@ #define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 #define SVR_P1014_E 0x80F901 +#define SVR_P1015 0x80E502 +#define SVR_P1015_E 0x80ED02 +#define SVR_P1016 0x80E503 +#define SVR_P1016_E 0x80ED03 +#define SVR_P1017 0x80F700 +#define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 #define SVR_P1020_E 0x80EC00 #define SVR_P1021 0x80E401 #define SVR_P1021_E 0x80EC01 #define SVR_P1022 0x80E600 #define SVR_P1022_E 0x80EE00 +#define SVR_P1023 0x80F600 +#define SVR_P1023_E 0x80FE00 +#define SVR_P1024 0x80E402 +#define SVR_P1024_E 0x80EC02 +#define SVR_P1025 0x80E403 +#define SVR_P1025_E 0x80EC03 #define SVR_P2010 0x80E300 #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 4719f8c696..aaa5add1fa 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -186,6 +186,12 @@ int __board_flash_wp_on(void) } int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on"))); +void __cpu_secondary_init_r(void) +{ +} +void cpu_secondary_init_r(void) +__attribute__((weak, alias("__cpu_secondary_init_r"))); + static int init_func_ram (void) { #ifdef CONFIG_BOARD_TYPES @@ -453,9 +459,13 @@ void board_init_f (ulong bootflag) debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); #ifdef CONFIG_LCD +#ifdef CONFIG_FB_ADDR + gd->fb_base = CONFIG_FB_ADDR; +#else /* reserve memory for LCD display (always full pages) */ addr = lcd_setmem (addr); gd->fb_base = addr; +#endif /* CONFIG_FB_ADDR */ #endif /* CONFIG_LCD */ #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) @@ -798,6 +808,14 @@ void board_init_r (gd_t *id, ulong dest_addr) env_relocate (); /* + * after non-volatile devices & environment is setup and cpu code have + * another round to deal with any initialization that might require + * full access to the environment or loading of some image (firmware) + * from a non-volatile device + */ + cpu_secondary_init_r(); + + /* * Fill in missing fields of bd_info. * We do this here, where we have "normal" access to the * environment; we used to do this still running from ROM, diff --git a/arch/powerpc/lib/bootcount.c b/arch/powerpc/lib/bootcount.c index 07ef28d1b4..f9ce539ecb 100644 --- a/arch/powerpc/lib/bootcount.c +++ b/arch/powerpc/lib/bootcount.c @@ -51,7 +51,7 @@ #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) #endif /* defined(CONFIG_MPC8260) */ -#if defined(CONFIG_MPC8360) +#if defined(CONFIG_QE) #include <asm/immap_qe.h> #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 116d81bec6..e01787dcb7 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -33,6 +33,7 @@ #include <bzlib.h> #include <environment.h> #include <asm/byteorder.h> +#include <asm/mp.h> #if defined(CONFIG_OF_LIBFDT) #include <fdt.h> @@ -95,7 +96,7 @@ static void boot_jump_linux(bootm_headers_t *images) debug (" Booting using OF flat tree...\n"); WATCHDOG_RESET (); (*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC, - CONFIG_SYS_BOOTMAPSZ, 0, 0); + getenv_bootm_mapsize(), 0, 0); /* does not return */ } else #endif @@ -166,6 +167,10 @@ void arch_lmb_reserve(struct lmb *lmb) sp -= 4096; lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp)); +#ifdef CONFIG_MP + cpu_mp_lmb_reserve(lmb); +#endif + return ; } @@ -181,7 +186,6 @@ static void boot_prep_linux(void) static int boot_cmdline_linux(bootm_headers_t *images) { - ulong bootmap_base = getenv_bootm_low(); ulong of_size = images->ft_len; struct lmb *lmb = &images->lmb; ulong *cmd_start = &images->cmdline_start; @@ -191,7 +195,7 @@ static int boot_cmdline_linux(bootm_headers_t *images) if (!of_size) { /* allocate space and init command line */ - ret = boot_get_cmdline (lmb, cmd_start, cmd_end, bootmap_base); + ret = boot_get_cmdline (lmb, cmd_start, cmd_end); if (ret) { puts("ERROR with allocation of cmdline\n"); return ret; @@ -203,7 +207,6 @@ static int boot_cmdline_linux(bootm_headers_t *images) static int boot_bd_t_linux(bootm_headers_t *images) { - ulong bootmap_base = getenv_bootm_low(); ulong of_size = images->ft_len; struct lmb *lmb = &images->lmb; bd_t **kbd = &images->kbd; @@ -212,7 +215,7 @@ static int boot_bd_t_linux(bootm_headers_t *images) if (!of_size) { /* allocate space for kernel copy of board info */ - ret = boot_get_kbd (lmb, kbd, bootmap_base); + ret = boot_get_kbd (lmb, kbd); if (ret) { puts("ERROR with allocation of kernel bd\n"); return ret; @@ -230,13 +233,16 @@ static int boot_body_linux(bootm_headers_t *images) ulong *initrd_start = &images->initrd_start; ulong *initrd_end = &images->initrd_end; #if defined(CONFIG_OF_LIBFDT) - ulong bootmap_base = getenv_bootm_low(); ulong of_size = images->ft_len; char **of_flat_tree = &images->ft_addr; #endif int ret; +#if defined(CONFIG_OF_LIBFDT) + boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); +#endif + /* allocate space and init command line */ ret = boot_cmdline_linux(images); if (ret) @@ -252,8 +258,8 @@ static int boot_body_linux(bootm_headers_t *images) if (ret) return ret; -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_SYS_BOOTMAPSZ) - ret = boot_relocate_fdt(lmb, bootmap_base, of_flat_tree, &of_size); +#if defined(CONFIG_OF_LIBFDT) + ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); if (ret) return ret; @@ -291,7 +297,7 @@ static int boot_body_linux(bootm_headers_t *images) if (*initrd_start && *initrd_end) fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); } -#endif /* CONFIG_OF_LIBFDT && CONFIG_SYS_BOOTMAPSZ */ +#endif /* CONFIG_OF_LIBFDT */ return 0; } diff --git a/arch/sh/config.mk b/arch/sh/config.mk index cd851f59c4..07ff8b9348 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -23,17 +23,11 @@ CROSS_COMPILE ?= sh4-linux- -STANDALONE_LOAD_ADDR = 0x8C000000 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000 ifeq ($(CPU),sh2) -STANDALONE_LOAD_ADDR += -EB +CONFIG_STANDALONE_LOAD_ADDR += -EB endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE) LDFLAGS_FINAL = --gc-sections - -ifdef CONFIG_SYS_LDSCRIPT -LDSCRIPT := $(subst ",,$(CONFIG_SYS_LDSCRIPT)) -else -LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds -endif diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk index 4de6515ef4..cae7478e28 100644 --- a/arch/sparc/config.mk +++ b/arch/sparc/config.mk @@ -23,6 +23,6 @@ CROSS_COMPILE ?= sparc-elf- -STANDALONE_LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) -T sparc.lds PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ diff --git a/arch/sparc/cpu/leon2/cpu_init.c b/arch/sparc/cpu/leon2/cpu_init.c index a24f778c6d..795c7d7a79 100644 --- a/arch/sparc/cpu/leon2/cpu_init.c +++ b/arch/sparc/cpu/leon2/cpu_init.c @@ -47,9 +47,9 @@ struct { * initialize a bunch of registers. * * Run from FLASH/PROM: - * - until memory controller is set up, only registers avaiable + * - until memory controller is set up, only registers available * - no global variables available for writing - * - constants avaiable + * - constants available */ void cpu_init_f(void) diff --git a/arch/sparc/cpu/leon3/cpu_init.c b/arch/sparc/cpu/leon3/cpu_init.c index be22ec26aa..cba9d0eb40 100644 --- a/arch/sparc/cpu/leon3/cpu_init.c +++ b/arch/sparc/cpu/leon3/cpu_init.c @@ -57,9 +57,9 @@ struct { * initialize a bunch of registers. * * Run from FLASH/PROM: - * - until memory controller is set up, only registers avaiable + * - until memory controller is set up, only registers available * - no global variables available for writing - * - constants avaiable + * - constants available */ void cpu_init_f(void) diff --git a/arch/i386/config.mk b/arch/x86/config.mk index 47e0fb4c78..ee23c9f87d 100644 --- a/arch/i386/config.mk +++ b/arch/x86/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -STANDALONE_LOAD_ADDR = 0x40000 +CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 PLATFORM_CPPFLAGS += -fno-strict-aliasing PLATFORM_CPPFLAGS += -Wstrict-prototypes @@ -39,4 +39,3 @@ PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions LDFLAGS_FINAL += --gc-sections -pie -LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds diff --git a/arch/i386/cpu/Makefile b/arch/x86/cpu/Makefile index ddde83c91d..ddde83c91d 100644 --- a/arch/i386/cpu/Makefile +++ b/arch/x86/cpu/Makefile diff --git a/arch/i386/cpu/config.mk b/arch/x86/cpu/config.mk index 9b2e2c9fe1..d1b528a437 100644 --- a/arch/i386/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -23,7 +23,7 @@ CROSS_COMPILE ?= i386-linux- -PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror +PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386 -Werror # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=0xffff0000 diff --git a/arch/i386/cpu/cpu.c b/arch/x86/cpu/cpu.c index 2339cd41bb..0c5d7c3d53 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -1,6 +1,9 @@ /* + * (C) Copyright 2008-2011 + * Graeme Russ, <graeme.russ@gmail.com> + * * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> @@ -29,18 +32,16 @@ * MA 02111-1307 USA */ -/* - * CPU specific code - */ - #include <common.h> #include <command.h> #include <asm/processor.h> #include <asm/processor-flags.h> #include <asm/interrupt.h> -/* Constructor for a conventional segment GDT (or LDT) entry */ -/* This is a macro so it can be used in initializers */ +/* + * Constructor for a conventional segment GDT (or LDT) entry + * This is a macro so it can be used in initialisers + */ #define GDT_ENTRY(flags, base, limit) \ ((((base) & 0xff000000ULL) << (56-24)) | \ (((flags) & 0x0000f0ffULL) << 40) | \ @@ -48,10 +49,6 @@ (((base) & 0x00ffffffULL) << 16) | \ (((limit) & 0x0000ffffULL))) -/* - * Set up the GDT - */ - struct gdt_ptr { u16 len; u32 ptr; @@ -59,8 +56,10 @@ struct gdt_ptr { static void reload_gdt(void) { - /* There are machines which are known to not boot with the GDT - being 8-byte unaligned. Intel recommends 16 byte alignment. */ + /* + * There are machines which are known to not boot with the GDT + * being 8-byte unaligned. Intel recommends 16 byte alignment + */ static const u64 boot_gdt[] __attribute__((aligned(16))) = { /* CS: code, read/execute, 4 GB, base 0 */ [GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff), @@ -86,7 +85,6 @@ static void reload_gdt(void) : : "m" (gdt) : "ecx"); } - int x86_cpu_init_f(void) { const u32 em_rst = ~X86_CR0_EM; @@ -125,7 +123,9 @@ int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { printf ("resetting ...\n"); - udelay(50000); /* wait 50 ms */ + + /* wait 50 ms */ + udelay(50000); disable_interrupts(); reset_cpu(0); @@ -136,7 +136,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) void flush_cache (unsigned long dummy1, unsigned long dummy2) { asm("wbinvd\n"); - return; } void __attribute__ ((regparm(0))) generate_gpf(void); @@ -150,7 +149,7 @@ asm(".globl generate_gpf\n" void __reset_cpu(ulong addr) { - printf("Resetting using i386 Triple Fault\n"); + printf("Resetting using x86 Triple Fault\n"); set_vector(13, generate_gpf); /* general protection fault handler */ set_vector(8, generate_gpf); /* double fault handler */ generate_gpf(); /* start the show */ diff --git a/arch/i386/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 1cefe02c86..62bcadc486 100644 --- a/arch/i386/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -1,9 +1,9 @@ /* - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. + * (C) Copyright 2008-2011 + * Graeme Russ, <graeme.russ@gmail.com> * * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * Portions of this file are derived from the Linux kernel source * Copyright (C) 1991, 1992 Linus Torvalds @@ -45,7 +45,7 @@ * read/write functions for the control registers and messing everything up. * A memory clobber would solve the problem, but would prevent reordering of * all loads stores around it, which can hurt performance. Solution is to - * use a variable and mimic reads and writes to it to enforce serialization + * use a variable and mimic reads and writes to it to enforce serialisation */ static unsigned long __force_order; diff --git a/arch/i386/cpu/resetvec.S b/arch/x86/cpu/resetvec.S index d9222dd2fc..c690d2516e 100644 --- a/arch/i386/cpu/resetvec.S +++ b/arch/x86/cpu/resetvec.S @@ -1,7 +1,8 @@ /* - * U-boot - i386 Startup Code + * U-boot - x86 Startup Code * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se> + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/cpu/sc520/Makefile b/arch/x86/cpu/sc520/Makefile index 54260b6107..694b61ee42 100644 --- a/arch/i386/cpu/sc520/Makefile +++ b/arch/x86/cpu/sc520/Makefile @@ -33,6 +33,7 @@ LIB := $(obj)lib$(SOC).o COBJS-$(CONFIG_SYS_SC520) += sc520.o COBJS-$(CONFIG_PCI) += sc520_pci.o +COBJS-$(CONFIG_SYS_SC520_RESET) += sc520_reset.o COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c index d0c313b91a..8c410a2337 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/x86/cpu/sc520/sc520.c @@ -1,6 +1,9 @@ /* + * (C) Copyright 2008-2011 + * Graeme Russ, <graeme.russ@gmail.com> + * * (C) Copyright 2002 - * Daniel Engstr�m, Omicron Ceti AB <daniel@omicron.se>. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -21,9 +24,6 @@ * MA 02111-1307 USA */ -/* stuff specific for the sc520, - * but idependent of implementation */ - #include <common.h> #include <asm/io.h> #include <asm/processor-flags.h> @@ -65,13 +65,3 @@ int cpu_init_r(void) return x86_cpu_init_r(); } -#ifdef CONFIG_SYS_SC520_RESET -void reset_cpu(ulong addr) -{ - printf("Resetting using SC520 MMCR\n"); - /* Write a '1' to the SYS_RST of the RESCFG MMCR */ - writeb(0x01, &sc520_mmcr->rescfg); - - /* NOTREACHED */ -} -#endif diff --git a/arch/i386/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S index 22f5225311..a33f94f491 100644 --- a/arch/i386/cpu/sc520/sc520_car.S +++ b/arch/x86/cpu/sc520/sc520_car.S @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010 - * Graeme Russ <graeme.russ@gmail.com>. + * (C) Copyright 2010-2011 + * Graeme Russ, <graeme.russ@gmail.com> * * See file CREDITS for list of people who contributed to this * project. @@ -21,7 +21,6 @@ * MA 02111-1307 USA */ - #include <config.h> #include <asm/processor-flags.h> #include <asm/ic/sc520.h> diff --git a/arch/i386/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c index b91773435e..8cd7ffecdb 100644 --- a/arch/i386/cpu/sc520/sc520_pci.c +++ b/arch/x86/cpu/sc520/sc520_pci.c @@ -1,6 +1,9 @@ /* + * (C) Copyright 2008-2011 + * Graeme Russ, <graeme.russ@gmail.com> + * * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -21,8 +24,6 @@ * MA 02111-1307 USA */ -/* stuff specific for the sc520, but independent of implementation */ - #include <common.h> #include <pci.h> #include <asm/io.h> @@ -54,7 +55,6 @@ static struct { { SC520_IRQ15, 1, 0x80 } }; - /* The interrupt used for PCI INTA-INTD */ int sc520_pci_ints[15] = { -1, -1, -1, -1, -1, -1, -1, -1, @@ -68,9 +68,8 @@ int pci_sc520_set_irq(int pci_pin, int irq) u8 tmpb; u16 tmpw; -# if 1 - printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); -#endif + debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); + if (irq < 0 || irq > 15) { return -1; /* illegal irq */ } @@ -138,5 +137,4 @@ void pci_sc520_init(struct pci_controller *hose) /* enable target memory acceses on host brige */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - } diff --git a/arch/x86/cpu/sc520/sc520_reset.c b/arch/x86/cpu/sc520/sc520_reset.c new file mode 100644 index 0000000000..79ef976838 --- /dev/null +++ b/arch/x86/cpu/sc520/sc520_reset.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2011 + * Graeme Russ, <graeme.russ@gmail.com> + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/ic/sc520.h> + +DECLARE_GLOBAL_DATA_PTR; + +void reset_cpu(ulong addr) +{ + printf("Resetting using SC520 MMCR\n"); + /* Write a '1' to the SYS_RST of the RESCFG MMCR */ + writeb(0x01, &sc520_mmcr->rescfg); + + /* NOTREACHED */ +} diff --git a/arch/i386/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c index d5ab55df06..f3623f53f2 100644 --- a/arch/i386/cpu/sc520/sc520_sdram.c +++ b/arch/x86/cpu/sc520/sc520_sdram.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010 - * Graeme Russ <graeme.russ@gmail.com>. + * (C) Copyright 2010,2011 + * Graeme Russ, <graeme.russ@gmail.com> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c index 6e5e346303..ac58d25970 100644 --- a/arch/i386/cpu/sc520/sc520_ssi.c +++ b/arch/x86/cpu/sc520/sc520_ssi.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -21,8 +21,6 @@ * MA 02111-1307 USA */ -/* stuff specific for the sc520, but independent of implementation */ - #include <common.h> #include <asm/io.h> #include <asm/ic/ssi.h> @@ -77,7 +75,6 @@ u8 ssi_txrx_byte(u8 data) return readb(&sc520_mmcr->ssircv); } - void ssi_tx_byte(u8 data) { writeb(data, &sc520_mmcr->ssixmit); diff --git a/arch/i386/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c index d5617e91f6..1bcfe67c94 100644 --- a/arch/i386/cpu/sc520/sc520_timer.c +++ b/arch/x86/cpu/sc520/sc520_timer.c @@ -1,6 +1,9 @@ /* + * (C) Copyright 2008-2011 + * Graeme Russ, <graeme.russ@gmail.com> + * * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -21,8 +24,6 @@ * MA 02111-1307 USA */ -/* stuff specific for the sc520, but independent of implementation */ - #include <common.h> #include <asm/io.h> #include <asm/interrupt.h> diff --git a/arch/i386/cpu/start.S b/arch/x86/cpu/start.S index 00313897ce..7ccc076fec 100644 --- a/arch/i386/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -1,7 +1,11 @@ /* - * U-boot - i386 Startup Code + * U-boot - x86 Startup Code * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se> + * (C) Copyright 2008-2011 + * Graeme Russ, <graeme.russ@gmail.com> + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -22,19 +26,17 @@ * MA 02111-1307 USA */ - #include <config.h> #include <version.h> #include <asm/global_data.h> #include <asm/processor-flags.h> - .section .text .code32 .globl _start .type _start, @function -.globl _i386boot_start -_i386boot_start: +.globl _x86boot_start +_x86boot_start: /* * This is the fail safe 32-bit bootstrap entry point. The * following code is not executed from a cold-reset (actually, a @@ -56,8 +58,8 @@ _i386boot_start: _start: /* This is the 32-bit cold-reset entry point */ - movl $0x18, %eax /* Load our segement registes, the - * gdt have already been loaded by start16.S */ + /* Load the segement registes to match the gdt loaded in start16.S */ + movl $0x18, %eax movw %ax, %fs movw %ax, %ds movw %ax, %gs @@ -82,21 +84,13 @@ car_init_ret: * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack */ movl $CONFIG_SYS_INIT_SP_ADDR, %esp - movl $CONFIG_SYS_INIT_GD_ADDR, %ebp - - /* Set Boot Flags in Global Data */ - movl %ebx, (GD_FLAGS * 4)(%ebp) - - /* Determine our load offset (and put in Global Data) */ - call 1f -1: popl %ecx - subl $1b, %ecx - movl %ecx, (GD_LOAD_OFF * 4)(%ebp) /* Set parameter to board_init_f() to boot flags */ - movl (GD_FLAGS * 4)(%ebp), %eax + xorl %eax, %eax + movw %bx, %ax - call board_init_f /* Enter, U-boot! */ + /* Enter, U-boot! */ + call board_init_f /* indicate (lack of) progress */ movw $0x85, %ax diff --git a/arch/i386/cpu/start16.S b/arch/x86/cpu/start16.S index 7dc5358366..f1b9d0a0c9 100644 --- a/arch/i386/cpu/start16.S +++ b/arch/x86/cpu/start16.S @@ -1,7 +1,11 @@ /* - * U-boot - i386 Startup Code + * U-boot - x86 Startup Code * - * Copyright (c) 2002, 2003 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se> + * (C) Copyright 2008-2011 + * Graeme Russ, <graeme.russ@gmail.com> + * + * (C) Copyright 2002,2003 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index 98a548d62e..55974228b5 100644 --- a/arch/i386/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -21,6 +21,7 @@ * MA 02111-1307 USA */ +#include <config.h> OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) ENTRY(_start) @@ -89,8 +90,8 @@ SECTIONS * Reset Vector at the end of the Flash ROM */ . = START_16; - .start16 : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); } + .start16 : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); } . = RESET_VEC_LOC; - .resetvec : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); } + .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); } } diff --git a/arch/i386/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index c7a38f237a..c7a38f237a 100644 --- a/arch/i386/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h diff --git a/arch/i386/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index 140095117e..140095117e 100644 --- a/arch/i386/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h diff --git a/arch/i386/include/asm/byteorder.h b/arch/x86/include/asm/byteorder.h index 7dfeb8bbed..7dfeb8bbed 100644 --- a/arch/i386/include/asm/byteorder.h +++ b/arch/x86/include/asm/byteorder.h diff --git a/arch/i386/include/asm/config.h b/arch/x86/include/asm/config.h index 049c44eaf8..049c44eaf8 100644 --- a/arch/i386/include/asm/config.h +++ b/arch/x86/include/asm/config.h diff --git a/arch/i386/include/asm/e820.h b/arch/x86/include/asm/e820.h index d155ce9cee..d155ce9cee 100644 --- a/arch/i386/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h diff --git a/arch/i386/include/asm/errno.h b/arch/x86/include/asm/errno.h index 4c82b503d9..4c82b503d9 100644 --- a/arch/i386/include/asm/errno.h +++ b/arch/x86/include/asm/errno.h diff --git a/arch/i386/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index f8a16d646f..f8a16d646f 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h diff --git a/arch/i386/include/asm/i8254.h b/arch/x86/include/asm/i8254.h index aafdfb8060..aafdfb8060 100644 --- a/arch/i386/include/asm/i8254.h +++ b/arch/x86/include/asm/i8254.h diff --git a/arch/i386/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index 774d7a31e7..774d7a31e7 100644 --- a/arch/i386/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h diff --git a/arch/i386/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h index e35cbd887a..e35cbd887a 100644 --- a/arch/i386/include/asm/ibmpc.h +++ b/arch/x86/include/asm/ibmpc.h diff --git a/arch/i386/include/asm/ic/pci.h b/arch/x86/include/asm/ic/pci.h index 2e4376b9b0..2e4376b9b0 100644 --- a/arch/i386/include/asm/ic/pci.h +++ b/arch/x86/include/asm/ic/pci.h diff --git a/arch/i386/include/asm/ic/sc520.h b/arch/x86/include/asm/ic/sc520.h index 956c1c2636..956c1c2636 100644 --- a/arch/i386/include/asm/ic/sc520.h +++ b/arch/x86/include/asm/ic/sc520.h diff --git a/arch/i386/include/asm/ic/ssi.h b/arch/x86/include/asm/ic/ssi.h index bd48eab161..bd48eab161 100644 --- a/arch/i386/include/asm/ic/ssi.h +++ b/arch/x86/include/asm/ic/ssi.h diff --git a/arch/i386/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index d32ef8b190..be52fe40d0 100644 --- a/arch/i386/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -29,10 +29,10 @@ #include <asm/types.h> -/* arch/i386/cpu/interrupts.c */ +/* arch/x86/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); -/* arch/i386/lib/interupts.c */ +/* arch/x86/lib/interupts.c */ void disable_irq(int irq); void enable_irq(int irq); diff --git a/arch/i386/include/asm/io.h b/arch/x86/include/asm/io.h index 9b757d489e..9b757d489e 100644 --- a/arch/i386/include/asm/io.h +++ b/arch/x86/include/asm/io.h diff --git a/arch/i386/include/asm/ioctl.h b/arch/x86/include/asm/ioctl.h index b279fe06df..b279fe06df 100644 --- a/arch/i386/include/asm/ioctl.h +++ b/arch/x86/include/asm/ioctl.h diff --git a/arch/i386/include/asm/ist.h b/arch/x86/include/asm/ist.h index 7e5dff1de0..7e5dff1de0 100644 --- a/arch/i386/include/asm/ist.h +++ b/arch/x86/include/asm/ist.h diff --git a/arch/i386/include/asm/pci.h b/arch/x86/include/asm/pci.h index 050a2bb868..050a2bb868 100644 --- a/arch/i386/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h diff --git a/arch/i386/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h index 5529f32702..5529f32702 100644 --- a/arch/i386/include/asm/posix_types.h +++ b/arch/x86/include/asm/posix_types.h diff --git a/arch/i386/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index 7a3e836eb2..7a3e836eb2 100644 --- a/arch/i386/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h diff --git a/arch/i386/include/asm/processor.h b/arch/x86/include/asm/processor.h index 22a129813c..22a129813c 100644 --- a/arch/i386/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h diff --git a/arch/i386/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index a727dbfb05..a727dbfb05 100644 --- a/arch/i386/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h diff --git a/arch/i386/include/asm/realmode.h b/arch/x86/include/asm/realmode.h index 9177e4ec0d..9177e4ec0d 100644 --- a/arch/i386/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h diff --git a/arch/i386/include/asm/string.h b/arch/x86/include/asm/string.h index 3643a79fdf..3643a79fdf 100644 --- a/arch/i386/include/asm/string.h +++ b/arch/x86/include/asm/string.h diff --git a/arch/i386/include/asm/types.h b/arch/x86/include/asm/types.h index 9a40e383eb..9a40e383eb 100644 --- a/arch/i386/include/asm/types.h +++ b/arch/x86/include/asm/types.h diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/x86/include/asm/u-boot-x86.h index 7b39bd2ae0..944e1a2005 100644 --- a/arch/i386/include/asm/u-boot-i386.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -35,7 +35,7 @@ void timer_isr(void *); typedef void (timer_fnc_t) (void); int register_timer_isr (timer_fnc_t *isr_func); -/* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */ +/* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */ int timer_init(void); int dram_init_f(void); @@ -51,7 +51,7 @@ void setup_pcat_compatibility(void); void isa_unmap_rom(u32 addr); u32 isa_map_rom(u32 bus_addr, int size); -/* arch/i386/lib/... */ +/* arch/x86/lib/... */ int video_bios_init(void); int video_init(void); diff --git a/arch/i386/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h index a43b3aaded..a43b3aaded 100644 --- a/arch/i386/include/asm/u-boot.h +++ b/arch/x86/include/asm/u-boot.h diff --git a/arch/i386/include/asm/unaligned.h b/arch/x86/include/asm/unaligned.h index 6cecbbb211..6cecbbb211 100644 --- a/arch/i386/include/asm/unaligned.h +++ b/arch/x86/include/asm/unaligned.h diff --git a/arch/i386/include/asm/video/edid.h b/arch/x86/include/asm/video/edid.h index 928c342b33..928c342b33 100644 --- a/arch/i386/include/asm/video/edid.h +++ b/arch/x86/include/asm/video/edid.h diff --git a/arch/i386/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index b6266e456a..b6266e456a 100644 --- a/arch/i386/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h diff --git a/arch/i386/lib/Makefile b/arch/x86/lib/Makefile index 71e94f76f3..71e94f76f3 100644 --- a/arch/i386/lib/Makefile +++ b/arch/x86/lib/Makefile diff --git a/arch/i386/lib/bios.S b/arch/x86/lib/bios.S index 48f1b81122..660a244394 100644 --- a/arch/i386/lib/bios.S +++ b/arch/x86/lib/bios.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -42,7 +42,6 @@ * a general purpose replacement for a real BIOS !! */ - .section .bios, "ax" .code16 .org 0 diff --git a/arch/i386/lib/bios.h b/arch/x86/lib/bios.h index 4901f8917a..3c8d61a6f4 100644 --- a/arch/i386/lib/bios.h +++ b/arch/x86/lib/bios.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -57,7 +57,7 @@ #define OFFS_FLAGS 44 /* 16bit */ #define SEGMENT 0x40 -#define STACK 0x800 /* stack at 0x40:0x800 -> 0x800 */ +#define STACK 0x800 /* stack at 0x40:0x800 -> 0x800 */ /* save general registers */ /* save some segments */ @@ -67,28 +67,26 @@ /* setup BIOS stackpointer */ #define MAKE_BIOS_STACK \ - pushal ; \ - pushw %ds ; \ - pushw %gs ; \ - pushw %es ; \ - pushw %ss ; \ - popw %gs ; \ - movw $SEGMENT,%ax ; \ - movw %ax,%ds ; \ - movw %ax,%es ; \ - movw %ax,%ss ; \ - movw %sp,%bp ; \ - movw $STACK,%sp + pushal; \ + pushw %ds; \ + pushw %gs; \ + pushw %es; \ + pushw %ss; \ + popw %gs; \ + movw $SEGMENT, %ax; \ + movw %ax, %ds; \ + movw %ax, %es; \ + movw %ax, %ss; \ + movw %sp, %bp; \ + movw $STACK, %sp #define RESTORE_CALLERS_STACK \ - pushw %gs ; /* restore callers stack segment */ \ - popw %ss ; \ - movw %bp,%sp ; /* restore stackpointer */ \ - \ - popw %es ; /* restore segment selectors */ \ - popw %gs ; \ - popw %ds ; \ - \ - popal /* restore GP registers */ + pushw %gs; /* restore callers stack segment */ \ + popw %ss; \ + movw %bp, %sp; /* restore stackpointer */ \ + popw %es; /* restore segment selectors */ \ + popw %gs; \ + popw %ds; \ + popal /* restore GP registers */ #endif diff --git a/arch/i386/lib/bios_pci.S b/arch/x86/lib/bios_pci.S index 9e412e5e4c..9e412e5e4c 100644 --- a/arch/i386/lib/bios_pci.S +++ b/arch/x86/lib/bios_pci.S diff --git a/arch/i386/lib/bios_setup.c b/arch/x86/lib/bios_setup.c index 75407c173c..6949b35069 100644 --- a/arch/i386/lib/bios_setup.c +++ b/arch/x86/lib/bios_setup.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -21,7 +21,6 @@ * MA 02111-1307 USA */ - /* * Partly based on msbios.c from rolo 1.6: *---------------------------------------------------------------------- diff --git a/arch/i386/lib/board.c b/arch/x86/lib/board.c index e0f9803e5e..df54222211 100644 --- a/arch/i386/lib/board.c +++ b/arch/x86/lib/board.c @@ -1,9 +1,12 @@ /* + * (C) Copyright 2008-2011 + * Graeme Russ, <graeme.russ@gmail.com> + * * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> @@ -38,7 +41,7 @@ #include <net.h> #include <ide.h> #include <serial.h> -#include <asm/u-boot-i386.h> +#include <asm/u-boot-x86.h> #include <elf.h> #ifdef CONFIG_BITBANGMII @@ -103,13 +106,6 @@ static int display_banner (void) return (0); } -/* - * WARNING: this code looks "cleaner" than the PowerPC version, but - * has the disadvantage that you either get nothing, or everything. - * On PowerPC, you might see "DRAM: " before the system hangs - which - * gives a simple yet clear indication which part of the - * initialization if failing. - */ static int display_dram_config (void) { int i; @@ -141,7 +137,6 @@ static void display_flash_config (ulong size) * can relocate the monitor code to RAM. */ - /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -251,13 +246,13 @@ static int do_elf_reloc_fixups(void) return 0; } -/* - * Load U-Boot into RAM, initialize BSS, perform relocation adjustments - */ +/* Load U-Boot into RAM, initialize BSS, perform relocation adjustments */ void board_init_f(ulong boot_flags) { init_fnc_t **init_fnc_ptr; + gd->flags = boot_flags; + for (init_fnc_ptr = init_sequence_f; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) hang(); diff --git a/arch/i386/lib/bootm.c b/arch/x86/lib/bootm.c index b36e58d9ec..a21a21f1f7 100644 --- a/arch/i386/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -5,10 +5,13 @@ * * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -17,8 +20,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #include <common.h> diff --git a/arch/i386/lib/interrupts.c b/arch/x86/lib/interrupts.c index 5a28278280..a2c598f9a4 100644 --- a/arch/i386/lib/interrupts.c +++ b/arch/x86/lib/interrupts.c @@ -1,21 +1,21 @@ /* * (C) Copyright 2009 - * Graeme Russ, graeme.russ@gmail.com + * Graeme Russ, <graeme.russ@gmail.com> * * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * Daniel Hellstrom, Gaisler Research, <daniel@gaisler.com> * * (C) Copyright 2006 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de + * Detlev Zundel, DENX Software Engineering, <dzu@denx.de> * * (C) Copyright -2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> * * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. + * Josh Huber, Mission Critical Linux, Inc, <huber@mclx.com> * * See file CREDITS for list of people who contributed to this * project. @@ -38,11 +38,11 @@ /* * This file contains the high-level API for the interrupt sub-system - * of the i386 port of U-Boot. Most of the functionality has been + * of the x86 port of U-Boot. Most of the functionality has been * shamelessly stolen from the leon2 / leon3 ports of U-Boot. * Daniel Hellstrom, Detlev Zundel, Wolfgang Denk and Josh Huber are * credited for the corresponding work on those ports. The original - * interrupt handling routines for the i386 port were written by + * interrupt handling routines for the x86 port were written by * Daniel Engström */ diff --git a/arch/i386/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c index 67e6e97e35..364c435837 100644 --- a/arch/i386/lib/pcat_interrupts.c +++ b/arch/x86/lib/pcat_interrupts.c @@ -1,9 +1,9 @@ /* * (C) Copyright 2009 - * Graeme Russ, graeme.russ@gmail.com + * Graeme Russ, <graeme.russ@gmail.com> * * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/lib/pcat_timer.c b/arch/x86/lib/pcat_timer.c index 1373fd125c..1911c6c19d 100644 --- a/arch/i386/lib/pcat_timer.c +++ b/arch/x86/lib/pcat_timer.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/lib/pci.c b/arch/x86/lib/pci.c index 9020e7ce76..e791e88bd4 100644 --- a/arch/i386/lib/pci.c +++ b/arch/x86/lib/pci.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -54,10 +54,9 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) class_code &= 0xffffff00; class_code >>= 8; -#if 0 - printf("PCI Header Vendor %04x device %04x class %06x\n", + debug("PCI Header Vendor %04x device %04x class %06x\n", vendor, device, class_code); -#endif + /* Enable the rom addess decoder */ pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK); pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr_reg); @@ -70,13 +69,12 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest) size = (~(addr_reg&PCI_ROM_ADDRESS_MASK))+1; -#if 0 - printf("ROM is %d bytes\n", size); -#endif + debug("ROM is %d bytes\n", size); + rom_addr = pci_get_rom_window(hose, size); -#if 0 - printf("ROM mapped at %x \n", rom_addr); -#endif + + debug("ROM mapped at %x\n", rom_addr); + pci_write_config_dword(dev, PCI_ROM_ADDRESS, pci_phys_to_mem(dev, rom_addr) |PCI_ROM_ADDRESS_ENABLE); diff --git a/arch/i386/lib/pci_type1.c b/arch/x86/lib/pci_type1.c index 225ae4a990..8ce5b33e3d 100644 --- a/arch/i386/lib/pci_type1.c +++ b/arch/x86/lib/pci_type1.c @@ -1,15 +1,30 @@ /* - * Support for type PCI configuration cycles. - * based on pci_indirect.c + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * - * Copyright (C) 2002 Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * See file CREDITS for list of people who contributed to this + * project. * * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ +/* + * Support for type PCI configuration cycles. + * based on pci_indirect.c + */ #include <common.h> #include <asm/io.h> #include <pci.h> diff --git a/arch/i386/lib/realmode.c b/arch/x86/lib/realmode.c index 2dda95b064..5be827c66b 100644 --- a/arch/i386/lib/realmode.c +++ b/arch/x86/lib/realmode.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -26,10 +26,8 @@ #include <asm/ptrace.h> #include <asm/realmode.h> - #define REALMODE_MAILBOX ((char*)0xe00) - extern ulong __realmode_start; extern ulong __realmode_size; extern char realmode_enter; @@ -57,13 +55,11 @@ int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out) { /* setup out thin bios emulation */ - if (bios_setup()) { + if (bios_setup()) return -1; - } - if (realmode_setup()) { + if (realmode_setup()) return -1; - } in->eip = off; in->xcs = seg; diff --git a/arch/i386/lib/realmode_switch.S b/arch/x86/lib/realmode_switch.S index d6c74ecd79..fce4eccab0 100644 --- a/arch/i386/lib/realmode_switch.S +++ b/arch/x86/lib/realmode_switch.S @@ -21,7 +21,6 @@ * MA 02111-1307 USA */ - /* 32bit -> 16bit -> 32bit mode switch code */ /* diff --git a/arch/i386/lib/timer.c b/arch/x86/lib/timer.c index 5cb1f54fb5..8fc68cdcb8 100644 --- a/arch/i386/lib/timer.c +++ b/arch/x86/lib/timer.c @@ -1,6 +1,9 @@ /* + * (C) Copyright 2008,2009 + * Graeme Russ, <graeme.russ@gmail.com> + * * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/lib/video.c b/arch/x86/lib/video.c index c58ed104cc..b29075c490 100644 --- a/arch/i386/lib/video.c +++ b/arch/x86/lib/video.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -30,7 +30,6 @@ #include <asm/io.h> #include <asm/pci.h> - /* basic textmode I/O from linux kernel */ static char *vidmem = (char *)0xb8000; static int vidport; @@ -42,9 +41,9 @@ static void beep(int dur) int i; outb_p(3, 0x61); - for (i=0;i<10*dur;i++) { + for (i = 0; i < 10*dur; i++) udelay(1000); - } + outb_p(0, 0x61); } @@ -52,8 +51,8 @@ static void scroll(void) { int i; - memcpy ( vidmem, vidmem + cols * 2, ( lines - 1 ) * cols * 2 ); - for ( i = ( lines - 1 ) * cols * 2; i < lines * cols * 2; i += 2 ) + memcpy(vidmem, vidmem + cols * 2, (lines - 1) * cols * 2); + for (i = (lines - 1) * cols * 2; i < lines * cols * 2; i += 2) vidmem[i] = ' '; } @@ -61,14 +60,14 @@ static void __video_putc(const char c, int *x, int *y) { if (c == '\n') { (*x) = 0; - if ( ++(*y) >= lines ) { + if (++(*y) >= lines) { scroll(); (*y)--; } } else if (c == '\b') { if ((*x) != 0) { --(*x); - vidmem [ ( (*x) + cols * (*y) ) * 2 ] = ' '; + vidmem[((*x) + cols * (*y)) * 2] = ' '; } } else if (c == '\r') { (*x) = 0; @@ -106,16 +105,15 @@ static void __video_putc(const char c, int *x, int *y) } } else if (c == '\f') { int i; - for (i=0;i<lines*cols*2;i+=2) { + for (i = 0; i < lines * cols * 2; i += 2) vidmem[i] = 0; - } (*x) = 0; (*y) = 0; } else { - vidmem [ ( (*x) + cols * (*y) ) * 2 ] = c; - if ( ++(*x) >= cols ) { + vidmem[((*x) + cols * (*y)) * 2] = c; + if (++(*x) >= cols) { (*x) = 0; - if ( ++(*y) >= lines ) { + if (++(*y) >= lines) { scroll(); (*y)--; } @@ -150,9 +148,8 @@ static void video_puts(const char *s) x = orig_x; y = orig_y; - while ( ( c = *s++ ) != '\0' ) { + while ((c = *s++) != '\0') __video_putc(c, &x, &y); - } orig_x = x; orig_y = y; @@ -189,10 +186,8 @@ int video_init(void) #if 0 printf("pos %x %d %d\n", pos, orig_x, orig_y); #endif - if (orig_y > lines) { + if (orig_y > lines) orig_x = orig_y =0; - } - memset(&vga_dev, 0, sizeof(vga_dev)); strcpy(vga_dev.name, "vga"); @@ -203,13 +198,11 @@ int video_init(void) vga_dev.tstc = NULL; /* 'tstc' function */ vga_dev.getc = NULL; /* 'getc' function */ - if (stdio_register(&vga_dev) == 0) { - return 1; - } + if (stdio_register(&vga_dev) == 0) + return 1; - if (i8042_kbd_init()) { + if (i8042_kbd_init()) return 1; - } memset(&kbd_dev, 0, sizeof(kbd_dev)); strcpy(kbd_dev.name, "kbd"); @@ -220,18 +213,17 @@ int video_init(void) kbd_dev.tstc = i8042_tstc; /* 'tstc' function */ kbd_dev.getc = i8042_getc; /* 'getc' function */ - if (stdio_register(&kbd_dev) == 0) { - return 1; - } + if (stdio_register(&kbd_dev) == 0) + return 1; + return 0; } int drv_video_init(void) { - if (video_bios_init()) { + if (video_bios_init()) return 1; - } return video_init(); } diff --git a/arch/i386/lib/video_bios.c b/arch/x86/lib/video_bios.c index c8060e60a7..6bc4335743 100644 --- a/arch/i386/lib/video_bios.c +++ b/arch/x86/lib/video_bios.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. diff --git a/arch/i386/lib/zimage.c b/arch/x86/lib/zimage.c index 0c42072691..cc4b40e64c 100644 --- a/arch/i386/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -22,7 +22,7 @@ */ /* - * Linux i386 zImage and bzImage loading + * Linux x86 zImage and bzImage loading * * based on the procdure described in * linux/Documentation/i386/boot.txt |