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-rw-r--r--arch/arm/Kconfig11
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/pxa1908-samsung-coreprimevelte.dts74
-rw-r--r--arch/arm/dts/pxa1908.dtsi106
-rw-r--r--arch/arm/mach-kirkwood/Kconfig1
-rw-r--r--arch/arm/mach-mmp/Kconfig12
-rw-r--r--arch/arm/mach-mmp/Makefile1
-rw-r--r--arch/arm/mach-mmp/board.c84
-rw-r--r--arch/arm/mach-mmp/mmu.c30
10 files changed, 322 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 314916527c9..f504d7d0760 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -842,6 +842,15 @@ config ARCH_MEDIATEK
Support for the MediaTek SoCs family developed by MediaTek Inc.
Please refer to doc/README.mediatek for more information.
+config ARCH_MMP
+ bool "Marvell MMP"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ select SAVE_PREV_BL_FDT_ADDR
+ select SAVE_PREV_BL_INITRAMFS_START_ADDR
+
config ARCH_LPC32XX
bool "NXP LPC32xx platform"
select CPU_ARM926EJS
@@ -2310,6 +2319,8 @@ source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
+source "arch/arm/mach-mmp/Kconfig"
+
source "arch/arm/mach-qemu/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index cb87a684754..7334e79965f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -69,6 +69,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MESON) += meson
+machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NEXELL) += nexell
machine-$(CONFIG_ARCH_NPCM) += npcm
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b7df72453ac..0bf3697bdbe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1226,6 +1226,8 @@ dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
corstone1000-fvp.dtb
+dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb
+
include $(srctree)/scripts/Makefile.dts
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts
new file mode 100644
index 00000000000..588e39e9265
--- /dev/null
+++ b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "pxa1908.dtsi"
+
+/ {
+ pxa,rev-id = <3928 2>;
+ model = "Samsung Galaxy Core Prime VE LTE";
+ compatible = "samsung,coreprimevelte", "marvell,pxa1908";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ /* S-Boot places the initramfs here */
+ linux,initrd-start = <0x4d70000>;
+ linux,initrd-end = <0x5000000>;
+
+ fb0: framebuffer@17177000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x17177000 0 (480 * 800 * 4)>;
+ width = <480>;
+ height = <800>;
+ stride = <(480 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x1000000 0 0x3f000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer@17000000 {
+ reg = <0 0x17000000 0 0x1800000>;
+ no-map;
+ };
+
+ gpu@9000000 {
+ reg = <0 0x9000000 0 0x1000000>;
+ };
+
+ /* Communications processor, aka modem */
+ cp@5000000 {
+ reg = <0 0x5000000 0 0x3000000>;
+ };
+
+ cm3@a000000 {
+ reg = <0 0xa000000 0 0x80000>;
+ };
+
+ seclog@8000000 {
+ reg = <0 0x8000000 0 0x100000>;
+ };
+
+ ramoops@8100000 {
+ compatible = "ramoops";
+ reg = <0 0x8100000 0 0x40000>;
+ record-size = <0x8000>;
+ console-size = <0x20000>;
+ max-reason = <5>;
+ };
+ };
+};
diff --git a/arch/arm/dts/pxa1908.dtsi b/arch/arm/dts/pxa1908.dtsi
new file mode 100644
index 00000000000..e8ec2606c25
--- /dev/null
+++ b/arch/arm/dts/pxa1908.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Marvell Armada PXA1908";
+ compatible = "marvell,pxa1908";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@d1df9000 {
+ compatible = "arm,gic-400";
+ reg = <0 0xd1df9000 0 0x1000>,
+ <0 0xd1dfa000 0 0x2000>,
+ /* The subsequent registers are guesses. */
+ <0 0xd1dfc000 0 0x2000>,
+ <0 0xd1dfe000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ apb@d4000000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4000000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4000000 0x200000>;
+
+ uart0: serial@17000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x17000 0x1000>;
+ clock-frequency = <14745600>;
+ reg-shift = <2>;
+ };
+
+ uart1: serial@18000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x18000 0x1000>;
+ clock-frequency = <14745600>;
+ reg-shift = <2>;
+ };
+
+ uart2: serial@36000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x36000 0x1000>;
+ clock-frequency = <117000000>;
+ reg-shift = <2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 031d4e5ecd3..6761a9cb393 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -38,6 +38,7 @@ config TARGET_OPENRD
bool "Marvell OpenRD Board"
select KW88F6281
select SHEEVA_88SV131
+ select KIRKWOOD_COMMON
config TARGET_DREAMPLUG
bool "DreamPlug Board"
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
new file mode 100644
index 00000000000..889f127fe82
--- /dev/null
+++ b/arch/arm/mach-mmp/Kconfig
@@ -0,0 +1,12 @@
+if ARCH_MMP
+
+config TARGET_COREPRIMEVELTE
+ bool "Support coreprimevelte"
+ select LINUX_KERNEL_IMAGE_HEADER
+
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default TEXT_BASE
+
+source "board/samsung/coreprimevelte/Kconfig"
+
+endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
new file mode 100644
index 00000000000..99beaed05c2
--- /dev/null
+++ b/arch/arm/mach-mmp/Makefile
@@ -0,0 +1 @@
+obj-y += board.o mmu.o
diff --git a/arch/arm/mach-mmp/board.c b/arch/arm/mach-mmp/board.c
new file mode 100644
index 00000000000..3384e5377a7
--- /dev/null
+++ b/arch/arm/mach-mmp/board.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024
+ * Duje Mihanović <duje.mihanovic@skole.hr>
+ */
+#include <errno.h>
+#include <init.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timer constants */
+#define APBC_COUNTER_CLK_SEL 0xd4015064
+#define COUNTER_BASE 0xd4101000
+#define COUNTER_EN BIT(0)
+#define COUNTER_HALT_ON_DEBUG BIT(1)
+
+int timer_init(void)
+{
+ u32 tmp = readl(APBC_COUNTER_CLK_SEL);
+
+ if ((tmp >> 16) != 0x319)
+ return -1;
+
+ /* Set timer frequency to 26MHz */
+ writel(tmp | 1, APBC_COUNTER_CLK_SEL);
+ writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE);
+
+ gd->arch.timer_rate_hz = 26000000;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_mem_size_base() != 0)
+ puts("fdtdec_setup_mem_size_base() has failed\n");
+
+ return 0;
+}
+
+#ifndef CONFIG_SYSRESET
+void reset_cpu(void)
+{
+}
+#endif
+
+/* Stolen from arch/arm/mach-snapdragon/board.c */
+int board_fdt_blob_setup(void **fdtp)
+{
+ struct fdt_header *fdt;
+ bool internal_valid, external_valid;
+ int ret = 0;
+
+ fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
+ external_valid = fdt && !fdt_check_header(fdt);
+ internal_valid = !fdt_check_header(*fdtp);
+
+ /*
+ * There is no point returning an error here, U-Boot can't do anything useful in this situation.
+ * Bail out while we can still print a useful error message.
+ */
+ if (!internal_valid && !external_valid)
+ panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n",
+ (phys_addr_t)fdt);
+
+ if (internal_valid) {
+ debug("Using built in FDT\n");
+ ret = -EEXIST;
+ } else {
+ debug("Using external FDT\n");
+ /* So we can use it before returning */
+ *fdtp = fdt;
+ }
+
+ return ret;
+}
diff --git a/arch/arm/mach-mmp/mmu.c b/arch/arm/mach-mmp/mmu.c
new file mode 100644
index 00000000000..ad2f1e3d994
--- /dev/null
+++ b/arch/arm/mach-mmp/mmu.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024
+ * Duje Mihanović <duje.mihanovic@skole.hr>
+ */
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region pxa1908_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 2UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 2UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = pxa1908_mem_map;
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 15:41:08 +0000