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-rw-r--r--arch/arm/dts/k3-am62a-ddr.dtsi7
-rw-r--r--arch/arm/dts/k3-j721s2-ddr.dtsi12
-rw-r--r--arch/arm/dts/k3-j784s4-ddr.dtsi24
-rw-r--r--arch/arm/mach-k3/Kconfig3
-rw-r--r--arch/arm/mach-k3/Makefile2
-rw-r--r--arch/arm/mach-k3/include/mach/k3-ddr.h15
-rw-r--r--arch/arm/mach-k3/k3-ddr.c72
7 files changed, 119 insertions, 16 deletions
diff --git a/arch/arm/dts/k3-am62a-ddr.dtsi b/arch/arm/dts/k3-am62a-ddr.dtsi
index 8629ea45b84..42e41f78505 100644
--- a/arch/arm/dts/k3-am62a-ddr.dtsi
+++ b/arch/arm/dts/k3-am62a-ddr.dtsi
@@ -4,11 +4,12 @@
*/
/ {
- memorycontroller: memory-controller@f308000 {
+ memorycontroller: memory-controller@f300000 {
compatible = "ti,am62a-ddrss";
reg = <0x00 0x0f308000 0x00 0x4000>,
- <0x00 0x43014000 0x00 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x00 0x43014000 0x00 0x100>,
+ <0x00 0x0f300000 0x00 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
diff --git a/arch/arm/dts/k3-j721s2-ddr.dtsi b/arch/arm/dts/k3-j721s2-ddr.dtsi
index 345e2b84f9e..9764085163c 100644
--- a/arch/arm/dts/k3-j721s2-ddr.dtsi
+++ b/arch/arm/dts/k3-j721s2-ddr.dtsi
@@ -5,6 +5,8 @@
&main_navss {
ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
+ <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
+ <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
<0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
@@ -24,8 +26,9 @@
memorycontroller0: memorycontroller@2990000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x02990000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x02980000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
<&k3_pds 96 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
@@ -2232,8 +2235,9 @@
memorycontroller1: memorycontroller@29b0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029b0000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x029a0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>,
<&k3_pds 97 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 139 0>, <&k3_clks 43 2>;
diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi
index 1c3242b0870..fc74c539331 100644
--- a/arch/arm/dts/k3-j784s4-ddr.dtsi
+++ b/arch/arm/dts/k3-j784s4-ddr.dtsi
@@ -9,6 +9,10 @@
<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
<0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
<0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
+ <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
+ <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
+ <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
+ <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
msmc0: msmc {
@@ -26,8 +30,9 @@
memorycontroller0: memorycontroller@2990000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x02990000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x02980000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
<&k3_pds 131 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
@@ -2234,8 +2239,9 @@
memorycontroller1: memorycontroller@29b0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029b0000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x029a0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
<&k3_pds 132 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
@@ -4442,8 +4448,9 @@
memorycontroller2: memorycontroller@29d0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029d0000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x029c0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
<&k3_pds 133 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
@@ -6650,8 +6657,9 @@
memorycontroller3: memorycontroller@29f0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029f0000 0x0 0x4000>,
- <0x0 0x0114000 0x0 0x100>;
- reg-names = "cfg", "ctrl_mmr_lp4";
+ <0x0 0x0114000 0x0 0x100>,
+ <0x0 0x29e0000 0x0 0x200>;
+ reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
<&k3_pds 139 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index f3f42b39213..a3ac490f677 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -156,6 +156,9 @@ config K3_X509_SWRV
help
SWRV for X509 certificate used for boot images
+config NR_DRAM_BANKS
+ default 2
+
if CPU_V7R
source "arch/arm/mach-k3/r5/Kconfig"
endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 8c4f6786a5b..5ce7fc62d80 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -6,7 +6,7 @@
obj-$(CONFIG_ARM64) += arm64/
obj-$(CONFIG_CPU_V7R) += r5/
obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
-obj-y += common.o security.o
+obj-y += common.o security.o k3-ddr.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h
new file mode 100644
index 00000000000..95496e1c59d
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/k3-ddr.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2024, Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef _K3_DDR_H_
+#define _K3_DDR_H_
+
+int dram_init(void);
+int dram_init_banksize(void);
+
+void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image);
+void fixup_memory_node(struct spl_image_info *spl_image);
+
+#endif /* _K3_DDR_H_ */
diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c
new file mode 100644
index 00000000000..6e3e60cdc86
--- /dev/null
+++ b/arch/arm/mach-k3/k3-ddr.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024, Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <fdt_support.h>
+#include <dm/uclass.h>
+#include <k3-ddrss.h>
+#include <spl.h>
+
+#include <asm/arch/k3-ddr.h>
+
+__weak int dram_init(void)
+{
+ return 0;
+}
+
+__weak int dram_init_banksize(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
+{
+ struct udevice *dev;
+ int ret, ctr = 1;
+
+ dram_init_banksize();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret)
+ panic("Cannnot get RAM device for ddr size fixup: %d\n", ret);
+
+ ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
+ if (ret)
+ printf("Error fixing up ddr node for ECC use! %d\n", ret);
+
+ ret = uclass_next_device_err(&dev);
+
+ while (ret && ret != -ENODEV) {
+ ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
+ if (ret)
+ printf("Error fixing up ddr node %d for ECC use! %d\n", ctr, ret);
+
+ ret = uclass_next_device_err(&dev);
+ ctr++;
+ }
+}
+
+void fixup_memory_node(struct spl_image_info *spl_image)
+{
+ u64 start[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ int bank;
+ int ret;
+
+ dram_init();
+ dram_init_banksize();
+
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start[bank] = gd->bd->bi_dram[bank].start;
+ size[bank] = gd->bd->bi_dram[bank].size;
+ }
+
+ ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
+ CONFIG_NR_DRAM_BANKS);
+
+ if (ret)
+ printf("Error fixing up memory node! %d\n", ret);
+}
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-04 15:45:16 +0000