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-rw-r--r--arch/arc/dts/axs10x_mb.dtsi34
-rw-r--r--arch/arc/dts/hsdk.dts7
-rw-r--r--arch/arc/include/asm/arcregs.h3
-rw-r--r--arch/arc/lib/start.S9
-rw-r--r--arch/arm/cpu/armv8/Kconfig11
-rw-r--r--arch/arm/cpu/armv8/Makefile4
-rw-r--r--arch/arm/cpu/armv8/exceptions.S132
-rw-r--r--arch/arm/cpu/armv8/start.S19
-rw-r--r--arch/arm/dts/stm32429i-eval.dts3
-rw-r--r--arch/arm/dts/sunxi-u-boot.dtsi2
-rw-r--r--arch/arm/dts/tegra-u-boot.dtsi6
-rw-r--r--arch/arm/mach-imx/mx7/Kconfig2
-rw-r--r--arch/arm/mach-tegra/board2.c2
-rw-r--r--arch/sandbox/include/asm/clk.h8
-rw-r--r--arch/x86/dts/u-boot.dtsi24
15 files changed, 191 insertions, 75 deletions
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index 3855a34dc20..dfc03810ca0 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -4,6 +4,10 @@
*/
/ {
+ aliases {
+ spi0 = &spi0;
+ };
+
axs10x_mb@e0000000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -56,5 +60,35 @@
reg-shift = <2>;
reg-io-width = <4>;
};
+
+ spi0: spi@0 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ clocks = <&apbclk>;
+ clock-names = "spi_clk";
+ cs-gpio = <&cs_gpio 0>;
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+
+ cs_gpio: gpio@11218 {
+ compatible = "snps,creg-gpio";
+ reg = <0x11218 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "axs-spi-cs";
+ gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <1>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
+ };
};
};
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 264512877e9..e41e4ce84bc 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -101,11 +101,16 @@
};
cs_gpio: gpio@f00014b0 {
- compatible = "snps,hsdk-creg-gpio";
+ compatible = "snps,creg-gpio";
reg = <0xf00014b0 0x4>;
gpio-controller;
#gpio-cells = <1>;
gpio-bank-name = "hsdk-spi-cs";
gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <2>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
};
};
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 56ec11f789b..9920d2e7195 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -19,6 +19,9 @@
#define ARC_AUX_IDENTITY 0x04
#define ARC_AUX_STATUS32 0x0a
+/* STATUS32 Bits Positions */
+#define STATUS_AD_BIT 19 /* Enable unaligned access */
+
/* Instruction cache related auxiliary registers */
#define ARC_AUX_IC_IVIC 0x10
#define ARC_AUX_IC_CTRL 0x11
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index e573ce7718b..84959b41bdf 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -61,6 +61,15 @@ ENTRY(_start)
1:
#endif
+#ifdef __ARC_UNALIGNED__
+ /*
+ * Enable handling of unaligned access in the CPU as by default
+ * this HW feature is disabled while GCC starting from 8.1.0
+ * unconditionally uses it for ARC HS cores.
+ */
+ flag 1 << STATUS_AD_BIT
+#endif
+
/* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %fp, %sp
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 741e15c7737..c8bebabdf6f 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -1,5 +1,16 @@
if ARM64
+config ARMV8_SPL_EXCEPTION_VECTORS
+ bool "Install crash dump exception vectors"
+ depends on SPL
+ default y
+ help
+ The default exception vector table is only used for the crash
+ dump, but still takes quite a lot of space in the image size.
+
+ Say N here if you are running out of code space in the image
+ and want to save some space at the cost of less debugging info.
+
config ARMV8_MULTIENTRY
bool "Enable multiple CPUs to enter into U-Boot"
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index d1d4ffecfd2..52c8daa0496 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -10,7 +10,11 @@ ifndef CONFIG_$(SPL_TPL_)TIMER
obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
obj-y += cache_v8.o
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o
+else
obj-y += exceptions.o
+endif
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S
index 1a78a5d1dcc..a15af72e023 100644
--- a/arch/arm/cpu/armv8/exceptions.S
+++ b/arch/arm/cpu/armv8/exceptions.S
@@ -11,7 +11,26 @@
#include <linux/linkage.h>
/*
- * Exception vectors.
+ * AArch64 exception vectors:
+ * We have four types of exceptions:
+ * - synchronous: traps, data aborts, undefined instructions, ...
+ * - IRQ: group 1 (normal) interrupts
+ * - FIQ: group 0 or secure interrupts
+ * - SError: fatal system errors
+ * There are entries for all four of those for different contexts:
+ * - from same exception level, when using the SP_EL0 stack pointer
+ * - from same exception level, when using the SP_ELx stack pointer
+ * - from lower exception level, when this is AArch64
+ * - from lower exception level, when this is AArch32
+ * Each of those 16 entries have space for 32 instructions, each entry must
+ * be 128 byte aligned, the whole table must be 2K aligned.
+ * The 32 instructions are not enough to save and restore all registers and
+ * to branch to the actual handler, so we split this up:
+ * Each entry saves the LR, branches to the save routine, then to the actual
+ * handler, then to the restore routine. The save and restore routines are
+ * each split in half and stuffed in the unused gap between the entries.
+ * Also as we do not run anything in a lower exception level, we just provide
+ * the first 8 entries for exceptions from the same EL.
*/
.align 11
.globl vectors
@@ -22,52 +41,9 @@ vectors:
bl do_bad_sync
b exception_exit
- .align 7 /* Current EL IRQ Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_irq
- b exception_exit
-
- .align 7 /* Current EL FIQ Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_fiq
- b exception_exit
-
- .align 7 /* Current EL Error Thread */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_bad_error
- b exception_exit
-
- .align 7 /* Current EL Synchronous Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_sync
- b exception_exit
-
- .align 7 /* Current EL IRQ Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_irq
- b exception_exit
-
- .align 7 /* Current EL FIQ Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_fiq
- b exception_exit
-
- .align 7 /* Current EL Error Handler */
- stp x29, x30, [sp, #-16]!
- bl _exception_entry
- bl do_error
- b exception_exit
-
/*
- * Enter Exception.
- * This will save the processor state that is ELR/X0~X30
- * to the stack frame.
+ * Save (most of) the GP registers to the stack frame.
+ * This is the first part of the shared routine called into from all entries.
*/
_exception_entry:
stp x27, x28, [sp, #-16]!
@@ -84,7 +60,19 @@ _exception_entry:
stp x5, x6, [sp, #-16]!
stp x3, x4, [sp, #-16]!
stp x1, x2, [sp, #-16]!
+ b _save_el_regs /* jump to the second part */
+ .align 7 /* Current EL IRQ Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_irq
+ b exception_exit
+
+/*
+ * Save exception specific context: ESR and ELR, for all exception levels.
+ * This is the second part of the shared routine called into from all entries.
+ */
+_save_el_regs:
/* Could be running at EL3/EL2/EL1 */
switch_el x11, 3f, 2f, 1f
3: mrs x1, esr_el3
@@ -100,16 +88,36 @@ _exception_entry:
mov x0, sp
ret
-
+ .align 7 /* Current EL FIQ Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_fiq
+ /* falling through to _exception_exit */
+/*
+ * Restore the exception return address, for all exception levels.
+ * This is the first part of the shared routine called into from all entries.
+ */
exception_exit:
ldp x2, x0, [sp],#16
switch_el x11, 3f, 2f, 1f
3: msr elr_el3, x2
- b 0f
+ b _restore_regs
2: msr elr_el2, x2
- b 0f
+ b _restore_regs
1: msr elr_el1, x2
-0:
+ b _restore_regs /* jump to the second part */
+
+ .align 7 /* Current EL Error Thread */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_bad_error
+ b exception_exit
+
+/*
+ * Restore the general purpose registers from the exception stack, then return.
+ * This is the second part of the shared routine called into from all entries.
+ */
+_restore_regs:
ldp x1, x2, [sp],#16
ldp x3, x4, [sp],#16
ldp x5, x6, [sp],#16
@@ -126,3 +134,27 @@ exception_exit:
ldp x27, x28, [sp],#16
ldp x29, x30, [sp],#16
eret
+
+ .align 7 /* Current EL (SP_ELx) Synchronous Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_sync
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) IRQ Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_irq
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) FIQ Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_fiq
+ b exception_exit
+
+ .align 7 /* Current EL (SP_ELx) Error Handler */
+ stp x29, x30, [sp, #-16]!
+ bl _exception_entry
+ bl do_error
+ b exception_exit
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index d4db4d044f6..12a78ee38b4 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -87,13 +87,22 @@ pie_fixup_done:
#ifdef CONFIG_SYS_RESET_SCTRL
bl reset_sctrl
#endif
+
+#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+.macro set_vbar, regname, reg
+ msr \regname, \reg
+.endm
+ adr x0, vectors
+#else
+.macro set_vbar, regname, reg
+.endm
+#endif
/*
* Could be EL3/EL2/EL1, Initial State:
* Little Endian, MMU Disabled, i/dCache Disabled
*/
- adr x0, vectors
switch_el x1, 3f, 2f, 1f
-3: msr vbar_el3, x0
+3: set_vbar vbar_el3, x0
mrs x0, scr_el3
orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
msr scr_el3, x0
@@ -103,11 +112,11 @@ pie_fixup_done:
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
#endif
b 0f
-2: msr vbar_el2, x0
+2: set_vbar vbar_el2, x0
mov x0, #0x33ff
msr cptr_el2, x0 /* Enable FP/SIMD */
b 0f
-1: msr vbar_el1, x0
+1: set_vbar vbar_el1, x0
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
@@ -345,6 +354,7 @@ ENDPROC(smp_kick_all_cpus)
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
+#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
@@ -354,6 +364,7 @@ ENTRY(c_runtime_cpu_setup)
b 0f
1: msr vbar_el1, x0
0:
+#endif
ret
ENDPROC(c_runtime_cpu_setup)
diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts
index c16594b7e43..f6753a4d1a1 100644
--- a/arch/arm/dts/stm32429i-eval.dts
+++ b/arch/arm/dts/stm32429i-eval.dts
@@ -223,8 +223,7 @@
&sdio {
status = "okay";
vmmc-supply = <&mmc_vcard>;
- cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
- cd-inverted;
+ cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 5adfd9bca2e..8a9f2a6417d 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -8,7 +8,7 @@
filename = "spl/sunxi-spl.bin";
};
u-boot-img {
- pos = <CONFIG_SPL_PAD_TO>;
+ offset = <CONFIG_SPL_PAD_TO>;
};
};
};
diff --git a/arch/arm/dts/tegra-u-boot.dtsi b/arch/arm/dts/tegra-u-boot.dtsi
index 4f692ee9757..fe19619919e 100644
--- a/arch/arm/dts/tegra-u-boot.dtsi
+++ b/arch/arm/dts/tegra-u-boot.dtsi
@@ -15,7 +15,7 @@
u-boot-spl {
};
u-boot {
- pos = <(U_BOOT_OFFSET)>;
+ offset = <(U_BOOT_OFFSET)>;
};
};
@@ -26,7 +26,7 @@
u-boot-spl {
};
u-boot {
- pos = <(U_BOOT_OFFSET)>;
+ offset = <(U_BOOT_OFFSET)>;
};
};
@@ -36,7 +36,7 @@
u-boot-spl {
};
u-boot-nodtb {
- pos = <(U_BOOT_OFFSET)>;
+ offset = <(U_BOOT_OFFSET)>;
};
};
};
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 1acd7f3c7cb..232f33285d4 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -43,6 +43,7 @@ config TARGET_PICO_IMX7D
select DM_THERMAL
select MX7D
select SUPPORT_SPL
+ imply CMD_DM
config TARGET_WARP7
bool "warp7"
@@ -51,7 +52,6 @@ config TARGET_WARP7
select DM_THERMAL
select MX7D
imply CMD_DM
- imply CMD_DM
config TARGET_COLIBRI_IMX7
bool "Support Colibri iMX7S/iMX7D modules"
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 5ecadf705e7..421a71b3014 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -252,7 +252,7 @@ static ulong carveout_size(void)
#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
// BASE+SIZE might not == 4GB. If so, we want the carveout to cover
// from BASE to 4GB, not BASE to BASE+SIZE.
- return (0 - CONFIG_ARMV7_SECURE_BASE);
+ return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
#else
return 0;
#endif
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index d85cbadf6ec..2b1c49f7830 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -138,5 +138,13 @@ int sandbox_clk_test_free(struct udevice *dev);
* @return: 0 if OK, or a negative error code.
*/
int sandbox_clk_test_release_bulk(struct udevice *dev);
+/**
+ * sandbox_clk_test_valid - Ask the sandbox clock test device to check its
+ * clocks are valid.
+ *
+ * @dev: The sandbox clock test (client) devivce.
+ * @return: 0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_valid(struct udevice *dev);
#endif
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1253fa51c22..1050236330a 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -11,7 +11,7 @@
binman {
filename = "u-boot.rom";
end-at-4gb;
- sort-by-pos;
+ sort-by-offset;
pad-byte = <0xff>;
size = <CONFIG_ROM_SIZE>;
#ifdef CONFIG_HAVE_INTEL_ME
@@ -24,18 +24,18 @@
#endif
#ifdef CONFIG_SPL
u-boot-spl-with-ucode-ptr {
- pos = <CONFIG_SPL_TEXT_BASE>;
+ offset = <CONFIG_SPL_TEXT_BASE>;
};
u-boot-dtb-with-ucode2 {
type = "u-boot-dtb-with-ucode";
};
u-boot {
- pos = <0xfff00000>;
+ offset = <0xfff00000>;
};
#else
u-boot-with-ucode-ptr {
- pos = <CONFIG_SYS_TEXT_BASE>;
+ offset = <CONFIG_SYS_TEXT_BASE>;
};
#endif
u-boot-dtb-with-ucode {
@@ -45,45 +45,45 @@
};
#ifdef CONFIG_HAVE_MRC
intel-mrc {
- pos = <CONFIG_X86_MRC_ADDR>;
+ offset = <CONFIG_X86_MRC_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_FSP
intel-fsp {
filename = CONFIG_FSP_FILE;
- pos = <CONFIG_FSP_ADDR>;
+ offset = <CONFIG_FSP_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_CMC
intel-cmc {
filename = CONFIG_CMC_FILE;
- pos = <CONFIG_CMC_ADDR>;
+ offset = <CONFIG_CMC_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_VGA_BIOS
intel-vga {
filename = CONFIG_VGA_BIOS_FILE;
- pos = <CONFIG_VGA_BIOS_ADDR>;
+ offset = <CONFIG_VGA_BIOS_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_VBT
intel-vbt {
filename = CONFIG_VBT_FILE;
- pos = <CONFIG_VBT_ADDR>;
+ offset = <CONFIG_VBT_ADDR>;
};
#endif
#ifdef CONFIG_HAVE_REFCODE
intel-refcode {
- pos = <CONFIG_X86_REFCODE_ADDR>;
+ offset = <CONFIG_X86_REFCODE_ADDR>;
};
#endif
#ifdef CONFIG_SPL
x86-start16-spl {
- pos = <CONFIG_SYS_X86_START16>;
+ offset = <CONFIG_SYS_X86_START16>;
};
#else
x86-start16 {
- pos = <CONFIG_SYS_X86_START16>;
+ offset = <CONFIG_SYS_X86_START16>;
};
#endif
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-25 18:00:02 +0000