diff options
Diffstat (limited to 'arch')
446 files changed, 5405 insertions, 8155 deletions
diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index 532a8131c59..fe6ad7b849a 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -10,12 +10,5 @@ dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/arm/Makefile b/arch/arm/Makefile index dbeedbe544b..cb87a684754 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) CONFIG_CPU_V7A= CONFIG_CPU_ARM720T=y endif @@ -24,7 +24,7 @@ endif # On Tegra systems we must build SPL for the armv4 core on the device # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy) arch-y += -D__LINUX_ARM_ARCH__=4 else arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) @@ -106,7 +106,7 @@ libs-y += $(machdirs) head-y := arch/arm/cpu/$(CPU)/start.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs") head-y := arch/arm/cpu/arm926ejs/mxs/start.o endif diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 5530d02b66c..e0045e22271 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -40,7 +40,7 @@ PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm endif # Choose between ARM/Thumb instruction sets -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always) PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \ $(call cc-option, -mthumb -mthumb-interwork,\ @@ -53,7 +53,7 @@ PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \ endif # Only test once -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) archprepare: checkthumb checkgcc6 checkthumb: @@ -99,7 +99,7 @@ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI) ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) # This file is parsed many times, so the string may get added multiple # times. Also, the prefix needs to be different based on whether -# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry +# CONFIG_XPL_BUILD is defined or not. 'filter-out' the existing entry # before adding the correct one. PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \ $(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS)) @@ -116,7 +116,7 @@ LDFLAGS_u-boot += -pie # # http://sourceware.org/bugzilla/show_bug.cgi?id=12532 # -ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) +ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y) ifeq ($(GAS_BUG_12532),) export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \ then echo y; else echo n; fi) @@ -126,7 +126,7 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls endif endif -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) # Check that only R_ARM_RELATIVE relocations are generated. INPUTS-y += checkarmreloc # The movt / movw can hardcode 16 bit parts of the addresses in the @@ -160,7 +160,7 @@ endif ifdef CONFIG_MACH_IMX ifneq ($(CONFIG_IMX_CONFIG),"") ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-y += SPL endif else diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile index 5dfa01ae8d0..38a3e4d95e2 100644 --- a/arch/arm/cpu/arm11/Makefile +++ b/arch/arm/cpu/arm11/Makefile @@ -5,6 +5,6 @@ obj-y = cpu.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_EFI_LOADER) += sctlr.o endif diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 78a9cc173a3..d3ab5928eee 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -65,7 +65,7 @@ cpu_init_crit: * When booting from NAND - it has definitely been a reset, so, no need * to flush caches and disable the MMU */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * flush v4 I/D caches */ diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 5ac3740621c..06456fe5a81 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -9,6 +9,6 @@ obj-y += cpu.o # some files can only build in ARM mode -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD CFLAGS_cpu.o := -marm endif diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 8cfe3f0fbbc..750cb94dc6e 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -6,7 +6,7 @@ extra-y = start.o obj-y = cpu.o cache.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_SPL_NO_CPU_SUPPORT extra-y := endif @@ -17,7 +17,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 1638ef8fd8d..f633e54ba62 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -3,11 +3,11 @@ # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -extra-$(CONFIG_SPL_BUILD) := start.o +extra-$(CONFIG_XPL_BUILD) := start.o obj-y = clock.o mxs.o iomux.o timer.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif diff --git a/arch/arm/cpu/arm926ejs/sunxi/config.mk b/arch/arm/cpu/arm926ejs/sunxi/config.mk index 76ffec9df6a..50899d20316 100644 --- a/arch/arm/cpu/arm926ejs/sunxi/config.mk +++ b/arch/arm/cpu/arm926ejs/sunxi/config.mk @@ -1,6 +1,6 @@ # Build a combined spl + u-boot image ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ALL-y += u-boot-sunxi-with-spl.bin endif endif diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 99cf9eb515f..6461f5f5bde 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,12 +12,12 @@ obj-y += syslib.o obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_EFI_LOADER) += sctlr.o obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o endif -ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y) +ifneq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index aa981faef00..8082f369ed6 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -32,7 +32,7 @@ int cleanup_before_linux_select(int flags) * * we turn off caches etc ... */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD disable_interrupts(); #endif diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 3c8c07fe016..a6c844b7e3d 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -26,7 +26,7 @@ WEAK(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr sp, =CONFIG_SPL_STACK #else ldr sp, =SYS_INIT_SP_ADDR @@ -39,7 +39,7 @@ WEAK(lowlevel_init) * Set up global data for boards that still need it. This will be * removed soon. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD ldr r9, =gdata #else sub sp, sp, #GD_SIZE diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index 0985420fe5c..4660ff0057e 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -8,7 +8,7 @@ ifdef CONFIG_ARCH_NEXELL obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o else obj-y += cpu_info.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += timer.o obj-y += sromc.o endif diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7730a16e512..b63481b43ca 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -279,7 +279,7 @@ ENTRY(cpu_init_cp15) orr r2, r4, r2 @ r2 has combined CPU variant + revision /* Early stack for ERRATA that needs into call C code */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(SYS_INIT_SP_ADDR) diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 3e975b366c4..0624e93efde 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,10 +12,10 @@ obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o obj-$(CONFIG_MACH_SUN6I) += sram.o obj-$(CONFIG_MACH_SUN8I) += sram.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 4f4368ff8c7..2e71ff2dc97 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -6,14 +6,14 @@ extra-y := start.o obj-y += cpu.o -ifndef CONFIG_$(SPL_TPL_)TIMER +ifndef CONFIG_$(PHASE_)TIMER obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o endif -ifndef CONFIG_$(SPL_)SYS_DCACHE_OFF +ifndef CONFIG_$(XPL_)SYS_DCACHE_OFF obj-y += cache_v8.o obj-y += cache.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o else obj-y += exceptions.o @@ -27,15 +27,15 @@ endif obj-y += cpu-dt.o obj-$(CONFIG_ARM_SMCCC) += smccc-call.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o obj-$(CONFIG_ACPI_PARKING_PROTOCOL) += acpi_park_v8.o else obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o endif -obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o +obj-$(CONFIG_$(XPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o endif diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 631d9efa5e1..e6be6359c5d 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -1016,7 +1016,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) * running however really wants to have dcache and the MMU active. Check that * everything is sane and give the developer a hint if it isn't. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache. #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index eefdf12369c..e2033dc5aff 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -5,7 +5,7 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_MP) += mp.o spintable.o obj-$(CONFIG_OF_LIBFDT) += fdt.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2dbfdd08a0..d2d3e346a36 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -10,6 +10,7 @@ #include <env.h> #include <init.h> #include <hang.h> +#include <lmb.h> #include <log.h> #include <net.h> #include <vsprintf.h> @@ -122,7 +123,7 @@ static struct mm_region early_map[] = { { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -181,7 +182,7 @@ static struct mm_region early_map[] = { { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)) PTE_BLOCK_MEMTYPE(MT_NORMAL) | #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | @@ -1055,7 +1056,7 @@ int cpu_eth_init(struct bd_info *bis) { int error = 0; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) error = fsl_mc_ldpaa_init(bis); #endif return error; @@ -1285,7 +1286,7 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) { phys_size_t ram_top = ram_size; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) ram_top = mc_get_dram_block_size(); if (ram_top > ram_size) return ram_size + ram_top; @@ -1381,7 +1382,7 @@ static int tfa_dram_init_banksize(void) if (i > 0) ret = 0; -#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1467,7 +1468,7 @@ int dram_init_banksize(void) } #endif /* CFG_SYS_MEM_RESERVE_SECURE */ -#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bd->bi_dram[2].size >= @@ -1525,8 +1526,8 @@ int dram_init_banksize(void) return 0; } -#if CONFIG_IS_ENABLED(EFI_LOADER) -void efi_add_known_memory(void) +#if CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP) +void lmb_arch_add_memory(void) { int i; phys_addr_t ram_start; @@ -1548,8 +1549,7 @@ void efi_add_known_memory(void) gd->arch.resv_ram < ram_start + ram_size) ram_size = gd->arch.resv_ram - ram_start; #endif - efi_add_memory_map(ram_start, ram_size, - EFI_CONVENTIONAL_MEMORY); + lmb_add(ram_start, ram_size); } } #endif @@ -1624,7 +1624,7 @@ __weak int dram_init(void) #ifdef CONFIG_SYS_FSL_DDR fsl_initdram(); #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ - defined(CONFIG_SPL_BUILD) + defined(CONFIG_XPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9a24d4b3031..1f03f5e2ecd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -93,7 +93,7 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) rcw_tmp = in_be32(&gur->rcwsr[7]); switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { case 2: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index b768790437f..b5213c780fb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -25,7 +25,7 @@ static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) int xfi_dpmac[XFI14 + 1]; int sgmii_dpmac[SGMII18 + 1]; @@ -162,7 +162,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, debug("Unknown SerDes lane protocol %d\n", lane_prtcl); else { serdes_prtcl_map[lane_prtcl] = 1; -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], @@ -553,7 +553,7 @@ int setup_serdes_volt(u32 svdd) void fsl_serdes_init(void) { -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD) int i , j; #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index 04ffefafbf7..aa0af077d2f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -23,7 +23,7 @@ static void set_icid(struct icid_id_table *tbl, int size) out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); } -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) static void set_fman_icids(struct fman_icid_id_table *tbl, int size) { int i; @@ -41,12 +41,12 @@ void set_icids(void) /* setup general icid offsets */ set_icid(icid_tbl, icid_tbl_sz); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids) { int i, ret; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 4358c6ed11c..75c204e8309 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -183,7 +183,7 @@ ENTRY(lowlevel_init) #endif /* Initialize GIC Secure Bank Status */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f bl get_gic_offset @@ -306,7 +306,7 @@ ENTRY(lowlevel_init) #endif #if !defined(CONFIG_TFABOOT) && \ - (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)) + (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD)) bl fsl_ocram_init #endif @@ -314,7 +314,7 @@ ENTRY(lowlevel_init) ret ENDPROC(lowlevel_init) -#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD) ENTRY(fsl_ocram_init) mov x28, lr /* Save LR */ bl fsl_clear_ocram diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index ec80e42055d..48b95627bae 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -60,7 +60,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index a73dd316f8d..ab175b60c6c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index a739ff2da58..1f1e3d4a97b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -41,7 +41,7 @@ u32 spl_boot_device(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_board_init(void) { @@ -136,4 +136,4 @@ int spl_start_uboot(void) return 1; } #endif /* CONFIG_SPL_OS_BOOT */ -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 544a4a53645..d3a8a7c4787 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -58,7 +58,7 @@ reset: .globl save_boot_params_ret save_boot_params_ret: -#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD) +#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_XPL_BUILD) /* Verify that we're 4K aligned. */ adr x0, _start ands x0, x0, #0xfff @@ -104,7 +104,7 @@ pie_skip_reloc: pie_fixup_done: #endif -#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD) .macro set_vbar, regname, reg msr \regname, \reg .endm @@ -174,7 +174,7 @@ pie_fixup_done: /* Processor specific initialization */ bl lowlevel_init -#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_XPL_BUILD) branch_if_master x0, master_cpu b spin_table_secondary_jump /* never return */ @@ -366,7 +366,7 @@ ENDPROC(smp_kick_all_cpus) /*-----------------------------------------------------------------------*/ ENTRY(c_runtime_cpu_setup) -#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD) /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d46f0bda1a8..03ed3cbeb79 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -327,6 +327,7 @@ zynqmp-sc-vpk120-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk120-revB.dtbo zynqmp-sc-vpk180-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revA.dtbo zynqmp-sc-vpk180-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revB.dtbo zynqmp-sc-vn-p-b2197-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vn-p-b2197-00-revA.dtbo +zynqmp-sc-vm-p-b1369-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vm-p-m1369-00-revA.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revB.dtb @@ -335,6 +336,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk120-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vn-p-b2197-00-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vm-p-b1369-00-revA.dtb zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo @@ -721,13 +723,6 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-pine-h64-model-b.dtb \ sun50i-h6-tanix-tx6.dtb \ sun50i-h6-tanix-tx6-mini.dtb -dtb-$(CONFIG_MACH_SUN50I_H616) += \ - sun50i-h313-tanix-tx1.dtb \ - sun50i-h616-orangepi-zero2.dtb \ - sun50i-h618-orangepi-zero2w.dtb \ - sun50i-h618-orangepi-zero3.dtb \ - sun50i-h618-transpeed-8k618-t.dtb \ - sun50i-h616-x96-mate.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-amarula-relic.dtb \ sun50i-a64-bananapi-m64.dtb \ @@ -967,10 +962,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ - imx8mp-debix-model-a.dtb \ - imx8mp-dhcom-pdk2.dtb \ - imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-drc02.dtb \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ + imx8mp-dhcom-picoitx.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ imx8mq-pico-pi.dtb \ @@ -1148,7 +1142,6 @@ dtb-$(CONFIG_ASPEED_AST2600) += \ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb dtb-$(CONFIG_STM32MP13X) += \ - stm32mp135f-dhcor-dhsbc.dtb \ stm32mp135f-dk.dtb dtb-$(CONFIG_STM32MP15X) += \ @@ -1164,13 +1157,7 @@ dtb-$(CONFIG_STM32MP15X) += \ stm32mp157c-ed1-scmi.dtb \ stm32mp157c-ev1.dtb \ stm32mp157c-ev1-scmi.dtb \ - stm32mp157c-odyssey.dtb \ - stm32mp15xx-dhcom-drc02.dtb \ - stm32mp15xx-dhcom-pdk2.dtb \ - stm32mp15xx-dhcom-picoitx.dtb \ - stm32mp15xx-dhcor-avenger96.dtb \ - stm32mp15xx-dhcor-drc-compact.dtb \ - stm32mp15xx-dhcor-testbench.dtb + stm32mp157c-odyssey.dtb dtb-$(CONFIG_STM32MP25X) += \ stm32mp257f-ev1.dtb @@ -1312,16 +1299,8 @@ dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += -a 0x8 DTC_FLAGS_imx8mp-dhcom-som-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb *.dtbo *_HS diff --git a/arch/arm/dts/bcm6846.dtsi b/arch/arm/dts/bcm6846.dtsi deleted file mode 100644 index 8aa47a2583b..00000000000 --- a/arch/arm/dts/bcm6846.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "brcm,bcm6846", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&CA7_0>, <&CA7_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x1b>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm96846.dts b/arch/arm/dts/bcm96846.dts deleted file mode 100644 index c70ebccabc1..00000000000 --- a/arch/arm/dts/bcm96846.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6846.dtsi" - -/ { - model = "Broadcom BCM96846 Reference Board"; - compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 6e5379e53c5..38925d53065 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -7,18 +7,48 @@ &{/imx8qm-pm} { + bootph-some-ram; bootph-pre-ram; }; &mu { + bootph-some-ram; bootph-pre-ram; }; &clk { + bootph-some-ram; bootph-pre-ram; }; &iomuxc { + bootph-some-ram; + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&{/mu@5d1c0000/iomuxc/imx8qm-mek} { + bootph-some-ram; + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_lpuart0 { + bootph-some-ram; + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { bootph-pre-ram; }; @@ -75,10 +105,12 @@ }; &pd_dma { + bootph-some-ram; bootph-pre-ram; }; &pd_dma_lpuart0 { + bootph-some-ram; bootph-pre-ram; }; @@ -131,6 +163,7 @@ }; &lpuart0 { + bootph-some-ram; bootph-pre-ram; }; diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts index 63908ba6bf1..6cf7ce3d5e0 100644 --- a/arch/arm/dts/fsl-imx8qm-mek.dts +++ b/arch/arm/dts/fsl-imx8qm-mek.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "fsl-imx8qm.dtsi" -#include "fsl-imx8qm-mek-u-boot.dtsi" / { model = "Freescale i.MX8QM MEK"; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 591eb66604b..e670214b5fc 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -6,19 +6,32 @@ #include "imx8qxp-u-boot.dtsi" &{/imx8qx-pm} { - + bootph-some-ram; bootph-pre-ram; }; &mu { + bootph-some-ram; bootph-pre-ram; }; &clk { + bootph-some-ram; bootph-pre-ram; }; &iomuxc { + bootph-some-ram; + bootph-pre-ram; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-mek} { + bootph-some-ram; + bootph-pre-ram; +}; + +&pinctrl_lpuart0 { + bootph-some-ram; bootph-pre-ram; }; @@ -75,10 +88,12 @@ }; &pd_dma { + bootph-some-ram; bootph-pre-ram; }; &pd_dma_lpuart0 { + bootph-some-ram; bootph-pre-ram; }; @@ -131,6 +146,7 @@ }; &lpuart0 { + bootph-some-ram; bootph-pre-ram; }; diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts index 6a987f0dbb3..983b918dc7d 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek.dts +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-mek-u-boot.dtsi" / { model = "Freescale i.MX8QXP MEK"; diff --git a/arch/arm/dts/imx8mm-cl-iot-gate.dts b/arch/arm/dts/imx8mm-cl-iot-gate.dts index 425701204a0..aa6ca070bff 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate.dts +++ b/arch/arm/dts/imx8mm-cl-iot-gate.dts @@ -350,6 +350,7 @@ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; bus-width = <8>; non-removable; + no-mmc-hs400; status = "okay"; }; diff --git a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi index 33bd89a8434..d5bd9f591e5 100644 --- a/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-debix-model-a-u-boot.dtsi @@ -20,6 +20,14 @@ }; }; +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + bootph-pre-ram; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-pre-ram; +}; + &crypto { bootph-pre-ram; }; @@ -88,14 +96,6 @@ bootph-pre-ram; }; -&pmic { - bootph-pre-ram; - - regulators { - bootph-pre-ram; - }; -}; - ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; diff --git a/arch/arm/dts/imx8mp-debix-model-a.dts b/arch/arm/dts/imx8mp-debix-model-a.dts deleted file mode 100644 index 58dae612b4b..00000000000 --- a/arch/arm/dts/imx8mp-debix-model-a.dts +++ /dev/null @@ -1,507 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - * Copyright 2022 Ideas on Board Oy - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/usb/pd.h> - -#include "imx8mp.dtsi" - -/ { - model = "Polyhex Debix Model A i.MX8MPlus board"; - compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_RED>; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-connection-type = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { /* RTL8211E */ - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - reset-assert-us = <20>; - reset-deassert-us = <200000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4{ - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc_int>; - }; -}; - -&i2c6 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { - /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -/* SD Card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; -}; - -/* eMMC */ -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f - MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f - MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_i2c6: i2c6grp { - fsl,pins = < - MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 - MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 - >; - }; - - pinctrl_rtc_int: rtcintgrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 - >; - }; -}; - diff --git a/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi new file mode 100644 index 00000000000..8a23b117d9a --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-drc02-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + */ + +#include "imx8mp-dhcom-u-boot.dtsi" diff --git a/arch/arm/dts/imx8mp-dhcom-drc02.dts b/arch/arm/dts/imx8mp-dhcom-drc02.dts new file mode 100644 index 00000000000..b3ab6e94508 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-drc02.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + * + * DHCOM iMX8MP variant: + * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2 + * DHCOM PCB number: 660-100 or newer + * DRC02 PCB number: 568-100 or newer + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx8mp-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM on DRC02"; + compatible = "dh,imx8mp-dhcom-drc02", "dh,imx8mp-dhcom-som", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; +}; + +&eqos { /* First ethernet */ + pinctrl-0 = <&pinctrl_eqos_rmii>; + phy-handle = <ðphy0f>; + phy-mode = "rmii"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>; +}; + +ðphy0g { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; + +ðphy0f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&fec { /* Second ethernet */ + pinctrl-0 = <&pinctrl_fec_rmii>; + phy-handle = <ðphy1f>; + phy-mode = "rmii"; + status = "okay"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>, <0>; +}; + +ðphy1f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "DRC02-In1", "", "", "", "", "DHCOM-I", "DRC02-HW2", "DRC02-HW0", + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX8 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <13 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "DHCOM-O", "DHCOM-N", "", "SOM-HW1", "", "", "", "", + "", "", "", "", "DRC02-In2", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "SOM-HW0", "", + "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", + "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SOM-HW1", "", "", "", "", + "", "", "", "DRC02-Out2", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "DHCOM-C", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DHCOM-E", "DRC02-Out1", + "", "", "", "", "", "", "", ""; +}; + +&i2c3 { + /* Resistive touch controller not populated on this one SoM variant. */ + touchscreen@49 { + status = "disabled"; + }; +}; + +&pcie_phy { + status = "disabled"; +}; + +&pcie { + status = "disabled"; +}; + +/* Console UART */ +&pinctrl_uart1 { + fsl,pins = < + /* No pull-ups on DRC02, enable in-SoC pull-ups */ + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x149 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x149 + >; +}; + +&pinctrl_uart3 { + fsl,pins = < + /* No pull-ups on DRC02, enable in-SoC pull-ups */ + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x149 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x149 + >; +}; + +&uart1 { + /* + * Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to + * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs + * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS. + */ + /delete-property/ uart-has-rtscts; + cts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */ + pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; + pinctrl-names = "default"; + rts-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ +}; + +&uart3 { + /* + * On DRC02 this UART is used as RS485 interface and RS485_TX_En is + * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property + * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via + * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 + * node above. + */ + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + pinctrl-0 = <&pinctrl_uart3 &pinctrl_dhcom_p &pinctrl_dhcom_q>; + pinctrl-names = "default"; + rts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&uart2 { + bluetooth { + status = "disabled"; + }; +}; + +/* USB_OTG port is not routed out on DRC02. */ +&usb3_0 { + status = "disabled"; +}; + +&usb_dwc3_0 { + status = "disabled"; +}; + +/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */ +&usb3_1 { + fsl,disable-port-power-control; + fsl,permanently-attached; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&usdhc1 { + status = "disabled"; +}; + +&iomuxc { + /* + * GPIO I is connected to UART1_RTS + * GPIO M is connected to UART1_CTS + * GPIO P is connected to RS485_TX_En + * GPIO Q is connected to RS485_RX_En + */ + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j + &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_n + &pinctrl_dhcom_o &pinctrl_dhcom_r &pinctrl_dhcom_s + &pinctrl_dhcom_int>; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2.dts b/arch/arm/dts/imx8mp-dhcom-pdk2.dts deleted file mode 100644 index 8f4eff37c40..00000000000 --- a/arch/arm/dts/imx8mp-dhcom-pdk2.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2022 Marek Vasut <marex@denx.de> - * - * DHCOM iMX8MP variant: - * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2 - * DHCOM PCB number: 660-100 or newer - * PDK2 PCB number: 516-400 or newer - */ - -/dts-v1/; - -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mp-dhcom-som.dtsi" - -/ { - model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)"; - compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som", - "fsl,imx8mp"; - - chosen { - stdout-path = &uart1; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-0 { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */ - label = "TA1-GPIO-A"; - linux,code = <KEY_A>; - pinctrl-0 = <&pinctrl_dhcom_a>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-1 { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */ - label = "TA2-GPIO-B"; - linux,code = <KEY_B>; - pinctrl-0 = <&pinctrl_dhcom_b>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-2 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ - label = "TA3-GPIO-C"; - linux,code = <KEY_C>; - pinctrl-0 = <&pinctrl_dhcom_c>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-3 { - gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */ - label = "TA4-GPIO-D"; - linux,code = <KEY_D>; - pinctrl-0 = <&pinctrl_dhcom_d>; - pinctrl-names = "default"; - wakeup-source; - }; - }; - - led { - compatible = "gpio-leds"; - - led-0 { - color = <LED_COLOR_ID_GREEN>; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */ - pinctrl-0 = <&pinctrl_dhcom_e>; - pinctrl-names = "default"; - }; - - led-1 { - color = <LED_COLOR_ID_GREEN>; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */ - pinctrl-0 = <&pinctrl_dhcom_f>; - pinctrl-names = "default"; - }; - - led-2 { - color = <LED_COLOR_ID_GREEN>; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */ - pinctrl-0 = <&pinctrl_dhcom_h>; - pinctrl-names = "default"; - }; - - led-3 { - color = <LED_COLOR_ID_GREEN>; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ - pinctrl-0 = <&pinctrl_dhcom_i>; - pinctrl-names = "default"; - }; - }; -}; - -&fec { /* Second ethernet */ - pinctrl-0 = <&pinctrl_fec_rgmii>; - phy-handle = <ðphypdk>; - phy-mode = "rgmii"; - - mdio { - ethphypdk: ethernet-phy@7 { /* KSZ 9021 */ - compatible = "ethernet-phy-ieee802.3-c22"; - pinctrl-0 = <&pinctrl_ethphy1>; - pinctrl-names = "default"; - interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - max-speed = <100>; - reg = <7>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - rxdv-skew-ps = <0>; - txc-skew-ps = <3000>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - txen-skew-ps = <0>; - }; - }; -}; - -&flexcan1 { - status = "okay"; -}; - -&usb3_1 { - fsl,over-current-active-low; -}; - -&iomuxc { - /* - * GPIO_A,B,C,D are connected to buttons. - * GPIO_E,F,H,I are connected to LEDs. - * GPIO_M is connected to CLKOUT2. - */ - pinctrl-0 = <&pinctrl_hog_base - &pinctrl_dhcom_g &pinctrl_dhcom_j - &pinctrl_dhcom_k &pinctrl_dhcom_l - &pinctrl_dhcom_int>; -}; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3.dts b/arch/arm/dts/imx8mp-dhcom-pdk3.dts deleted file mode 100644 index 867d238f2b5..00000000000 --- a/arch/arm/dts/imx8mp-dhcom-pdk3.dts +++ /dev/null @@ -1,317 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Marek Vasut <marex@denx.de> - * - * DHCOM iMX8MP variant: - * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2 - * DHCOM PCB number: 660-100 or newer - * PDK3 PCB number: 669-100 or newer - */ - -/dts-v1/; - -#include <dt-bindings/leds/common.h> -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mp-dhcom-som.dtsi" - -/ { - model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)"; - compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som", - "fsl,imx8mp"; - - chosen { - stdout-path = &uart1; - }; - - clk_ext_audio_codec: clock-codec { - #clock-cells = <0>; - clock-frequency = <24000000>; - compatible = "fixed-clock"; - }; - - clk_xtal25: clk-xtal25 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_c_0_hs_ep: endpoint { - remote-endpoint = <&dwc3_0_hs_ep>; - }; - }; - - port@1 { - reg = <1>; - - usb_c_0_ss_ep: endpoint { - remote-endpoint = <&ptn5150_in_ep>; - }; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-0 { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */ - label = "TA1-GPIO-A"; - linux,code = <KEY_A>; - pinctrl-0 = <&pinctrl_dhcom_a>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-1 { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */ - label = "TA2-GPIO-B"; - linux,code = <KEY_B>; - pinctrl-0 = <&pinctrl_dhcom_b>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-2 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ - label = "TA3-GPIO-C"; - linux,code = <KEY_C>; - pinctrl-0 = <&pinctrl_dhcom_c>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-3 { - gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; /* GPIO E */ - label = "TA4-GPIO-E"; - linux,code = <KEY_E>; - pinctrl-0 = <&pinctrl_dhcom_e>; - pinctrl-names = "default"; - wakeup-source; - }; - }; - - led { - compatible = "gpio-leds"; - - led-0 { - color = <LED_COLOR_ID_GREEN>; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <0>; - gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; /* GPIO D */ - pinctrl-0 = <&pinctrl_dhcom_d>; - pinctrl-names = "default"; - }; - - led-1 { - color = <LED_COLOR_ID_GREEN>; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */ - pinctrl-0 = <&pinctrl_dhcom_f>; - pinctrl-names = "default"; - }; - - led-2 { - color = <LED_COLOR_ID_GREEN>; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */ - pinctrl-0 = <&pinctrl_dhcom_g>; - pinctrl-names = "default"; - }; - - led-3 { - color = <LED_COLOR_ID_GREEN>; - default-state = "off"; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ - pinctrl-0 = <&pinctrl_dhcom_i>; - pinctrl-names = "default"; - }; - }; - - reg_avdd: regulator-avdd { /* AUDIO_VDD */ - compatible = "regulator-fixed"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "AUDIO_VDD"; - }; -}; - -&i2c5 { - i2cmux@70 { - compatible = "nxp,pca9540"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2cmuxed0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - typec@3d { - compatible = "nxp,ptn5150"; - reg = <0x3d>; - interrupt-parent = <&gpio4>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ptn5150>; - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ptn5150_in_ep: endpoint { - remote-endpoint = <&usb_c_0_ss_ep>; - }; - }; - - port@1 { - reg = <1>; - - ptn5150_out_ep: endpoint { - remote-endpoint = <&dwc3_0_ss_ep>; - }; - }; - }; - }; - - power-sensor@40 { - compatible = "ti,ina238"; - reg = <0x40>; - shunt-resistor = <20000>; /* 0.02 R */ - ti,shunt-gain = <1>; /* Drop cca. 40mV */ - }; - - eeprom_board: eeprom@54 { - compatible = "atmel,24c04"; - pagesize = <16>; - reg = <0x54>; - }; - - pcieclk: clk@6b { - compatible = "skyworks,si52144"; - reg = <0x6b>; - clocks = <&clk_xtal25>; - #clock-cells = <1>; - }; - }; - - i2cmuxed1: i2c@1 { /* HDMI DDC I2C */ - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&fec { /* Second ethernet */ - pinctrl-0 = <&pinctrl_fec_rgmii>; - phy-handle = <ðphypdk>; - phy-mode = "rgmii-id"; - - mdio { - ethphypdk: ethernet-phy@7 { /* Micrel KSZ9131RNXI */ - compatible = "ethernet-phy-id0022.1642", - "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&pinctrl_ethphy1>; - pinctrl-names = "default"; - reg = <7>; - reset-assert-us = <1000>; - /* RESET_N signal rise time ~100ms */ - reset-deassert-us = <120000>; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; -}; - -&flexcan1 { - status = "okay"; -}; - -&pcie_phy { - clocks = <&pcieclk 1>; - clock-names = "ref"; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - status = "okay"; -}; - -&pcie { - fsl,max-link-speed = <3>; - reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usb_dwc3_0 { - usb-role-switch; - - port { - #address-cells = <1>; - #size-cells = <0>; - - dwc3_0_hs_ep: endpoint@0 { - reg = <0>; - remote-endpoint = <&usb_c_0_hs_ep>; - }; - - dwc3_0_ss_ep: endpoint@1 { - reg = <1>; - remote-endpoint = <&ptn5150_out_ep>; - }; - }; -}; - -&usb3_1 { - fsl,disable-port-power-control; - fsl,permanently-attached; -}; - -&usb_dwc3_1 { - /* This port has USB5734 Hub connected to it, PWR/OC pins are unused */ - /delete-property/ pinctrl-names; - /delete-property/ pinctrl-0; -}; - -&iomuxc { - /* - * GPIO_A,B,C,E are connected to buttons. - * GPIO_D,F,G,I are connected to LEDs. - * GPIO_H is connected to USB Hub RESET_N. - * GPIO_M is connected to CLKOUT2. - */ - pinctrl-0 = <&pinctrl_hog_base - &pinctrl_dhcom_h &pinctrl_dhcom_j &pinctrl_dhcom_k - &pinctrl_dhcom_l - &pinctrl_dhcom_int>; - - pinctrl_ptn5150: ptn5150grp { - fsl,pins = < - MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi new file mode 100644 index 00000000000..4e95cd0e483 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-picoitx-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023-2024 Marek Vasut <marex@denx.de> + */ + +#include "imx8mp-dhcom-u-boot.dtsi" diff --git a/arch/arm/dts/imx8mp-dhcom-picoitx.dts b/arch/arm/dts/imx8mp-dhcom-picoitx.dts new file mode 100644 index 00000000000..285aaa5b6c0 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-picoitx.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023-2024 Marek Vasut <marex@denx.de> + * + * DHCOM iMX8MP variant: + * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E-SD-RTC-T-RGB-I-01D2 + * DHCOM PCB number: 660-200 or newer + * PicoITX PCB number: 487-600 or newer + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "imx8mp-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM PicoITX"; + compatible = "dh,imx8mp-dhcom-picoitx", "dh,imx8mp-dhcom-som", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_YELLOW>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; +}; + +&eqos { /* First ethernet */ + pinctrl-0 = <&pinctrl_eqos_rmii>; + phy-handle = <ðphy0f>; + phy-mode = "rmii"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>; +}; + +ðphy0g { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; + +ðphy0f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&fec { + status = "disabled"; +}; + +&flexcan1 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "DHCOM-G", "", "", "", + "", "DHCOM-I", "PicoITX-HW0", "PicoITX-HW2", + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "PicoITX-HW1", "", "", "", "", + "", "", "", "", "DHCOM-INT", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "SOM-HW1", "", "", "", "", + "", "", "", "PicoITX-Out2", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "PicoITX-In2", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", + "", "", "PicoITX-In1", "PicoITX-Out1", + "", "", "", "", "", "", "", ""; +}; + +/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */ +&pcie_phy { + status = "disabled"; +}; + +&pcie { + status = "disabled"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&uart2 { + bluetooth { + status = "disabled"; + }; +}; + +/* USB_OTG port is not routed out on PicoITX. */ +&usb3_0 { + status = "disabled"; +}; + +&usb_dwc3_0 { + status = "disabled"; +}; + +&usb3_1 { + fsl,over-current-active-low; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ +&usdhc1 { + status = "disabled"; +}; + +&iomuxc { + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * I: yellow led + */ + pinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j + &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_m + &pinctrl_dhcom_n &pinctrl_dhcom_o &pinctrl_dhcom_p + &pinctrl_dhcom_q &pinctrl_dhcom_r &pinctrl_dhcom_s + &pinctrl_dhcom_int>; +}; diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi index d316e869516..af229501a4d 100644 --- a/arch/arm/dts/imx8qm-u-boot.dtsi +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -10,7 +10,7 @@ }; &binman { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u-boot-spl-ddr { align = <4>; align-size = <4>; diff --git a/arch/arm/dts/imx8qxp-u-boot.dtsi b/arch/arm/dts/imx8qxp-u-boot.dtsi index 7622c40906f..62791c34c77 100644 --- a/arch/arm/dts/imx8qxp-u-boot.dtsi +++ b/arch/arm/dts/imx8qxp-u-boot.dtsi @@ -10,7 +10,7 @@ }; &binman { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u-boot-spl-ddr { align = <4>; align-size = <4>; diff --git a/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi new file mode 100644 index 00000000000..27b4b2ed84a --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include "imx93-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + bootph-pre-ram; + bootph-some-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index 03e6a858a7b..a25eae9bd38 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -87,7 +87,7 @@ reg = <0x402c0000 0x4000>; interrupts = <110>; clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, - <&clks IMXRT1050_CLK_OSC>, + <&clks IMXRT1050_CLK_AHB_PODF>, <&clks IMXRT1050_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts index c2fd0c0392c..0d8e7016860 100644 --- a/arch/arm/dts/imxrt1170-evk.dts +++ b/arch/arm/dts/imxrt1170-evk.dts @@ -20,6 +20,8 @@ }; memory { + #address-cells = <1>; + #size-cells = <1>; device_type = "memory"; reg = <0x20240000 0xf0000 0x80000000 0x4000000>; diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts index ec5d3f4ba2c..b8e5f49a1fc 100644 --- a/arch/arm/dts/k3-am62-r5-lp-sk.dts +++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts @@ -25,7 +25,8 @@ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <1200000000>; diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index f0b66f0cb94..9e0a6ed6784 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -24,7 +24,8 @@ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <1250000000>; diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 0912b953db0..d2dd75469c1 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -25,7 +25,8 @@ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <1200000000>; diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index bc05dcb5efb..464227b3b25 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -23,7 +23,8 @@ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <1200000000>; diff --git a/arch/arm/dts/k3-am62p5-r5-sk.dts b/arch/arm/dts/k3-am62p5-r5-sk.dts index 658f2cf730a..baf1a83dc12 100644 --- a/arch/arm/dts/k3-am62p5-r5-sk.dts +++ b/arch/arm/dts/k3-am62p5-r5-sk.dts @@ -26,7 +26,8 @@ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <1200000000>; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index be8596987ba..933f75095b1 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -22,7 +22,8 @@ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <1000000000>; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 2186152a0b8..6e31dfd97c5 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -22,7 +22,8 @@ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <1000000000>; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index dea2ba85dcb..ab5195eb15c 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -22,7 +22,8 @@ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 202 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 202 0>; assigned-clock-rates = <800000000>; ti,sci = <&dmsc>; diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts index 4d6aab5ccc3..13809f82d99 100644 --- a/arch/arm/dts/k3-am69-r5-sk.dts +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -26,7 +26,8 @@ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 202 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <2000000000>; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 94760c78dd3..f096b102793 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -23,7 +23,8 @@ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; + clocks = <&k3_clks 61 1>, <&k3_clks 202 2>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>; assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>; assigned-clock-rates = <2000000000>, <200000000>; @@ -102,3 +103,8 @@ &mcu_udmap { ti,sci = <&dm_tifs>; }; + +&wkup_vtm0 { + vdd-supply-2 = <&buckb1>; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi index fd0d921272c..688a6cf4089 100644 --- a/arch/arm/dts/k3-j721e-r5.dtsi +++ b/arch/arm/dts/k3-j721e-r5.dtsi @@ -20,7 +20,8 @@ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; + clocks = <&k3_clks 61 1>, <&k3_clks 202 2>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; assigned-clock-rates = <2000000000>, <200000000>; ti,sci = <&dmsc>; diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts index e92b1917df4..506ad9b7910 100644 --- a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts @@ -10,3 +10,12 @@ #include "k3-j721s2-ddr.dtsi" #include "k3-j721s2-common-proc-board-u-boot.dtsi" #include "k3-j721s2-r5.dtsi" + +&tps659411 { + bootph-pre-ram; +}; + +&wkup_vtm0 { + bootph-pre-ram; + vdd-supply-2 = <&bucka1234>; +}; diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index caf696c2d96..634676c8491 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -20,7 +20,8 @@ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 1>; + clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>; assigned-clock-parents = <&k3_clks 61 3>; assigned-clock-rates = <200000000>, <2000000000>; diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi index 28087a3b6fb..6b521166575 100644 --- a/arch/arm/dts/k3-j722s-binman.dtsi +++ b/arch/arm/dts/k3-j722s-binman.dtsi @@ -8,6 +8,56 @@ #if IS_ENABLED(CONFIG_TARGET_J722S_R5_EVM) &binman { + tiboot3-j722s-hs-evm.bin { + filename = "tiboot3-j722s-hs-evm.bin"; + ti-secure-rom { + content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>, + <&combined_dm_cfg>, <&sysfw_inner_cert>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl>; + content-sysfw = <&ti_fs_enc>; + content-sysfw-data = <&combined_tifs_cfg>; + content-sysfw-inner-cert = <&sysfw_inner_cert>; + content-dm-data = <&combined_dm_cfg>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c7a800>; + }; + + u_boot_spl: u-boot-spl { + no-expanded; + }; + + ti_fs_enc: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +&binman { tiboot3-j722s-hs-fs-evm.bin { filename = "tiboot3-j722s-hs-fs-evm.bin"; symlink = "tiboot3.bin"; diff --git a/arch/arm/dts/k3-j722s-ddr-lp4-50-4000.dtsi b/arch/arm/dts/k3-j722s-ddr-lp4-50-4000.dtsi new file mode 100644 index 00000000000..8cd121a5920 --- /dev/null +++ b/arch/arm/dts/k3-j722s-ddr-lp4-50-4000.dtsi @@ -0,0 +1,2797 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023-2024 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.21.1+3772 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.11.0 + * This file was generated on Mon Sep 23 2024 00:17:01 GMT+0530 (IST) + */ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 25000000 +#define DDRSS_PLL_FREQUENCY_1 1000000000 +#define DDRSS_PLL_FREQUENCY_2 1000000000 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x00061A80 +#define DDRSS_CTL_12_DATA 0x003D0900 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000FA0 +#define DDRSS_CTL_15_DATA 0x00061A80 +#define DDRSS_CTL_16_DATA 0x003D0900 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000FA0 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00005050 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000800 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000204 +#define DDRSS_CTL_50_DATA 0x00820014 +#define DDRSS_CTL_51_DATA 0x0915005A +#define DDRSS_CTL_52_DATA 0x00003E28 +#define DDRSS_CTL_53_DATA 0x00820014 +#define DDRSS_CTL_54_DATA 0x0915005A +#define DDRSS_CTL_55_DATA 0x09003E28 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x0400036D +#define DDRSS_CTL_58_DATA 0x09102005 +#define DDRSS_CTL_59_DATA 0x00001C14 +#define DDRSS_CTL_60_DATA 0x0F00891C +#define DDRSS_CTL_61_DATA 0x09102010 +#define DDRSS_CTL_62_DATA 0x00001C14 +#define DDRSS_CTL_63_DATA 0x0F00891C +#define DDRSS_CTL_64_DATA 0x03042010 +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x26292629 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x044E4E08 +#define DDRSS_CTL_69_DATA 0x042E2E04 +#define DDRSS_CTL_70_DATA 0x00002E2E +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x00130803 +#define DDRSS_CTL_75_DATA 0x00000059 +#define DDRSS_CTL_76_DATA 0x000002F8 +#define DDRSS_CTL_77_DATA 0x00000F34 +#define DDRSS_CTL_78_DATA 0x000002F8 +#define DDRSS_CTL_79_DATA 0x00000F34 +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x0000000A +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x0000017C +#define DDRSS_CTL_84_DATA 0x000003C8 +#define DDRSS_CTL_85_DATA 0x0000017C +#define DDRSS_CTL_86_DATA 0x000003C8 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000F0005 +#define DDRSS_CTL_90_DATA 0x2C08000F +#define DDRSS_CTL_91_DATA 0x0A05052C +#define DDRSS_CTL_92_DATA 0x1C0F0A03 +#define DDRSS_CTL_93_DATA 0x1C0F0A04 +#define DDRSS_CTL_94_DATA 0x04010104 +#define DDRSS_CTL_95_DATA 0x00010401 +#define DDRSS_CTL_96_DATA 0x00140014 +#define DDRSS_CTL_97_DATA 0x03070307 +#define DDRSS_CTL_98_DATA 0x03070307 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x04041E04 +#define DDRSS_CTL_103_DATA 0x0F0A0F0A +#define DDRSS_CTL_104_DATA 0x0A04041E +#define DDRSS_CTL_105_DATA 0x030F0A0F +#define DDRSS_CTL_106_DATA 0x00000404 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00001640 +#define DDRSS_CTL_120_DATA 0x00001640 +#define DDRSS_CTL_121_DATA 0x00001640 +#define DDRSS_CTL_122_DATA 0x00001640 +#define DDRSS_CTL_123_DATA 0x00001640 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000026F +#define DDRSS_CTL_126_DATA 0x0003CD00 +#define DDRSS_CTL_127_DATA 0x0003CD00 +#define DDRSS_CTL_128_DATA 0x0003CD00 +#define DDRSS_CTL_129_DATA 0x0003CD00 +#define DDRSS_CTL_130_DATA 0x0003CD00 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x00006A6C +#define DDRSS_CTL_133_DATA 0x0003CD00 +#define DDRSS_CTL_134_DATA 0x0003CD00 +#define DDRSS_CTL_135_DATA 0x0003CD00 +#define DDRSS_CTL_136_DATA 0x0003CD00 +#define DDRSS_CTL_137_DATA 0x0003CD00 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x00006A6C +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x040A040A +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x07010A09 +#define DDRSS_CTL_162_DATA 0x000E0A09 +#define DDRSS_CTL_163_DATA 0x010A0900 +#define DDRSS_CTL_164_DATA 0x0E0A0907 +#define DDRSS_CTL_165_DATA 0x0A090000 +#define DDRSS_CTL_166_DATA 0x0A090701 +#define DDRSS_CTL_167_DATA 0x0000000E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00C80190 +#define DDRSS_CTL_199_DATA 0x0F0F01F4 +#define DDRSS_CTL_200_DATA 0x000001F4 +#define DDRSS_CTL_201_DATA 0x00C80190 +#define DDRSS_CTL_202_DATA 0x0F0F01F4 +#define DDRSS_CTL_203_DATA 0x000001F4 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000084 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x000000E4 +#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x000000E4 +#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000084 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x000000E4 +#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x000000E4 +#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x000000B3 +#define DDRSS_CTL_228_DATA 0x000000B3 +#define DDRSS_CTL_229_DATA 0x000000B3 +#define DDRSS_CTL_230_DATA 0x000000B3 +#define DDRSS_CTL_231_DATA 0x000000B3 +#define DDRSS_CTL_232_DATA 0x000000B3 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x35000000 +#define DDRSS_CTL_257_DATA 0x35353535 +#define DDRSS_CTL_258_DATA 0x00002735 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000000F +#define DDRSS_CTL_267_DATA 0x0000000F +#define DDRSS_CTL_268_DATA 0x0000000F +#define DDRSS_CTL_269_DATA 0x0000000F +#define DDRSS_CTL_270_DATA 0x0000000F +#define DDRSS_CTL_271_DATA 0x0000000F +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00001600 +#define DDRSS_CTL_274_DATA 0x00000016 +#define DDRSS_CTL_275_DATA 0x00000016 +#define DDRSS_CTL_276_DATA 0x00000016 +#define DDRSS_CTL_277_DATA 0x00000016 +#define DDRSS_CTL_278_DATA 0x00000016 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x07D00040 +#define DDRSS_CTL_316_DATA 0x0002003C +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x003C07D0 +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x00640064 +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000101 +#define DDRSS_CTL_324_DATA 0x1FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0x3FFF2000 +#define DDRSS_CTL_327_DATA 0x000FFF00 +#define DDRSS_CTL_328_DATA 0x0B000001 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C03 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01090903 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0F081B1B +#define DDRSS_CTL_389_DATA 0x0009040F +#define DDRSS_CTL_390_DATA 0x0B0D040F +#define DDRSS_CTL_391_DATA 0x0B0D0406 +#define DDRSS_CTL_392_DATA 0x0D0D0906 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x08030801 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x000000B2 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000321 +#define DDRSS_CTL_403_DATA 0x000006F4 +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x39200201 +#define DDRSS_CTL_406_DATA 0x00001E68 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x000088D4 +#define DDRSS_CTL_412_DATA 0x00013010 +#define DDRSS_CTL_413_DATA 0x111A0402 +#define DDRSS_CTL_414_DATA 0x39200C09 +#define DDRSS_CTL_415_DATA 0x00001E68 +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x000088D4 +#define DDRSS_CTL_421_DATA 0x00013010 +#define DDRSS_CTL_422_DATA 0x111A0402 +#define DDRSS_CTL_423_DATA 0x00200C09 +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x000F0001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x000F0F00 +#define DDRSS_PI_49_DATA 0x0000001A +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x0000170F +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010F00 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x01010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F12 +#define DDRSS_PI_101_DATA 0x08111413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x012C012C +#define DDRSS_PI_178_DATA 0x00282801 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x00000060 +#define DDRSS_PI_181_DATA 0x00020060 +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x0000100C +#define DDRSS_PI_185_DATA 0x00104000 +#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_187_DATA 0x00000013 +#define DDRSS_PI_188_DATA 0x00000059 +#define DDRSS_PI_189_DATA 0x000002F8 +#define DDRSS_PI_190_DATA 0x00000F34 +#define DDRSS_PI_191_DATA 0x000002F8 +#define DDRSS_PI_192_DATA 0x04000F34 +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00290029 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05090903 +#define DDRSS_PI_200_DATA 0x01011B1B +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0C021212 +#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x001D0045 +#define DDRSS_PI_210_DATA 0x001D0045 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x000301F4 +#define DDRSS_PI_214_DATA 0x010001F4 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01F50100 +#define DDRSS_PI_217_DATA 0x010001F5 +#define DDRSS_PI_218_DATA 0x01F501F5 +#define DDRSS_PI_219_DATA 0x32103200 +#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x1D12090D +#define DDRSS_PI_223_DATA 0x1D120913 +#define DDRSS_PI_224_DATA 0x000C0013 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x0022000D +#define DDRSS_PI_231_DATA 0x002201F4 +#define DDRSS_PI_232_DATA 0x000001F4 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000301 +#define DDRSS_PI_236_DATA 0x00310204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x17000301 +#define DDRSS_PI_239_DATA 0x00310C12 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x17000301 +#define DDRSS_PI_242_DATA 0x00000C12 +#define DDRSS_PI_243_DATA 0x05040900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x00000315 +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x2E100000 +#define DDRSS_PI_249_DATA 0x26150029 +#define DDRSS_PI_250_DATA 0x00007B66 +#define DDRSS_PI_251_DATA 0x2008005A +#define DDRSS_PI_252_DATA 0x1C141C1E +#define DDRSS_PI_253_DATA 0x2E100000 +#define DDRSS_PI_254_DATA 0x26150029 +#define DDRSS_PI_255_DATA 0x00007B66 +#define DDRSS_PI_256_DATA 0x2008005A +#define DDRSS_PI_257_DATA 0x1C141C1E +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x000000B2 +#define DDRSS_PI_260_DATA 0x000006F4 +#define DDRSS_PI_261_DATA 0x00001E68 +#define DDRSS_PI_262_DATA 0x00013010 +#define DDRSS_PI_263_DATA 0x00001E68 +#define DDRSS_PI_264_DATA 0x00013010 +#define DDRSS_PI_265_DATA 0x03070014 +#define DDRSS_PI_266_DATA 0x03030307 +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x0A040503 +#define DDRSS_PI_270_DATA 0x00000A04 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x00000014 +#define DDRSS_PI_276_DATA 0x00061A80 +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000FA0 +#define DDRSS_PI_280_DATA 0x00000307 +#define DDRSS_PI_281_DATA 0x00061A80 +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000FA0 +#define DDRSS_PI_285_DATA 0x01000307 +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x07D00040 +#define DDRSS_PI_289_DATA 0x0001003C +#define DDRSS_PI_290_DATA 0x07D00040 +#define DDRSS_PI_291_DATA 0x0000033C +#define DDRSS_PI_292_DATA 0x00280064 +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13100A18 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000084 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x000000B3 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x35000000 +#define DDRSS_PI_335_DATA 0x20160F27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x000000E4 +#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_339_DATA 0x000000B3 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x35000000 +#define DDRSS_PI_343_DATA 0x20160F27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x000000E4 +#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_347_DATA 0x000000B3 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x35000000 +#define DDRSS_PI_351_DATA 0x20160F27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000084 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x000000B3 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x35000000 +#define DDRSS_PI_359_DATA 0x20160F27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x000000E4 +#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_363_DATA 0x000000B3 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x35000000 +#define DDRSS_PI_367_DATA 0x20160F27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x000000E4 +#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_371_DATA 0x000000B3 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x35000000 +#define DDRSS_PI_375_DATA 0x20160F27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000084 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x000000B3 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x35000000 +#define DDRSS_PI_383_DATA 0x20160F27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x000000E4 +#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_387_DATA 0x000000B3 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x35000000 +#define DDRSS_PI_391_DATA 0x20160F27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x000000E4 +#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_395_DATA 0x000000B3 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x35000000 +#define DDRSS_PI_399_DATA 0x20160F27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000084 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x000000B3 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x35000000 +#define DDRSS_PI_407_DATA 0x20160F27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x000000E4 +#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_411_DATA 0x000000B3 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x35000000 +#define DDRSS_PI_415_DATA 0x20160F27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x000000E4 +#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_419_DATA 0x000000B3 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x35000000 +#define DDRSS_PI_423_DATA 0x20160F27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000301 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071040 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0C01 +#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00041000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02000010 +#define DDRSS_PHY_93_DATA 0x00000005 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06001 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0D000000 +#define DDRSS_PHY_99_DATA 0x000D0C0C +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C083E +#define DDRSS_PHY_102_DATA 0x000F0C35 +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x01330120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x00000300 +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000D2010 +#define DDRSS_PHY_111_DATA 0x76543210 +#define DDRSS_PHY_112_DATA 0x00000008 +#define DDRSS_PHY_113_DATA 0x04800480 +#define DDRSS_PHY_114_DATA 0x04800480 +#define DDRSS_PHY_115_DATA 0x04800480 +#define DDRSS_PHY_116_DATA 0x04800480 +#define DDRSS_PHY_117_DATA 0x00000480 +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x011900A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000301 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071040 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0C01 +#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00041000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02000010 +#define DDRSS_PHY_349_DATA 0x00000005 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06001 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0D000000 +#define DDRSS_PHY_355_DATA 0x000D0C0C +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C083E +#define DDRSS_PHY_358_DATA 0x000F0C35 +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x01330120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x00000300 +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000D2010 +#define DDRSS_PHY_367_DATA 0x76543210 +#define DDRSS_PHY_368_DATA 0x00000008 +#define DDRSS_PHY_369_DATA 0x04800480 +#define DDRSS_PHY_370_DATA 0x04800480 +#define DDRSS_PHY_371_DATA 0x04800480 +#define DDRSS_PHY_372_DATA 0x04800480 +#define DDRSS_PHY_373_DATA 0x00000480 +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x011900A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000301 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071040 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0C01 +#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00041000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02000010 +#define DDRSS_PHY_605_DATA 0x00000005 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06001 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0D000000 +#define DDRSS_PHY_611_DATA 0x000D0C0C +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C083E +#define DDRSS_PHY_614_DATA 0x000F0C35 +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x01330120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x00000300 +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000D2010 +#define DDRSS_PHY_623_DATA 0x76543210 +#define DDRSS_PHY_624_DATA 0x00000008 +#define DDRSS_PHY_625_DATA 0x04800480 +#define DDRSS_PHY_626_DATA 0x04800480 +#define DDRSS_PHY_627_DATA 0x04800480 +#define DDRSS_PHY_628_DATA 0x04800480 +#define DDRSS_PHY_629_DATA 0x00000480 +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x011900A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000301 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071040 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0C01 +#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00041000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02000010 +#define DDRSS_PHY_861_DATA 0x00000005 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06001 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0D000000 +#define DDRSS_PHY_867_DATA 0x000D0C0C +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C083E +#define DDRSS_PHY_870_DATA 0x000F0C35 +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x01330120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x00000300 +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000D2010 +#define DDRSS_PHY_879_DATA 0x76543210 +#define DDRSS_PHY_880_DATA 0x00000008 +#define DDRSS_PHY_881_DATA 0x04800480 +#define DDRSS_PHY_882_DATA 0x04800480 +#define DDRSS_PHY_883_DATA 0x04800480 +#define DDRSS_PHY_884_DATA 0x04800480 +#define DDRSS_PHY_885_DATA 0x00000480 +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x011900A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000405CC +#define DDRSS_PHY_1062_DATA 0x03000004 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000405CC +#define DDRSS_PHY_1318_DATA 0x03000004 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000405CC +#define DDRSS_PHY_1574_DATA 0x03000004 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F0F +#define DDRSS_PHY_1822_DATA 0x0F0F0F0F +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x02010804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C4 +#define DDRSS_PHY_1889_DATA 0x04000004 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000005 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts index aff83cd5d91..5e5c2e3111e 100644 --- a/arch/arm/dts/k3-j722s-r5-evm.dts +++ b/arch/arm/dts/k3-j722s-r5-evm.dts @@ -7,7 +7,7 @@ #include "k3-j722s-evm.dts" #include "k3-j722s-evm-u-boot.dtsi" -#include "k3-j722s-ddr-lp4-50-3733.dtsi" +#include "k3-j722s-ddr-lp4-50-4000.dtsi" #include "k3-am62a-ddr.dtsi" / { @@ -25,10 +25,11 @@ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 135 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; assigned-clock-parents = <&k3_clks 61 2>; - assigned-clock-rates = <200000000>, <1200000000>; + assigned-clock-rates = <200000000>, <1400000000>; ti,sci = <&dmsc>; ti,sci-proc-id = <32>; ti,sci-host-id = <10>; diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts index d2c75229363..8b8b0e70047 100644 --- a/arch/arm/dts/k3-j784s4-r5-evm.dts +++ b/arch/arm/dts/k3-j784s4-r5-evm.dts @@ -26,7 +26,8 @@ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; resets = <&k3_reset 202 0>; - clocks = <&k3_clks 61 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 202 0>; + clock-names = "gtc", "core"; assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>; assigned-clock-parents = <&k3_clks 61 2>; assigned-clock-rates = <200000000>, <2000000000>; diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi index 8070b62af5b..6629f3256a8 100644 --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi @@ -17,10 +17,6 @@ }; }; -&canvas { - status = "disabled"; -}; - &vpu { reg = <0x0 0xff900000 0x0 0x100000>, <0x0 0xff63c000 0x0 0x1000>, diff --git a/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi b/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi new file mode 100644 index 00000000000..cbada739042 --- /dev/null +++ b/arch/arm/dts/meson-g12b-a311d-libretech-cc-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> + */ + +#include "meson-g12-common-u-boot.dtsi" + +&sd_emmc_c { + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>; + bus-width = <4>; +}; + +&spifc { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi b/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi new file mode 100644 index 00000000000..1c4f019120f --- /dev/null +++ b/arch/arm/dts/meson-sm1-s905d3-libretech-cc-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org> + */ + +#include "meson-g12-common-u-boot.dtsi" + +&sd_emmc_c { + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>; + bus-width = <4>; +}; + +&spifc { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi index 39bb66c4fcb..a30adb0be98 100644 --- a/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi +++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi @@ -6,6 +6,12 @@ #include "rk3328-u-boot.dtsi" / { + leds { + led-0 { + default-state = "on"; + }; + }; + smbios { compatible = "u-boot,sysinfo-smbios"; diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi index 037cec10ce3..7438bec4ee6 100644 --- a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -15,13 +15,8 @@ }; &spi1 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; bootph-pre-ram; bootph-some-ram; - spi-max-frequency = <10000000>; }; }; diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi index 5ec15a845c1..7a6af430a6f 100644 --- a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -1,8 +1,22 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> * Copyright (c) 2023 Radxa Limited */ -#include "rk3399-rock-pi-4-u-boot.dtsi" +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + leds { + led-0 { + default-state = "on"; + }; + + led-1 { + default-state = "on"; + }; + }; +}; &pcfg_pull_none_18ma { bootph-pre-ram; @@ -14,6 +28,12 @@ bootph-some-ram; }; +&sdhci { + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; +}; + &spi1 { status = "okay"; @@ -25,3 +45,7 @@ spi-max-frequency = <10000000>; }; }; + +&vdd_log { + regulator-init-microvolt = <950000>; +}; diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index b3bfc77f756..4861574636e 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -6,6 +6,14 @@ #include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr4-100.dtsi" +/ { + leds { + led-0 { + default-state = "on"; + }; + }; +}; + &sdhci { cap-mmc-highspeed; mmc-ddr-1_8v; diff --git a/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi new file mode 100644 index 00000000000..fa3fbe6c810 --- /dev/null +++ b/arch/arm/dts/rk3566-anbernic-rg353p-u-boot.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = &sdmmc0, &sdhci; + }; + + /* + * Adding fixed regulator to work around driver regulator + * requirements. Note that the correct regulator is on by + * default at boot and that saradc regulator gets corrected + * when proper device-tree is loaded. + */ + vcc_1v8_dummy: vcc-1v8-dummy { + bootph-pre-ram; + bootph-some-ram; + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_dummy"; + status = "okay"; + }; +}; + +&saradc { + bootph-pre-ram; + bootph-some-ram; + vref-supply = <&vcc_1v8_dummy>; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi deleted file mode 100644 index c7e849816a6..00000000000 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include "rk356x-u-boot.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = &sdmmc0, &sdhci; - }; -}; - -&dsi_dphy0 { - status = "okay"; -}; - -&dsi0 { - status = "okay"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2m1_xfer>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pmucru { - assigned-clocks = <&pmucru SCLK_32K_IOE>; - assigned-clock-parents = <&pmucru CLK_RTC_32K>; -}; - -/* - * We don't need the clocks, but if they are present they may cause - * probing to fail so we remove them for U-Boot. - */ -&rk817 { - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-parents; - /delete-property/ clocks; - /delete-property/ clock-names; -}; - -&sdhci { - pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, - <&emmc_datastrobe>, <&emmc_rstnout>; - pinctrl-names = "default"; - bus-width = <8>; - max-frequency = <200000000>; - mmc-hs200-1_8v; - non-removable; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts deleted file mode 100644 index c393c8d07af..00000000000 --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3566-anbernic-rgxx3.dtsi" - -/ { - -/* - * Note this is a pseudo-model that doesn't exist in mainline Linux. - * This model is used for all RGXX3 devices and the board.c file will - * set the correct dtb name for loading mainline Linux automatically. - */ - model = "RGXX3"; - compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s", - "anbernic,rg353m", "anbernic,rg353p", - "anbernic,rg353ps", "anbernic,rg353v", - "anbernic,rg353vs", "anbernic,rg503", - "powkiddy,rgb10max3", "powkiddy,rgb30", - "powkiddy,rk2023", "rockchip,rk3566"; -}; - -&cru { - assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, - <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; - assigned-clock-rates = <32768>, <1200000000>, - <200000000>, <241500000>; -}; diff --git a/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi b/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi new file mode 100644 index 00000000000..6e8307e3bdf --- /dev/null +++ b/arch/arm/dts/rk3566-odroid-m1s-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index e0e501deccf..412f9e06aff 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -5,6 +5,14 @@ #include "rk356x-u-boot.dtsi" +/ { + leds { + led-1 { + default-state = "on"; + }; + }; +}; + &sdhci { cap-mmc-highspeed; }; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi index 74755a44eae..efeab626d8a 100644 --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -2,6 +2,29 @@ #include "rk356x-u-boot.dtsi" +/ { + gpio-leds { + led-0 { + default-state = "on"; + }; + + led-red { + default-state = "on"; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + }; + + led-green { + default-state = "on"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + default-state = "on"; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + }; +}; + &pcie3x1 { pinctrl-0 = <&pcie30x1_reset_h>; }; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 0da3d9c56b8..29c18f5a340 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -6,6 +6,14 @@ #include "rk356x-u-boot.dtsi" +/ { + leds { + led-0 { + default-state = "on"; + }; + }; +}; + &pcie3x2 { pinctrl-0 = <&pcie3x2_reset_h>; }; diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi index 968385622fa..8465dcd4c9c 100644 --- a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi +++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi @@ -11,20 +11,14 @@ bootph-some-ram; }; -&sfc { - pinctrl-names = "default"; - pinctrl-0 = <&fspim1_pins>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; +&saradc { + bootph-pre-ram; + vdd-microvolts = <1800000>; +}; +&sfc { flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; bootph-pre-ram; bootph-some-ram; - spi-max-frequency = <24000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; }; }; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 4dd17ff408c..d51fbf51cb8 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -3,31 +3,58 @@ * Copyright (c) 2023 Collabora Ltd. */ +#include <dt-bindings/usb/pd.h> #include "rk3588-u-boot.dtsi" +/ { + leds { + led_rgb_b { + default-state = "on"; + }; + }; +}; + &fspim2_pins { bootph-pre-ram; bootph-some-ram; }; +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "sink"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>, + <PDO_VAR(5000, 20000, 5000)>; + }; + }; +}; + &sdhci { cap-mmc-highspeed; mmc-hs200-1_8v; }; &sfc { - pinctrl-names = "default"; - pinctrl-0 = <&fspim2_pins>; - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; bootph-pre-ram; bootph-some-ram; - spi-max-frequency = <24000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; }; }; diff --git a/arch/arm/dts/rk3588s-odroid-m2-u-boot.dtsi b/arch/arm/dts/rk3588s-odroid-m2-u-boot.dtsi new file mode 100644 index 00000000000..853ed58cfe5 --- /dev/null +++ b/arch/arm/dts/rk3588s-odroid-m2-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index efba0c359ba..a75ae296386 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -5,6 +5,14 @@ #include "rk3588s-u-boot.dtsi" +/ { + leds { + io-led { + default-state = "on"; + }; + }; +}; + &sdhci { cap-mmc-highspeed; mmc-hs200-1_8v; diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts deleted file mode 100644 index fc1c48ad56d..00000000000 --- a/arch/arm/dts/stm32mp135f-dhcor-dhsbc.dts +++ /dev/null @@ -1,383 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2024 Marek Vasut <marex@denx.de> - * - * DHCOR STM32MP13 variant: - * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG - * DHCOR PCB number: 718-100 or newer - * DHSBC PCB number: 719-100 or newer - */ - -/dts-v1/; - -#include <dt-bindings/regulator/st,stm32mp13-regulator.h> -#include "stm32mp135.dtsi" -#include "stm32mp13xf.dtsi" -#include "stm32mp13xx-dhcor-som.dtsi" - -/ { - model = "DH electronics STM32MP135F DHCOR DHSBC"; - compatible = "dh,stm32mp135f-dhcor-dhsbc", - "dh,stm32mp135f-dhcor-som", - "st,stm32mp135"; - - aliases { - ethernet0 = ð1; - ethernet1 = ð2; - serial2 = &usart1; - serial3 = &usart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&adc_1 { - pinctrl-names = "default"; - pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>; - vdda-supply = <&vdd_adc>; - vref-supply = <&vdd_adc>; - status = "okay"; - - adc1: adc@0 { - status = "okay"; - - /* - * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11. - * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: - * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. - * Use arbitrary margin here (e.g. 5us). - * - * The pinmux pins must be set as ANALOG, use datasheet - * DS13483 Table 7. STM32MP135C/F ball definitions to - * find out which 'pin name' maps to which 'additional - * functions', which lists the mapping between pin and - * ADC channel. In this case, PA5 maps to ADC1_INP2 and - * PF13 maps to ADC1_INP11 . - */ - channel@2 { - reg = <2>; - st,min-sample-time-ns = <5000>; - }; - - channel@11 { - reg = <11>; - st,min-sample-time-ns = <5000>; - }; - - /* Expansion connector: INP12:pin29 */ - channel@12 { - reg = <12>; - st,min-sample-time-ns = <5000>; - }; - }; -}; - -ð1 { - status = "okay"; - pinctrl-0 = <ð1_rgmii_pins_a>; - pinctrl-1 = <ð1_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - st,ext-phyclk; - nvmem-cells = <ðernet_mac1_address>; - nvmem-cell-names = "mac-address"; - - mdio1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - ethphy1: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpiog>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - reg = <1>; - reset-assert-us = <15000>; - reset-deassert-us = <55000>; - reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð2 { - status = "okay"; - pinctrl-0 = <ð2_rgmii_pins_a>; - pinctrl-1 = <ð2_rgmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii-id"; - phy-handle = <ðphy2>; - st,ext-phyclk; - nvmem-cells = <ðernet_mac2_address>; - nvmem-cell-names = "mac-address"; - - mdio1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - ethphy2: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpiog>; - interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - reg = <1>; - reset-assert-us = <15000>; - reset-deassert-us = <55000>; - reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpioa { - gpio-line-names = "", "", "", "", - "", "DHSBC_USB_PWR_CC1", "", "", - "", "", "", "DHSBC_nETH1_RST", - "", "DHCOR_HW-CODING_0", "", ""; -}; - -&gpiob { - gpio-line-names = "", "", "", "", - "", "", "", "DHCOR_BT_HOST_WAKE", - "", "", "", "", - "", "DHSBC_nTPM_CS", "", ""; -}; - -&gpioc { - gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "DHCOR_RAM-CODING_0", "", "", - "", "DHCOR_RAM-CODING_1", "", "", - "", "", "", ""; -}; - -&gpioe { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "DHSBC_nTPM_RST", "", "", - "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", ""; -}; - -&gpiof { - gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "", - "", "", "", "", - "", "", "", "", - "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", ""; -}; - -&gpiog { - gpio-line-names = "", "", "", "", - "", "", "", "", - "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "", - "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; -}; - -&gpioi { - gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", - "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", - "DHSBC_BOOT0", "DHSBC_BOOT1", - "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS"; -}; - -&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_sleep_pins_a>; - i2c-scl-rising-time-ns = <96>; - i2c-scl-falling-time-ns = <3>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_pins_b>; - pinctrl-1 = <&i2c5_sleep_pins_b>; - i2c-scl-rising-time-ns = <96>; - i2c-scl-falling-time-ns = <3>; - clock-frequency = <400000>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can1_pins_a>; - pinctrl-1 = <&m_can1_sleep_pins_a>; - status = "okay"; -}; - -&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can2_pins_a>; - pinctrl-1 = <&m_can2_sleep_pins_a>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; - status = "okay"; -}; - -&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */ - clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>; - pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>; -}; - -&scmi_voltd { - status = "disabled"; -}; - -&spi2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi2_pins_a>; - pinctrl-1 = <&spi2_sleep_pins_a>; - cs-gpios = <&gpiob 13 0>; - status = "okay"; - - st33htph: tpm@0 { - compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; - reg = <0>; - spi-max-frequency = <24000000>; - }; -}; - -&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi3_pins_a>; - pinctrl-1 = <&spi3_sleep_pins_a>; - cs-gpios = <&gpiof 3 0>; - status = "disabled"; -}; - -&timers5 { /* Expansion connector: CH3:pin31 */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - pwm { - pinctrl-0 = <&pwm5_pins_a>; - pinctrl-1 = <&pwm5_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@4 { - status = "okay"; - }; -}; - -&timers13 { /* Expansion connector: CH1:pin32 */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - pwm { - pinctrl-0 = <&pwm13_pins_a>; - pinctrl-1 = <&pwm13_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - status = "okay"; - }; - timer@12 { - status = "okay"; - }; -}; - -&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart1_pins_b>; - pinctrl-1 = <&usart1_sleep_pins_b>; - pinctrl-2 = <&usart1_idle_pins_b>; - status = "okay"; -}; - -&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */ - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart2_pins_b>; - pinctrl-1 = <&usart2_sleep_pins_b>; - pinctrl-2 = <&usart2_idle_pins_b>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbh_ohci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - usb33d-supply = <&usb33>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - st,current-boost-microamp = <1000>; - st,decrease-hs-slew-rate; - st,tune-hs-dc-level = <2>; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <11>; - st,trim-hs-impedance = <2>; - st,tune-squelch-level = <1>; - st,enable-hs-rx-gain-eq; - st,no-hs-ftime-ctrl; - st,no-lsfs-sc; - connector { - compatible = "usb-a-connector"; - vbus-supply = <&vbus_sw>; - }; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - st,current-boost-microamp = <1000>; - st,decrease-hs-slew-rate; - st,tune-hs-dc-level = <2>; - st,enable-hs-rftime-reduction; - st,trim-hs-current = <11>; - st,trim-hs-impedance = <2>; - st,tune-squelch-level = <1>; - st,enable-hs-rx-gain-eq; - st,no-hs-ftime-ctrl; - st,no-lsfs-sc; - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; - label = "Type-C"; - self-powered; - type = "micro"; - }; -}; diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index fe56f05616a..66d4c40c6a8 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -56,6 +56,24 @@ status = "okay"; }; }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + bootph-pre-ram; + opp-650000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; + opp-800000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1350000>; + opp-supported-hw = <0x2>; + }; + }; }; &bsec { @@ -82,14 +100,10 @@ bootph-all; }; -&cpu0_opp_table { - bootph-pre-ram; - opp-650000000 { - bootph-pre-ram; - }; - opp-800000000 { - bootph-pre-ram; - }; +&cpu0 { + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + operating-points-v2 = <&cpu0_opp_table>; }; &gpioa { diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi b/arch/arm/dts/stm32mp151a-dhcor-testbench-u-boot.dtsi index 31995c058eb..31995c058eb 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi +++ b/arch/arm/dts/stm32mp151a-dhcor-testbench-u-boot.dtsi diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi b/arch/arm/dts/stm32mp153c-dhcom-drc02-u-boot.dtsi index f83cfe90b84..f83cfe90b84 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02-u-boot.dtsi +++ b/arch/arm/dts/stm32mp153c-dhcom-drc02-u-boot.dtsi diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi b/arch/arm/dts/stm32mp153c-dhcor-drc-compact-u-boot.dtsi index 038c3a92eb1..038c3a92eb1 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi +++ b/arch/arm/dts/stm32mp153c-dhcor-drc-compact-u-boot.dtsi diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dhcor-avenger96-u-boot.dtsi index ab4d66c9619..ab4d66c9619 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dhcor-avenger96-u-boot.dtsi diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dhcom-pdk2-u-boot.dtsi index 2324926f9df..2324926f9df 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-dhcom-pdk2-u-boot.dtsi diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dhcom-picoitx-u-boot.dtsi index 0bcaec50198..0bcaec50198 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-dhcom-picoitx-u-boot.dtsi diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts deleted file mode 100644 index 90625bf6b60..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020 Marek Vasut <marex@denx.de> - */ -/dts-v1/; - -#include "stm32mp151.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcom-som.dtsi" -#include "stm32mp15xx-dhcom-drc02.dtsi" - -/ { - model = "DH Electronics STM32MP15xx DHCOM DRC02"; - compatible = "dh,stm32mp15xx-dhcom-drc02", - "dh,stm32mp15xx-dhcom-som", - "st,stm32mp1xx"; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi deleted file mode 100644 index 35b1034aa3c..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi +++ /dev/null @@ -1,169 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020 Marek Vasut <marex@denx.de> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&adc { - status = "disabled"; -}; - -&dac { - status = "disabled"; -}; - -&gpiob { - /* - * NOTE: On DRC02, the RS485_RX_En is controlled by a separate - * GPIO line, however the STM32 UART driver assumes RX happens - * during TX anyway and that it only controls drive enable DE - * line. Hence, the RX is always enabled here. - */ - rs485-rx-en-hog { - gpio-hog; - gpios = <8 0>; - output-low; - line-name = "rs485-rx-en"; - }; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-B", "", - "", "", "", "DRC02-Out1", - "DRC02-Out2", "", "", ""; -}; - -&gpioi { - gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I", - "DHCOM-R", "DHCOM-M", "", "", - "DRC02-In2", "", "", "", - "", "", "", ""; - - /* - * NOTE: The USB Hub on the DRC02 needs a reset signal to be - * pulled high in order to be detected by the USB Controller. - * This signal should be handled by USB power sequencing in - * order to reset the Hub when USB bus is powered down, but - * so far there is no such functionality. - */ - usb-hub-hog { - gpio-hog; - gpios = <2 0>; - output-high; - line-name = "usb-hub-reset"; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c4 { - touchscreen@49 { - status = "disabled"; - }; -}; - -&i2c5 { /* TP7/TP8 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&sdmmc3 { - /* - * On DRC02, the SoM does not have SDIO WiFi. The pins - * are used for on-board microSD slot instead. - */ - /delete-property/broken-cd; - cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; - disable-wp; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins_a>; - cs-gpios = <&gpioz 3 0>; - /* Use PIO for the display */ - /delete-property/dmas; - /delete-property/dma-names; - status = "disabled"; /* Enable once there is display driver */ - /* - * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are - * also connected to the display board connector. - */ -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* - * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), - * however the STM32MP1 pinmux cannot map them to UART4 . - */ - -&uart8 { /* RS485 */ - linux,rs485-enabled-at-boot-time; - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts deleted file mode 100644 index b2e450aa13b..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2019 Marek Vasut <marex@denx.de> - */ -/dts-v1/; - -#include "stm32mp151.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcom-som.dtsi" -#include "stm32mp15xx-dhcom-pdk2.dtsi" - -/ { - model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)"; - compatible = "dh,stm32mp15xx-dhcom-pdk2", - "dh,stm32mp15xx-dhcom-som", - "st,stm32mp15x"; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi deleted file mode 100644 index 5f586f02406..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ /dev/null @@ -1,329 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk_ext_audio_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - display_bl: display-bl { - compatible = "pwm-backlight"; - pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - default-brightness-level = <8>; - enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; - power-supply = <®_panel_bl>; - status = "okay"; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - /* - * The EXTi IRQ line 3 is shared with ethernet, - * so mark this as polled GPIO key. - */ - button-0 { - label = "TA1-GPIO-A"; - linux,code = <KEY_A>; - gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; - }; - - /* - * The EXTi IRQ line 6 is shared with touchscreen, - * so mark this as polled GPIO key. - */ - button-1 { - label = "TA2-GPIO-B"; - linux,code = <KEY_B>; - gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; - }; - - /* - * The EXTi IRQ line 0 is shared with PMIC, - * so mark this as polled GPIO key. - */ - button-2 { - label = "TA3-GPIO-C"; - linux,code = <KEY_C>; - gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-3 { - label = "TA4-GPIO-D"; - linux,code = <KEY_D>; - gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - led { - compatible = "gpio-leds"; - - led-0 { - label = "green:led5"; - gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - status = "disabled"; - }; - - led-1 { - label = "green:led6"; - gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - label = "green:led7"; - gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - label = "green:led8"; - gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&display_bl>; - power-supply = <®_panel_bl>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_panel_bl: regulator-panel-bl { - compatible = "regulator-fixed"; - regulator-name = "panel_backlight"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_panel_supply>; - }; - - reg_panel_supply: regulator-panel-supply { - compatible = "regulator-fixed"; - regulator-name = "panel_supply"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - }; - - sound { - compatible = "audio-graph-card"; - routing = - "MIC_IN", "Capture", - "Capture", "Mic Bias", - "Playback", "HP_OUT"; - dais = <&sai2a_port &sai2b_port>; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; - status = "okay"; -}; - -&i2c2 { /* Header X22 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&i2c5 { /* Header X21 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - VDDA-supply = <&v3v3>; - VDDIO-supply = <&vdd>; - - sgtl5000_port: port { - #address-cells = <1>; - #size-cells = <0>; - - sgtl5000_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2a_endpoint>; - frame-master = <&sgtl5000_tx_endpoint>; - bitclock-master = <&sgtl5000_tx_endpoint>; - }; - - sgtl5000_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2b_endpoint>; - frame-master = <&sgtl5000_rx_endpoint>; - bitclock-master = <&sgtl5000_rx_endpoint>; - }; - }; - - }; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&gpioc>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_b>; - pinctrl-1 = <<dc_sleep_pins_b>; - status = "okay"; - - port { - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; - pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&sgtl5000_tx_endpoint>; - format = "i2s"; - mclk-fs = <512>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; - }; - - sai2b: audio-controller@4400b024 { - dma-names = "rx"; - st,sync = <&sai2a 2>; - clocks = <&rcc SAI2_K>, <&sai2a>; - clock-names = "sai_ck", "MCLK"; - status = "okay"; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&sgtl5000_rx_endpoint>; - format = "i2s"; - mclk-fs = <512>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; - }; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - pwm2: pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts deleted file mode 100644 index 3e908102f61..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020 Marek Vasut <marex@denx.de> - */ -/dts-v1/; - -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcom-som.dtsi" -#include "stm32mp15xx-dhcom-picoitx.dtsi" - -/ { - model = "DH Electronics STM32MP15xx DHCOM PicoITX"; - compatible = "dh,stm32mp15xx-dhcom-picoitx", - "dh,stm32mp15xx-dhcom-som", - "st,stm32mp1xx"; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi deleted file mode 100644 index abc595350e7..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020 Marek Vasut <marex@denx.de> - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - led { - compatible = "gpio-leds"; - - led-0 { - label = "yellow:led"; - gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&adc { - status = "disabled"; -}; - -&dac { - status = "disabled"; -}; - -&fmc { - status = "disabled"; -}; - -&gpioa { - /* - * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable - * port power. This signal should be handled by USB power sequencing - * in order to turn on port power when USB bus is powered up, but so - * far there is no such functionality. - */ - usb-port-power-hog { - gpio-hog; - gpios = <13 0>; - output-low; - line-name = "usb-port-power"; - }; -}; - -&gpioc { - gpio-line-names = "", "", "", "", - "", "", "PicoITX-In1", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-B", "", - "", "", "", "PicoITX-Out1", - "PicoITX-Out2", "", "", ""; -}; - -&gpiog { - gpio-line-names = "PicoITX-In2", "", "", "", - "", "", "", "", - "DHCOM-L", "", "", "", - "", "", "", ""; -}; - -&i2c2 { /* On board-to-board connector (optional) */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c5 { /* On board-to-board connector */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; -}; - -&ksz8851 { - status = "disabled"; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbh_ohci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi deleted file mode 100644 index d3b85a8764d..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ /dev/null @@ -1,544 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> - */ - -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxaa-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mfd/st,stpmic1.h> - -/ { - aliases { - ethernet0 = ðernet0; - ethernet1 = &ksz8851; - rtc0 = &hwrtc; - rtc1 = &rtc; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xC0000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mcuram2: mcuram2@10000000 { - compatible = "shared-dma-pool"; - reg = <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible = "shared-dma-pool"; - reg = <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible = "shared-dma-pool"; - reg = <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible = "shared-dma-pool"; - reg = <0x10042000 0x4000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - }; - - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; -}; - -&adc { - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - - adc1: adc@0 { - st,min-sample-time-nsecs = <5000>; - st,adc-channels = <0>; - status = "okay"; - }; - - adc2: adc@100 { - st,adc-channels = <1>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; -}; - -&crc1 { - status = "okay"; -}; - -&dac { - pinctrl-names = "default"; - pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; - vref-supply = <&vdda>; - status = "okay"; - - dac1: dac@1 { - status = "okay"; - }; - dac2: dac@2 { - status = "okay"; - }; -}; - -&dts { - status = "okay"; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - /* LAN8710Ai */ - compatible = "ethernet-phy-id0007.c0f0", - "ethernet-phy-ieee802.3-c22"; - clocks = <&rcc CK_MCO2>; - reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; - reset-assert-us = <500>; - reset-deassert-us = <500>; - smsc,disable-energy-detect; - interrupt-parent = <&gpioi>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_b>; - pinctrl-1 = <&fmc_sleep_pins_b>; - status = "okay"; - - ksz8851: ethernet@1,0 { - compatible = "micrel,ks8851-mll"; - reg = <1 0x0 0x2>, <1 0x2 0x20000>; - interrupt-parent = <&gpioc>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - bank-width = <2>; - - /* Timing values are in nS */ - st,fmc2-ebi-cs-mux-enable; - st,fmc2-ebi-cs-transaction-type = <4>; - st,fmc2-ebi-cs-buswidth = <16>; - st,fmc2-ebi-cs-address-setup-ns = <5>; - st,fmc2-ebi-cs-address-hold-ns = <5>; - st,fmc2-ebi-cs-bus-turnaround-ns = <5>; - st,fmc2-ebi-cs-data-setup-ns = <45>; - st,fmc2-ebi-cs-data-hold-ns = <1>; - st,fmc2-ebi-cs-write-address-setup-ns = <5>; - st,fmc2-ebi-cs-write-address-hold-ns = <5>; - st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; - st,fmc2-ebi-cs-write-data-setup-ns = <45>; - st,fmc2-ebi-cs-write-data-hold-ns = <1>; - }; -}; - -&gpioa { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-K", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiob { - gpio-line-names = "", "", "", "", - "", "", "", "", - "DHCOM-Q", "", "", "", - "", "", "", ""; -}; - -&gpioc { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-E", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-B", "", - "", "", "", "DHCOM-F", - "DHCOM-D", "", "", ""; -}; - -&gpioe { - gpio-line-names = "", "", "", "", - "", "", "DHCOM-P", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiof { - gpio-line-names = "", "", "", "DHCOM-A", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiog { - gpio-line-names = "DHCOM-C", "", "", "", - "", "", "", "", - "DHCOM-L", "", "", "", - "", "", "", ""; -}; - -&gpioh { - gpio-line-names = "", "", "", "", - "", "", "", "DHCOM-N", - "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U", - "DHCOM-T", "", "DHCOM-S", ""; -}; - -&gpioi { - gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I", - "DHCOM-R", "DHCOM-M", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - hwrtc: rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-always-on; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO1 0>; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = <IT_CURLIM_LDO2 0>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = <IT_CURLIM_LDO4 0>; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO5 0>; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = <IT_CURLIM_LDO6 0>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = <IT_OCP_BOOST 0>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = <IT_OCP_OTG 0>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; - interrupt-names = "onkey-falling", "onkey-rising"; - power-off-time-sec = <10>; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; - - touchscreen@49 { - compatible = "ti,tsc2004"; - reg = <0x49>; - vio-supply = <&v3v3>; - interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; - }; - - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&ipcc { - status = "okay"; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&m4_rproc { - memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; - interrupt-parent = <&exti>; - interrupts = <68 1>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a - &qspi_bk1_pins_a - &qspi_cs1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a - &qspi_bk1_sleep_pins_a - &qspi_cs1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rcc { - /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ - clocks = <&rcc CK_MCO2>; - clock-names = "ETH_RX_CLK/ETH_REF_CLK"; - - /* - * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, - * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, - * so that MCO2 behaves as a divider for the ETHRX clock here. - */ - assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; - assigned-clock-parents = <&rcc PLL4_P>; - assigned-clock-rates = <50000000>, <100000000>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep", "init"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; - pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>; - cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - st,cmd-gpios = <&gpiod 2 0>; - st,ck-gpios = <&gpioc 12 0>; - st,ckin-gpios = <&gpioe 4 0>; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - status = "okay"; -}; - -&sdmmc1_b4_pins_a { - /* - * SD bus pull-up resistors: - * - optional on SoMs with SD voltage translator - * - mandatory on SoMs without SD voltage translator - */ - pins1 { - bias-pull-up; - }; - pins2 { - bias-pull-up; - }; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width = <8>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - mmc-ddr-3_3v; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index d7b78cdcfa9..dd67e960a64 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -8,6 +8,7 @@ #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi" #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi" #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" +#include "stm32mp15xx-dhsom-u-boot.dtsi" / { aliases { diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts deleted file mode 100644 index dd8fcecbca5..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - * Copyright (C) 2020 Marek Vasut <marex@denx.de> - */ - -/dts-v1/; - -#include "stm32mp151.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcor-som.dtsi" -#include "stm32mp15xx-dhcor-avenger96.dtsi" - -/ { - model = "Arrow Electronics STM32MP15xx Avenger96 board"; - compatible = "arrow,stm32mp15xx-avenger96", - "dh,stm32mp15xx-dhcor-som", - "st,stm32mp15x"; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi deleted file mode 100644 index 61e17f44ce8..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ /dev/null @@ -1,437 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - * Copyright (C) 2020 Marek Vasut <marex@denx.de> - */ - -/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ -#include "stm32mp15xx-dhcor-io1v8.dtsi" - -/ { - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - serial2 = &usart2; - spi0 = &qspi; - }; - - /* XTal Q1 */ - cec_clock: clk-cec-fixed { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7513_out>; - }; - }; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user0"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user1"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user2"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; - - sound { - compatible = "audio-graph-card"; - label = "STM32MP1-AV96-HDMI"; - dais = <&sai2a_port>; - status = "okay"; - }; - - wlan_pwr: regulator-wlan { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_b>; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - - adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; - - adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_c>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - - phy0: ethernet-phy@7 { - reg = <7>; - - rxc-skew-ps = <1500>; - rxdv-skew-ps = <540>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - - txc-skew-ps = <1440>; - txen-skew-ps = <540>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <420>; - txd3-skew-ps = <420>; - }; - }; -}; - -&gpioa { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "", "", "AV96-K", - "AV96-I", "", "AV96-A", ""; -}; - -&gpiob { - gpio-line-names = "", "", "", "", - "", "AV96-J", "", "", - "", "", "", "AV96-B", - "", "AV96-L", "", ""; -}; - -&gpioc { - gpio-line-names = "", "", "", "AV96-C", - "", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiod { - gpio-line-names = "", "", "", "", - "", "", "", "", - "AV96-D", "", "", "", - "", "", "AV96-E", "AV96-F"; -}; - -&gpiof { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "", "", "", - "AV96-G", "AV96-H", "", ""; -}; - -&i2c1 { /* X6 I2C1 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { /* X6 I2C2 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_c>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - hdmi-transmitter@3d { - compatible = "adi,adv7513"; - reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; - reg-names = "main", "edid", "cec", "packet"; - clocks = <&cec_clock>; - clock-names = "cec"; - - avdd-supply = <&v3v3>; - dvdd-supply = <&v3v3>; - pvdd-supply = <&v3v3>; - dvdd-3v-supply = <&v3v3>; - bgvdd-supply = <&v3v3>; - - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpiog>; - - status = "okay"; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7513_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - adv7513_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - - port@2 { - reg = <2>; - adv7513_i2s0: endpoint { - remote-endpoint = <&sai2a_endpoint>; - }; - }; - }; - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_d>; - pinctrl-1 = <<dc_sleep_pins_d>; - status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - ltdc_ep0_out: endpoint@0 { - reg = <0>; - remote-endpoint = <&adv7513_in>; - }; - }; -}; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_c>; - pinctrl-1 = <&sai2a_sleep_pins_c>; - clock-names = "pclk", "x8k", "x11k"; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&adv7513_i2s0>; - format = "i2s"; - mclk-fs = <256>; - }; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; - bus-width = <8>; - mmc-ddr-1_8v; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd_io>; - status = "okay"; -}; - -&sdmmc3 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_b>; - pinctrl-1 = <&sdmmc3_b4_od_pins_b>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; - broken-cd; - non-removable; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&wlan_pwr>; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - brcmf: bcrmf@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - cs-gpios = <&gpioi 0 0>; - status = "disabled"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -/* Bluetooth */ -&usart2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usart2_pins_a>; - pinctrl-1 = <&usart2_sleep_pins_a>; - st,hw-flow-ctrl; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - max-speed = <3000000>; - shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - status = "okay"; - vbus-supply = <&vbus_otg>; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts deleted file mode 100644 index c1f99c1685e..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dts +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) 2022 Marek Vasut <marex@denx.de> - */ - -/dts-v1/; - -#include "stm32mp151.dtsi" -#include "stm32mp15xc.dtsi" -#include "stm32mp15xx-dhcor-som.dtsi" -#include "stm32mp15xx-dhcor-drc-compact.dtsi" - -/ { - model = "DH electronics STM32MP15xx DHCOR DRC Compact"; - compatible = "dh,stm32mp15xx-dhcor-drc-compact", - "dh,stm32mp15xx-dhcor-som", - "st,stm32mp1xx"; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi deleted file mode 100644 index bedccf0f00a..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) 2022 Marek Vasut <marex@denx.de> - */ - -/ { - aliases { - ethernet0 = ðernet0; - ethernet1 = &ksz8851; - mmc0 = &sdmmc1; - rtc0 = &hwrtc; - rtc1 = &rtc; - serial0 = &uart4; - serial1 = &uart8; - serial2 = &usart3; - serial3 = &uart5; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "yellow:user0"; - gpios = <&gpioz 6 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led2 { - label = "red:user1"; - gpios = <&gpioz 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpioh 2 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; -}; - -&adc { /* X11 ADC inputs */ - pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_b>; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - - adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; - - adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_c>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - reset-post-delay-us = <1000>; - - phy0: ethernet-phy@7 { - reg = <7>; - - rxc-skew-ps = <1500>; - rxdv-skew-ps = <540>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - - txc-skew-ps = <1440>; - txen-skew-ps = <540>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <420>; - txd3-skew-ps = <420>; - }; - }; -}; - -&fmc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&fmc_pins_b>; - pinctrl-1 = <&fmc_sleep_pins_b>; - status = "okay"; - - ksz8851: ethernet@1,0 { - compatible = "micrel,ks8851-mll"; - reg = <1 0x0 0x2>, <1 0x2 0x20000>; - interrupt-parent = <&gpioc>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - bank-width = <2>; - - /* Timing values are in nS */ - st,fmc2-ebi-cs-mux-enable; - st,fmc2-ebi-cs-transaction-type = <4>; - st,fmc2-ebi-cs-buswidth = <16>; - st,fmc2-ebi-cs-address-setup-ns = <5>; - st,fmc2-ebi-cs-address-hold-ns = <5>; - st,fmc2-ebi-cs-bus-turnaround-ns = <5>; - st,fmc2-ebi-cs-data-setup-ns = <45>; - st,fmc2-ebi-cs-data-hold-ns = <1>; - st,fmc2-ebi-cs-write-address-setup-ns = <5>; - st,fmc2-ebi-cs-write-address-hold-ns = <5>; - st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; - st,fmc2-ebi-cs-write-data-setup-ns = <45>; - st,fmc2-ebi-cs-write-data-hold-ns = <1>; - }; -}; - -&gpioa { - gpio-line-names = "", "", "", "", - "DRCC-VAR2", "", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpioe { - gpio-line-names = "", "", "", "", - "", "DRCC-GPIO0", "", "", - "", "", "", "", - "", "", "", ""; -}; - -&gpiog { - gpio-line-names = "", "", "", "", - "", "", "", "", - "", "", "", "", - "DRCC-GPIO5", "", "", ""; -}; - -&gpioh { - gpio-line-names = "", "", "", "DRCC-HW2", - "DRCC-GPIO4", "", "", "", - "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1", - "DRCC-VAR0", "", "", "DRCC-GPIO6"; -}; - -&gpioi { - gpio-line-names = "", "", "", "", - "", "", "", "DRCC-GPIO2", - "", "DRCC-GPIO1", "", "", - "", "", "", ""; -}; - -&i2c1 { /* X11 I2C1 */ - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - hwrtc: rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&sdmmc1 { /* MicroSD */ - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&vdd>; - vqmmc-supply = <&vdd>; - status = "okay"; -}; - -&sdmmc2 { /* eMMC */ - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&vdd>; - status = "okay"; -}; - -&sdmmc3 { /* SDIO Wi-Fi */ - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc3_b4_pins_a>; - pinctrl-1 = <&sdmmc3_b4_od_pins_a>; - pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; - broken-cd; - bus-width = <4>; - mmc-ddr-3_3v; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - status = "okay"; -}; - -&spi2 { /* X11 SPI */ - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_b>; - cs-gpios = <&gpioi 0 0>; - status = "disabled"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&uart4 { - label = "UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_d>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart5 { /* X11 UART */ - label = "X11-UART5"; - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart8 { - label = "RS485-1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usart3 { /* RS485 or RS232 */ - label = "RS485-2"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&usart3_pins_e>; - pinctrl-1 = <&usart3_sleep_pins_e>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbh_ohci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "otg"; - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - vbus-supply = <&vbus_otg>; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; - connector { - compatible = "usb-a-connector"; - vbus-supply = <&vbus_sw>; - }; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi deleted file mode 100644 index e20917824bf..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - * Copyright (C) 2020 Marek Vasut <marex@denx.de> - */ - -/ { - /* Enpirion EP3A8LQI U2 on the DHCOR */ - vdd_io: regulator-buck-io { - compatible = "regulator-fixed"; - regulator-name = "buck-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd>; - }; -}; - -&vdd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; -}; - -&pwr_regulators { - vdd-supply = <&vdd_io>; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi deleted file mode 100644 index f36eec1b4ac..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) Linaro Ltd 2019 - All Rights Reserved - * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - * Copyright (C) 2020 Marek Vasut <marex@denx.de> - */ - -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mfd/st,stpmic1.h> - -/ { - aliases { - spi0 = &qspi; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x40000000>; - }; -}; - -&crc1 { - status = "okay"; -}; - -&dts { - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO1 0>; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = <IT_CURLIM_LDO2 0>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = <IT_CURLIM_LDO4 0>; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = <IT_CURLIM_LDO5 0>; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = <IT_CURLIM_LDO6 0>; - regulator-enable-ramp-delay = <300000>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = <IT_OCP_BOOST 0>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = <IT_OCP_OTG 0>; - regulator-active-discharge = <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = <IT_OCP_SWOUT 0>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; - - eeprom@53 { - compatible = "atmel,24c02"; - reg = <0x53>; - pagesize = <16>; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&qspi { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a - &qspi_bk1_pins_a - &qspi_cs1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a - &qspi_bk1_sleep_pins_a - &qspi_cs1_sleep_pins_a>; - reg = <0x58003000 0x1000>, <0x70000000 0x200000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts deleted file mode 100644 index 5fdd762ddbf..00000000000 --- a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) -/* - * Copyright (C) 2022 Marek Vasut <marex@denx.de> - */ -/dts-v1/; - -#include "stm32mp151.dtsi" -#include "stm32mp15xx-dhcor-som.dtsi" - -/ { - model = "DH electronics STM32MP15xx DHCOR Testbench"; - compatible = "dh,stm32mp15xx-dhcor-testbench", - "dh,stm32mp15xx-dhcor-som", - "st,stm32mp1xx"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - serial0 = &uart4; - serial1 = &uart7; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - sd_switch: regulator-sd_switch { - compatible = "regulator-gpio"; - regulator-name = "sd_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-type = "voltage"; - regulator-always-on; - - gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; - gpios-states = <0>; - states = <1800000 0x1>, - <2900000 0x0>; - }; -}; - -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc12_ain_pins_b>; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vdda>; - status = "okay"; - - adc1: adc@0 { - st,adc-channels = <0 1 6>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; - - adc2: adc@100 { - st,adc-channels = <0 1 2>; - st,min-sample-time-nsecs = <5000>; - status = "okay"; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_c>; - pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - - phy0: ethernet-phy@7 { - reg = <7>; - - rxc-skew-ps = <1500>; - rxdv-skew-ps = <540>; - rxd0-skew-ps = <420>; - rxd1-skew-ps = <420>; - rxd2-skew-ps = <420>; - rxd3-skew-ps = <420>; - - txc-skew-ps = <1440>; - txen-skew-ps = <540>; - txd0-skew-ps = <420>; - txd1-skew-ps = <420>; - txd2-skew-ps = <420>; - txd3-skew-ps = <420>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - vqmmc-supply = <&sd_switch>; - status = "okay"; -}; - -&sdmmc2 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; - bus-width = <8>; - mmc-ddr-1_8v; - no-sd; - no-sdio; - non-removable; - st,neg-edge; - vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&uart7 { - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - uart-has-rtscts; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - phy-names = "usb"; - status = "okay"; -}; - -&usbotg_hs { - pinctrl-0 = <&usbotg_hs_pins_a>; - pinctrl-names = "default"; - phy-names = "usb2-phy"; - phys = <&usbphyc_port1 0>; - status = "okay"; - vbus-supply = <&vbus_otg>; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; - -&vdd { - /delete-property/ regulator-always-on; - regulator-min-microvolt = <1200000>; -}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index ba84db679e1..08439342cb2 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -12,6 +12,7 @@ #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi" #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi" #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi" +#include "stm32mp15xx-dhsom-u-boot.dtsi" / { bootph-all; diff --git a/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi new file mode 100644 index 00000000000..386c605c07f --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhsom-u-boot.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + */ + +&binman { + u-boot { + filename = "u-boot.itb"; + + fit { + description = "U-Boot mainline"; + fit,fdt-list = "of-list"; + #address-cells = <1>; + + images { + uboot { + arch = "arm"; + compression = "none"; + description = "U-Boot (32-bit)"; + entry = <CONFIG_TEXT_BASE>; + load = <CONFIG_TEXT_BASE>; + type = "standalone"; + + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + + @fdt-SEQ { + compression = "none"; + description = "NAME"; + type = "flat_dt"; + + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + @config-SEQ { + description = "NAME"; + fdt = "fdt-SEQ"; + firmware = "uboot"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sun50i-h313-tanix-tx1.dts b/arch/arm/dts/sun50i-h313-tanix-tx1.dts deleted file mode 100644 index bb2cde59bd0..00000000000 --- a/arch/arm/dts/sun50i-h313-tanix-tx1.dts +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2024 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Tanix TX1"; - compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - ethernet0 = &sdio_wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key { - label = "hidden"; - linux,code = <BTN_0>; - gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 */ - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_BLUE>; - gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - default-state = "on"; - }; - }; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - max-frequency = <100000000>; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL, so needs to be always on. */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1120000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts b/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts deleted file mode 100644 index 4bfb52609c9..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1-manta.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. - */ - -/dts-v1/; - -#include "sun50i-h616-bigtreetech-cb1.dtsi" - -/ { - model = "BigTreeTech CB1"; - compatible = "bigtreetech,cb1-manta", "bigtreetech,cb1", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi deleted file mode 100644 index d12b01c5f41..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - aliases { - ethernet0 = &rtl8189ftv; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - }; - }; - - reg_vcc5v: regulator-vcc5v { - /* board wide 5V supply from carrier boards */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc33_wifi: vcc33-wifi { - compatible = "regulator-fixed"; - regulator-name = "vcc33-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; - - reg_vcc_wifi_io: vcc-wifi-io { - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi-io"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <®_vcc33_wifi>; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc 1>; - clock-names = "ext_clock"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - post-power-on-delay-ms = <200>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&mmc0 { - vmmc-supply = <®_dldo1>; - /* Card detection pin is not connected */ - broken-cd; - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc33_wifi>; - vqmmc-supply = <®_vcc_wifi_io>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - mmc-ddr-1_8v; - status = "okay"; - - rtl8189ftv: wifi@1 { - reg = <1>; - }; -}; - -&r_i2c { - status = "okay"; - - axp313a: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - interrupt-controller; - #interrupt-cells = <1>; - - regulators { - reg_dcdc1: dcdc1 { - regulator-name = "vdd-gpu-sys"; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-always-on; - }; - - reg_dcdc2: dcdc2 { - regulator-name = "vdd-cpu"; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-ramp-delay = <200>; - regulator-always-on; - }; - - reg_dcdc3: dcdc3 { - regulator-name = "vcc-dram"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_aldo1: aldo1 { - regulator-name = "vcc-1v8-pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_dldo1: dldo1 { - regulator-name = "vcc-3v3-io"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts b/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts deleted file mode 100644 index ff84a379447..00000000000 --- a/arch/arm/dts/sun50i-h616-bigtreetech-pi.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Martin Botka <martin@biqu3d.com>. - */ - -/dts-v1/; - -#include "sun50i-h616-bigtreetech-cb1.dtsi" - -/ { - model = "BigTreeTech Pi"; - compatible = "bigtreetech,pi", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi b/arch/arm/dts/sun50i-h616-cpu-opp.dtsi deleted file mode 100644 index aca22a7f019..00000000000 --- a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2023 Martin Botka <martin@somainline.org> - -/ { - cpu_opp_table: opp-table-cpu { - compatible = "allwinner,sun50i-h616-operating-points"; - nvmem-cells = <&cpu_speed_grade>; - opp-shared; - - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x12>; - }; - - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-792000000 { - opp-hz = /bits/ 64 <792000000>; - opp-microvolt-speed1 = <900000>; - opp-microvolt-speed4 = <940000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x12>; - }; - - opp-936000000 { - opp-hz = /bits/ 64 <936000000>; - opp-microvolt = <900000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt-speed0 = <950000>; - opp-microvolt-speed1 = <940000>; - opp-microvolt-speed2 = <950000>; - opp-microvolt-speed3 = <950000>; - opp-microvolt-speed4 = <1020000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-1104000000 { - opp-hz = /bits/ 64 <1104000000>; - opp-microvolt-speed0 = <1000000>; - opp-microvolt-speed2 = <1000000>; - opp-microvolt-speed3 = <1000000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt-speed0 = <1050000>; - opp-microvolt-speed1 = <1020000>; - opp-microvolt-speed2 = <1050000>; - opp-microvolt-speed3 = <1050000>; - opp-microvolt-speed4 = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; - }; - - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1d>; - }; - - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; - }; - - opp-1512000000 { - opp-hz = /bits/ 64 <1512000000>; - opp-microvolt-speed1 = <1100000>; - opp-microvolt-speed3 = <1100000>; - clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0a>; - }; - }; -}; - -&cpu0 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu1 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu2 { - operating-points-v2 = <&cpu_opp_table>; -}; - -&cpu3 { - operating-points-v2 = <&cpu_opp_table>; -}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi deleted file mode 100644 index fc7315b9440..00000000000 --- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Arm Ltd. - * - * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3. - * Excludes PMIC nodes and properties, since they are different between the two. - */ - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_RED>; - gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - default-state = "on"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; - enable-active-high; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - }; -}; - -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on headers only. */ - -&emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-handle = <&ext_rgmii_phy>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts deleted file mode 100644 index a360d8567f9..00000000000 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616-orangepi-zero.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -/ { - model = "OrangePi Zero2"; - compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&emac0 { - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - phy-mode = "rgmii"; - phy-supply = <®_dcdce>; -}; - -&mmc0 { - vmmc-supply = <®_dcdce>; -}; - -&r_rsb { - status = "okay"; - - axp305: pmic@745 { - compatible = "x-powers,axp305", "x-powers,axp805", - "x-powers,axp806"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x745>; - - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-sys"; - }; - - reg_aldo2: aldo2 { /* 3.3V on headers */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext"; - }; - - reg_aldo3: aldo3 { /* 3.3V on headers */ - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext2"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - bldo2 { - /* unused */ - }; - - bldo3 { - /* unused */ - }; - - bldo4 { - /* unused */ - }; - - cldo1 { - /* reserved */ - }; - - cldo2 { - /* unused */ - }; - - cldo3 { - /* unused */ - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-dram"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-eth-mmc"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pf-supply = <®_aldo1>; - vcc-pg-supply = <®_bldo1>; - vcc-ph-supply = <®_aldo1>; - vcc-pi-supply = <®_aldo1>; -}; diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts deleted file mode 100644 index 26d25b5b59e..00000000000 --- a/arch/arm/dts/sun50i-h616-x96-mate.dts +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "X96 Mate"; - compatible = "hechuang,x96-mate", "allwinner,sun50i-h616"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdca>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dcdce>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc2 { - vmmc-supply = <®_dcdce>; - vqmmc-supply = <®_bldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp305: pmic@745 { - compatible = "x-powers,axp305", "x-powers,axp805", - "x-powers,axp806"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x745>; - - x-powers,self-working-mode; - vina-supply = <®_vcc5v>; - vinb-supply = <®_vcc5v>; - vinc-supply = <®_vcc5v>; - vind-supply = <®_vcc5v>; - vine-supply = <®_vcc5v>; - aldoin-supply = <®_vcc5v>; - bldoin-supply = <®_vcc5v>; - cldoin-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-sys"; - }; - - /* Enabled by the Android BSP */ - reg_aldo2: aldo2 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext"; - status = "disabled"; - }; - - /* Enabled by the Android BSP */ - reg_aldo3: aldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3-ext2"; - status = "disabled"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Enabled by the Android BSP */ - reg_bldo2: bldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8-2"; - status = "disabled"; - }; - - bldo3 { - /* unused */ - }; - - bldo4 { - /* unused */ - }; - - cldo1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc2v5"; - }; - - cldo2 { - /* unused */ - }; - - cldo3 { - /* unused */ - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdcc: dcdcc { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vdd-dram"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-eth-mmc"; - }; - - sw { - /* unused */ - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi deleted file mode 100644 index 921d5f61d8d..00000000000 --- a/arch/arm/dts/sun50i-h616.dtsi +++ /dev/null @@ -1,930 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2020 Arm Ltd. -// based on the H6 dtsi, which is: -// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/sun50i-h616-ccu.h> -#include <dt-bindings/clock/sun50i-h6-r-ccu.h> -#include <dt-bindings/clock/sun6i-rtc.h> -#include <dt-bindings/reset/sun50i-h616-ccu.h> -#include <dt-bindings/reset/sun50i-h6-r-ccu.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <1>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <2>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <3>; - enable-method = "psci"; - clocks = <&ccu CLK_CPUX>; - #cooling-cells = <2>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * 256 KiB reserved for Trusted Firmware-A (BL31). - * This is added by BL31 itself, but some bootloaders fail - * to propagate this into the DTB handed to kernels. - */ - secmon@40000000 { - reg = <0x0 0x40000000 0x0 0x40000>; - no-map; - }; - }; - - osc24M: osc24M-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - arm,no-tick-in-suspend; - interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; - - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h616-system-control"; - reg = <0x03000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram_c: sram@28000 { - compatible = "mmio-sram"; - reg = <0x00028000 0x30000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00028000 0x30000>; - }; - }; - - ccu: clock@3001000 { - compatible = "allwinner,sun50i-h616-ccu"; - reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - dma: dma-controller@3002000 { - compatible = "allwinner,sun50i-h616-dma", - "allwinner,sun50i-a100-dma"; - reg = <0x03002000 0x1000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; - clock-names = "bus", "mbus"; - dma-channels = <16>; - dma-requests = <49>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - sid: efuse@3006000 { - compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; - reg = <0x03006000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - ths_calibration: thermal-sensor-calibration@14 { - reg = <0x14 0x8>; - }; - - cpu_speed_grade: cpu-speed-grade@0 { - reg = <0x0 2>; - }; - }; - - watchdog: watchdog@30090a0 { - compatible = "allwinner,sun50i-h616-wdt", - "allwinner,sun6i-a31-wdt"; - reg = <0x030090a0 0x20>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-h616-pinctrl"; - reg = <0x0300b000 0x400>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - ext_rgmii_pins: rgmii-pins { - pins = "PI0", "PI1", "PI2", "PI3", "PI4", - "PI5", "PI7", "PI8", "PI9", "PI10", - "PI11", "PI12", "PI13", "PI14", "PI15", - "PI16"; - function = "emac0"; - drive-strength = <40>; - }; - - i2c0_pins: i2c0-pins { - pins = "PI5", "PI6"; - function = "i2c0"; - }; - - i2c3_ph_pins: i2c3-ph-pins { - pins = "PH4", "PH5"; - function = "i2c3"; - }; - - ir_rx_pin: ir-rx-pin { - pins = "PH10"; - function = "ir_rx"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_pins: mmc2-pins { - pins = "PC0", "PC1", "PC5", "PC6", - "PC8", "PC9", "PC10", "PC11", - "PC13", "PC14", "PC15", "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - spi0_pins: spi0-pins { - pins = "PC0", "PC2", "PC4"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi0_cs0_pin: spi0-cs0-pin { - pins = "PC3"; - function = "spi0"; - }; - - /omit-if-no-ref/ - spi1_pins: spi1-pins { - pins = "PH6", "PH7", "PH8"; - function = "spi1"; - }; - - /omit-if-no-ref/ - spi1_cs0_pin: spi1-cs0-pin { - pins = "PH5"; - function = "spi1"; - }; - - spdif_tx_pin: spdif-tx-pin { - pins = "PH4"; - function = "spdif"; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH0", "PH1"; - function = "uart0"; - }; - - /omit-if-no-ref/ - uart1_pins: uart1-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart1_rts_cts_pins: uart1-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - /omit-if-no-ref/ - x32clk_fanout_pin: x32clk-fanout-pin { - pins = "PG10"; - function = "clock"; - }; - }; - - gic: interrupt-controller@3021000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - mmc0: mmc@4020000 { - compatible = "allwinner,sun50i-h616-mmc", - "allwinner,sun50i-a100-mmc"; - reg = <0x04020000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@4021000 { - compatible = "allwinner,sun50i-h616-mmc", - "allwinner,sun50i-a100-mmc"; - reg = <0x04021000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@4022000 { - compatible = "allwinner,sun50i-h616-emmc", - "allwinner,sun50i-a100-emmc"; - reg = <0x04022000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - status = "disabled"; - max-frequency = <150000000>; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-3_3v; - cap-sdio-irq; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@5000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000000 0x400>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - dmas = <&dma 14>, <&dma 14>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@5000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000400 0x400>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@5000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000800 0x400>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - dmas = <&dma 16>, <&dma 16>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@5000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x05000c00 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - dmas = <&dma 17>, <&dma 17>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@5001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x05001000 0x400>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - dmas = <&dma 18>, <&dma 18>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - uart5: serial@5001400 { - compatible = "snps,dw-apb-uart"; - reg = <0x05001400 0x400>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART5>; - dmas = <&dma 19>, <&dma 19>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART5>; - status = "disabled"; - }; - - i2c0: i2c@5002000 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002000 0x400>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C0>; - dmas = <&dma 43>, <&dma 43>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@5002400 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002400 0x400>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C1>; - dmas = <&dma 44>, <&dma 44>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@5002800 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002800 0x400>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C2>; - dmas = <&dma 45>, <&dma 45>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@5002c00 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05002c00 0x400>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C3>; - dmas = <&dma 46>, <&dma 46>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@5003000 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x05003000 0x400>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C4>; - dmas = <&dma 47>, <&dma 47>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_I2C4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@5010000 { - compatible = "allwinner,sun50i-h616-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x05010000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@5011000 { - compatible = "allwinner,sun50i-h616-spi", - "allwinner,sun8i-h3-spi"; - reg = <0x05011000 0x1000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac0: ethernet@5020000 { - compatible = "allwinner,sun50i-h616-emac0", - "allwinner,sun50i-a64-emac"; - reg = <0x05020000 0x10000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_EMAC0>; - clock-names = "stmmaceth"; - resets = <&ccu RST_BUS_EMAC0>; - reset-names = "stmmaceth"; - syscon = <&syscon>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - spdif: spdif@5093000 { - compatible = "allwinner,sun50i-h616-spdif"; - reg = <0x05093000 0x400>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; - clock-names = "apb", "spdif"; - resets = <&ccu RST_BUS_SPDIF>; - dmas = <&dma 2>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx_pin>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - ths: thermal-sensor@5070400 { - compatible = "allwinner,sun50i-h616-ths"; - reg = <0x05070400 0x400>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_THS>; - clock-names = "bus"; - resets = <&ccu RST_BUS_THS>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - allwinner,sram = <&syscon>; - #thermal-sensor-cells = <1>; - }; - - usbotg: usb@5100000 { - compatible = "allwinner,sun50i-h616-musb", - "allwinner,sun8i-h3-musb"; - reg = <0x05100000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@5100400 { - compatible = "allwinner,sun50i-h616-usb-phy"; - reg = <0x05100400 0x24>, - <0x05101800 0x14>, - <0x05200800 0x14>, - <0x05310800 0x14>, - <0x05311800 0x14>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>, - <&ccu CLK_BUS_EHCI2>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy", - "pmu2_clk"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@5101000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05101000 0x100>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@5101400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05101400 0x100>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@5200000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05200000 0x100>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_BUS_EHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>, - <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@5200400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05200400 0x100>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@5310000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05310000 0x100>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_BUS_EHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>, - <&ccu RST_BUS_EHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@5310400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05310400 0x100>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@5311000 { - compatible = "allwinner,sun50i-h616-ehci", - "generic-ehci"; - reg = <0x05311000 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_BUS_EHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>, - <&ccu RST_BUS_EHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@5311400 { - compatible = "allwinner,sun50i-h616-ohci", - "generic-ohci"; - reg = <0x05311400 0x100>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - rtc: rtc@7000000 { - compatible = "allwinner,sun50i-h616-rtc"; - reg = <0x07000000 0x400>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, - <&ccu CLK_PLL_SYSTEM_32K>; - clock-names = "bus", "hosc", - "pll-32k"; - #clock-cells = <1>; - }; - - r_ccu: clock@7010000 { - compatible = "allwinner,sun50i-h616-r-ccu"; - reg = <0x07010000 0x210>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, - <&ccu CLK_PLL_PERIPH0>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - nmi_intc: interrupt-controller@7010320 { - compatible = "allwinner,sun50i-h616-nmi", - "allwinner,sun9i-a80-nmi"; - reg = <0x07010320 0xc>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - }; - - r_pio: pinctrl@7022000 { - compatible = "allwinner,sun50i-h616-r-pinctrl"; - reg = <0x07022000 0x400>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - - /omit-if-no-ref/ - r_i2c_pins: r-i2c-pins { - pins = "PL0", "PL1"; - function = "s_i2c"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PL0", "PL1"; - function = "s_rsb"; - }; - }; - - ir: ir@7040000 { - compatible = "allwinner,sun50i-h616-ir", - "allwinner,sun6i-a31-ir"; - reg = <0x07040000 0x400>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1_IR>, - <&r_ccu CLK_IR>; - clock-names = "apb", "ir"; - resets = <&r_ccu RST_R_APB1_IR>; - pinctrl-names = "default"; - pinctrl-0 = <&ir_rx_pin>; - status = "disabled"; - }; - - r_i2c: i2c@7081400 { - compatible = "allwinner,sun50i-h616-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x07081400 0x400>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB2_I2C>; - dmas = <&dma 48>, <&dma 48>; - dma-names = "rx", "tx"; - resets = <&r_ccu RST_R_APB2_I2C>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_rsb: rsb@7083000 { - compatible = "allwinner,sun50i-h616-rsb", - "allwinner,sun8i-a23-rsb"; - reg = <0x07083000 0x400>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB2_RSB>; - clock-frequency = <3000000>; - resets = <&r_ccu RST_R_APB2_RSB>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <500>; - polling-delay = <1000>; - thermal-sensors = <&ths 2>; - sustainable-power = <1000>; - - trips { - cpu_threshold: cpu-trip-0 { - temperature = <60000>; - type = "passive"; - hysteresis = <0>; - }; - cpu_target: cpu-trip-1 { - temperature = <70000>; - type = "passive"; - hysteresis = <0>; - }; - cpu_critical: cpu-trip-2 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <500>; - polling-delay = <1000>; - thermal-sensors = <&ths 0>; - sustainable-power = <1100>; - - trips { - gpu_temp_critical: gpu-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - ve-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 1>; - - trips { - ve_temp_critical: ve-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - - ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&ths 3>; - - trips { - ddr_temp_critical: ddr-trip-0 { - temperature = <110000>; - type = "critical"; - hysteresis = <0>; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi b/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi deleted file mode 100644 index e92d150aaf1..00000000000 --- a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) Jisheng Zhang <jszhang@kernel.org> - */ - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8-pll"; - }; - - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-io"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; diff --git a/arch/arm/dts/sun50i-h618-longanpi-3h.dts b/arch/arm/dts/sun50i-h618-longanpi-3h.dts deleted file mode 100644 index 18b29c6b867..00000000000 --- a/arch/arm/dts/sun50i-h618-longanpi-3h.dts +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) Jisheng Zhang <jszhang@kernel.org> - */ - -/dts-v1/; - -#include "sun50i-h618-longan-module-3h.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Sipeed Longan Pi 3H"; - compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618"; - - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - color = <LED_COLOR_ID_ORANGE>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <0>; - gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ - }; - - led-1 { - color = <LED_COLOR_ID_ORANGE>; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - gpios = <&pio 6 4 GPIO_ACTIVE_LOW>; /* PG4 */ - }; - }; - - reg_vcc5v: regulator-vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <®_vcc5v>; - }; -}; - -&axp313 { - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&ehci2 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -/* WiFi & BT combo module is connected to this Host */ -&ehci3 { - status = "okay"; -}; - -&ohci3 { - status = "okay"; -}; - -&emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - phy-supply = <®_vcc3v3>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&mmc0 { - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v>; - usb2_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts b/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts deleted file mode 100644 index 6a4f0da9723..00000000000 --- a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "OrangePi Zero 2W"; - compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: vcc3v3 { - /* SY8089 DC/DC converter */ - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_vcc5v>; - regulator-always-on; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on the FPC connector (or the exansion board) */ - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; /* internally via VCC-IO */ - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; /* internally via VCC-IO */ - vcc-pi-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL and DRAM */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_vcc5v>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts deleted file mode 100644 index e1cd7572a14..00000000000 --- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616-orangepi-zero.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -/ { - model = "OrangePi Zero3"; - compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&emac0 { - allwinner,tx-delay-ps = <700>; - phy-mode = "rgmii-rxid"; - phy-supply = <®_dldo1>; -}; - -&ext_rgmii_phy { - motorcomm,clk-out-frequency-hz = <125000000>; -}; - -&mmc0 { - /* - * The schematic shows the card detect pin wired up to PF6, via an - * inverter, but it just doesn't work. - */ - broken-cd; - vmmc-supply = <®_dldo1>; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - /* Supplies VCC-PLL, so needs to be always on. */ - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8"; - }; - - /* Supplies VCC-IO, so needs to be always on. */ - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_dldo1>; - vcc-pf-supply = <®_dldo1>; - vcc-pg-supply = <®_aldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; diff --git a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts b/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts deleted file mode 100644 index d6631bfe629..00000000000 --- a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Arm Ltd. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" -#include "sun50i-h616-cpu-opp.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Transpeed 8K618-T"; - compatible = "transpeed,8k618-t", "allwinner,sun50i-h618"; - - aliases { - ethernet1 = &sdio_wifi; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the DC input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_vcc3v3: vcc3v3 { - /* discrete 3.3V regulator */ - compatible = "regulator-fixed"; - regulator-name = "vcc-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&ir { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_dldo1>; - cd-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>; /* PI16 */ - bus-width = <4>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - }; -}; - -&mmc2 { - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_aldo1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&r_i2c { - status = "okay"; - - axp313: pmic@36 { - compatible = "x-powers,axp313a"; - reg = <0x36>; - #interrupt-cells = <1>; - interrupt-controller; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - - regulators { - reg_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-1v8-pll"; - }; - - reg_dldo1: dldo1 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3-io-mmc"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <990000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1360000>; - regulator-max-microvolt = <1360000>; - regulator-name = "vdd-dram"; - }; - }; - }; -}; - -&pio { - vcc-pc-supply = <®_aldo1>; - vcc-pg-supply = <®_dldo1>; - vcc-ph-supply = <®_dldo1>; - vcc-pi-supply = <®_dldo1>; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg { - dr_mode = "host"; /* USB A type receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts deleted file mode 100644 index ee30584b6ad..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - */ - -/dts-v1/; - -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/linux-event-codes.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> - -/ { - model = "Anbernic RG35XX 2024"; - chassis-type = "handset"; - compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys_gamepad: gpio-keys-gamepad { - compatible = "gpio-keys"; - - button-a { - label = "Action-Pad A"; - gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_EAST>; - }; - - button-b { - label = "Action-Pad B"; - gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_SOUTH>; - }; - - button-down { - label = "D-Pad Down"; - gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_DOWN>; - }; - - button-l1 { - label = "Key L1"; - gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TL>; - }; - - button-l2 { - label = "Key L2"; - gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TL2>; - }; - - button-left { - label = "D-Pad left"; - gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_LEFT>; - }; - - button-menu { - label = "Key Menu"; - gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_MODE>; - }; - - button-r1 { - label = "Key R1"; - gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TR>; - }; - - button-r2 { - label = "Key R2"; - gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_TR2>; - }; - - button-right { - label = "D-Pad Right"; - gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_RIGHT>; - }; - - button-select { - label = "Key Select"; - gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_SELECT>; - }; - button-start { - label = "Key Start"; - gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_START>; - }; - - button-up { - label = "D-Pad Up"; - gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_DPAD_UP>; - }; - - button-x { - label = "Action-Pad X"; - gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_NORTH>; - }; - - button-y { - label = "Action Pad Y"; - gpios = <&pio 0 2 GPIO_ACTIVE_LOW>; /* PA2 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_WEST>; - }; - }; - - gpio-keys-volume { - compatible = "gpio-keys"; - autorepeat; - - button-vol-up { - label = "Key Volume Up"; - gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; /* PE1 */ - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; - }; - - button-vol-down { - label = "Key Volume Down"; - gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PE2 */ - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ - default-state = "on"; - }; - }; - - reg_vcc5v: regulator-vcc5v { /* USB-C power input */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc1>; -}; - -&ehci0 { - status = "okay"; -}; - -&mmc0 { - vmmc-supply = <®_cldo3>; - disable-wp; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci0 { - status = "okay"; -}; - -&pio { - vcc-pa-supply = <®_cldo3>; - vcc-pc-supply = <®_cldo3>; - vcc-pe-supply = <®_cldo3>; - vcc-pf-supply = <®_cldo3>; - vcc-pg-supply = <®_aldo4>; - vcc-ph-supply = <®_cldo3>; - vcc-pi-supply = <®_cldo3>; -}; - -&r_rsb { - status = "okay"; - - axp717: pmic@3a3 { - compatible = "x-powers,axp717"; - reg = <0x3a3>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - vin1-supply = <®_vcc5v>; - vin2-supply = <®_vcc5v>; - vin3-supply = <®_vcc5v>; - vin4-supply = <®_vcc5v>; - - regulators { - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpu"; - }; - - reg_dcdc2: dcdc2 { - regulator-always-on; - regulator-min-microvolt = <940000>; - regulator-max-microvolt = <940000>; - regulator-name = "vdd-gpu-sys"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-dram"; - }; - - reg_aldo1: aldo1 { - /* 1.8v - unused */ - }; - - reg_aldo2: aldo2 { - /* 1.8v - unused */ - }; - - reg_aldo3: aldo3 { - /* 1.8v - unused */ - }; - - reg_aldo4: aldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pg"; - }; - - reg_bldo1: bldo1 { - /* 1.8v - unused */ - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pll"; - }; - - reg_bldo3: bldo3 { - /* 2.8v - unused */ - }; - - reg_bldo4: bldo4 { - /* 1.2v - unused */ - }; - - reg_cldo1: cldo1 { - /* 3.3v - audio codec - not yet implemented */ - }; - - reg_cldo2: cldo2 { - /* 3.3v - unused */ - }; - - reg_cldo3: cldo3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-io"; - }; - - reg_cldo4: cldo4 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_boost: boost { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5200000>; - regulator-name = "boost"; - }; - - reg_cpusldo: cpusldo { - /* unused */ - }; - }; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */ -&usbotg { - dr_mode = "peripheral"; /* USB type-C receptable */ - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts deleted file mode 100644 index 63036256917..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - * Copyright (C) 2024 Chris Morgan <macroalpha82@gmail.com>. - */ - -#include "sun50i-h700-anbernic-rg35xx-plus.dts" - -/ { - model = "Anbernic RG35XX H"; - compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; -}; - -&gpio_keys_gamepad { - button-thumbl { - label = "GPIO Thumb Left"; - gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_THUMBL>; - }; - - button-thumbr { - label = "GPIO Thumb Right"; - gpios = <&pio 4 9 GPIO_ACTIVE_LOW>; /* PE9 */ - linux,input-type = <EV_KEY>; - linux,code = <BTN_THUMBR>; - }; -}; - -&ehci1 { - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts deleted file mode 100644 index 60a8e492210..00000000000 --- a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. - */ - -#include "sun50i-h700-anbernic-rg35xx-2024.dts" - -/ { - model = "Anbernic RG35XX Plus"; - compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700"; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&rtc CLK_OSC32K_FANOUT>; - clock-names = "ext_clock"; - pinctrl-0 = <&x32clk_fanout_pin>; - pinctrl-names = "default"; - post-power-on-delay-ms = <200>; - reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ - }; -}; - -/* SDIO WiFi RTL8821CS */ -&mmc1 { - vmmc-supply = <®_cldo4>; - vqmmc-supply = <®_aldo4>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; - - sdio_wifi: wifi@1 { - reg = <1>; - interrupt-parent = <&pio>; - interrupts = <6 15 IRQ_TYPE_LEVEL_LOW>; /* PG15 */ - interrupt-names = "host-wake"; - }; -}; - -/* Bluetooth RTL8821CS */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; - device-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */ - enable-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>; /* PG19 */ - host-wake-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16 */ - }; -}; diff --git a/arch/arm/dts/tegra-u-boot.dtsi b/arch/arm/dts/tegra-u-boot.dtsi index b3d0dec7757..c200f2d3a0b 100644 --- a/arch/arm/dts/tegra-u-boot.dtsi +++ b/arch/arm/dts/tegra-u-boot.dtsi @@ -19,6 +19,27 @@ }; }; +#ifdef CONFIG_MULTI_DTB_FIT + image2 { + filename = "u-boot-dtb-tegra.bin"; + pad-byte = <0xff>; + u-boot-spl { + }; + u-boot-nodtb { + offset = <(U_BOOT_OFFSET)>; + }; + fit-dtb { +#ifdef CONFIG_MULTI_DTB_FIT_LZO + filename = "fit-dtb.blob.lzo"; +#elif CONFIG_MULTI_DTB_FIT_GZIP + filename = "fit-dtb.blob.gz"; +#else + filename = "fit-dtb.blob"; +#endif + type = "blob"; + }; + }; +#else /* Same as image1 - some tools still expect the -dtb suffix */ image2 { filename = "u-boot-dtb-tegra.bin"; @@ -29,6 +50,7 @@ offset = <(U_BOOT_OFFSET)>; }; }; +#endif image3 { filename = "u-boot-nodtb-tegra.bin"; diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index b98ed16bc5f..179060c56ee 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -40,6 +40,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index e6a5c2b699e..ffcc3334529 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -40,6 +40,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/versal-net-mini-emmc.dts b/arch/arm/dts/versal-net-mini-emmc.dts index e200fb694c6..20e4e299404 100644 --- a/arch/arm/dts/versal-net-mini-emmc.dts +++ b/arch/arm/dts/versal-net-mini-emmc.dts @@ -54,6 +54,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0 0xf1050000 0 0x10000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/versal-net-mini.dts b/arch/arm/dts/versal-net-mini.dts index 9365efbe9fe..f98f95a5c2f 100644 --- a/arch/arm/dts/versal-net-mini.dts +++ b/arch/arm/dts/versal-net-mini.dts @@ -60,7 +60,6 @@ clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; - current-speed = <115200>; skip-init; }; }; diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index 8d007378033..8031488d17a 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -83,6 +83,9 @@ bootph-all; status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */ non-removable; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <4>; }; diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts index 96d2937de8b..a8f345032ea 100644 --- a/arch/arm/dts/zynq-minized.dts +++ b/arch/arm/dts/zynq-minized.dts @@ -92,6 +92,9 @@ &sdhci1 { status = "okay"; non-removable; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <4>; max-frequency = <12000000>; diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 293d8e97b63..d540f334f51 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -60,6 +60,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index c439f778ca4..6ef8b1462eb 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -68,6 +68,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index d6cd193a449..c597adb80cb 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -88,6 +88,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 902fdd4de6c..eefe5ab61e7 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -84,6 +84,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index f3994bca4a0..7ea4eab6a37 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -84,6 +84,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index cf2219797a5..ad4b3c5f8b1 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -52,6 +52,9 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; non-removable; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 4c9f56a8076..fd421b4fe7e 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -52,6 +52,9 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; non-removable; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index ae52e8e996a..fce0d8d5ca1 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -60,6 +60,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; @@ -155,7 +158,7 @@ reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; @@ -163,15 +166,15 @@ /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ @@ -212,75 +215,75 @@ reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1f>; }; }; diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 1fcb5bfb928..1af3f643567 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -288,6 +288,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso new file mode 100644 index 00000000000..8412aecd726 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso @@ -0,0 +1,400 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VM-P-M1369-00 + * + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sc-vm-p-m1369-revA", + "xlnx,zynqmp-sc-vm-p-m1369", "xlnx,zynqmp"; + + ina226-u19 { + compatible = "iio-hwmon"; + io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>; + }; + ina226-u287 { + compatible = "iio-hwmon"; + io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; + }; + ina226-u288 { + compatible = "iio-hwmon"; + io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>; + }; + ina226-u289 { + compatible = "iio-hwmon"; + io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; + }; + ina226-u290 { + compatible = "iio-hwmon"; + io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>; + }; + ina226-u291 { + compatible = "iio-hwmon"; + io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; + }; + ina226-u292 { + compatible = "iio-hwmon"; + io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; + }; + ina226-u293 { + compatible = "iio-hwmon"; + io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; + }; + ina226-u294 { + compatible = "iio-hwmon"; + io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; + }; + ina226-u295 { + compatible = "iio-hwmon"; + io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>; + }; + ina226-u298 { + compatible = "iio-hwmon"; + io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>; + }; + ina226-u296 { + compatible = "iio-hwmon"; + io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>; + }; + ina226-u299 { + compatible = "iio-hwmon"; + io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; + }; + ina226-u300 { + compatible = "iio-hwmon"; + io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; + }; + ina226-u301 { + compatible = "iio-hwmon"; + io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; + }; + ina226-u297 { + compatible = "iio-hwmon"; + io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>; + }; +}; + +&i2c1 { /* i2c_main bus */ + #address-cells = <1>; + #size-cells = <0>; + + /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */ + + /* i2c_main_1 - u72 - j108 - disable translation, add 8 */ + /* J133 - OE for u91@55 + 8 - 161,132813MHz - QSFP56G_0 */ + qsfp56g_0_clk: clock-controller@5d { + compatible = "renesas,proxo-xp"; + reg = <0x5d>; + #clock-cells = <0>; + clock-output-names = "qsfp56g_0_clk"; + }; + + /* J134 - OE for u92@57 + 8 - 322,265625MHz - QSFP56G_1 */ + qsfp56g_1_clk: clock-controller@5f { + compatible = "renesas,proxo-xp"; + reg = <0x5f>; + #clock-cells = <0>; + clock-output-names = "qsfp56g_1_clk"; + }; + + /* i2c_main_2 - u74 - j110 - disable translation, add 9 */ + /* J210 - OE for u164@50 + 9 - 320MHz - CH2_LP5 */ + ch2_lpddr5_refclk: clock-controller@59 { + compatible = "renesas,proxo-xp"; + reg = <0x59>; + #clock-cells = <0>; + clock-output-names = "ch2_lpddr5_refclk"; + }; + + /* i2c_main_3 - u76 - j112 - disable translation, add 6 */ + /* J231 - OE for u165@50 + 6 - 320MHz - _RDIMM */ + ddr5_dimm1_refclk: clock-controller@56 { + compatible = "renesas,proxo-xp"; + reg = <0x56>; + #clock-cells = <0>; + clock-output-names = "ddr5_udimm_refclk"; + }; + + /* i2c_main_4 - u73 - j109 - disable translation, add 5 */ + /* J117 - OE for u82@50 + 5 - 33,3333MHz - PS_REFCLK */ + ps_refclk: clock-controller@55 { + compatible = "renesas,proxo-xp"; + reg = <0x55>; + #clock-cells = <0>; + clock-output-names = "ps_refclk"; + }; + + /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */ + /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */ + /* this should be SW controlable too */ +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + /* u134 tps544b25 but connected to J178 connector */ + /* u48/IMx3112/0x77 - 1:2 multiplexer - also accessed from Versal NET */ + /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */ + /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */ + /* Access to i2c_pmc bus via u49 with OE j100 or via SYSCTLR_I2C_PMC_EN */ + + /* ina226_pmbus - J103 - disable INA226_PMBUS */ + vcc_soc_ina: power-monitor@40 { /* u19 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x40>; + shunt-resistor = <1000>; /* R222 */ + }; + + vcc_ram_ina: power-monitor@41 { /* u287 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x41>; + shunt-resistor = <1000>; /* R32981 */ + }; + + vcc_pslp_ina: power-monitor@42 { /* u288 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x42>; + shunt-resistor = <1000>; /* R32984 */ + }; + + vccaux_ina: power-monitor@43 { /* u289 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x43>; + shunt-resistor = <1000>; /* R32987 */ + }; + + vccaux_pmc_ina: power-monitor@44 { /* u290 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x44>; + shunt-resistor = <1000>; /* R32990 */ + }; + + vcco_500_ina: power-monitor@45 { /* u291 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x45>; + shunt-resistor = <1000>; /* R32993 */ + }; + + vcco_501_ina: power-monitor@46 { /* u292 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x46>; + shunt-resistor = <1000>; /* R32996 */ + }; + + vcco_502_ina: power-monitor@47 { /* u293 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x47>; + shunt-resistor = <1000>; /* R32999 */ + }; + + vcco_503_ina: power-monitor@48 { /* u294 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x48>; + shunt-resistor = <1000>; /* R33002 */ + }; + + vcc_ddr5_rdimm_ina: power-monitor@49 { /* u295 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x49>; + shunt-resistor = <1000>; /* R33005 */ + }; + + lp5_1v0_ina: power-monitor@4a { /* u298 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4a>; + shunt-resistor = <1000>; /* R33014 */ + }; + + vcc_fmc_ina: power-monitor@4b { /* u296 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4b>; + shunt-resistor = <1000>; /* R33008 */ + }; + + gtm_avcc_ina: power-monitor@4c { /* u299 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4c>; + shunt-resistor = <1000>; /* R33017 */ + }; + + gtm_avtt_ina: power-monitor@4d { /* u300 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4d>; + shunt-resistor = <1000>; /* R33020 */ + }; + + gtm_avccaux_ina: power-monitor@4e { /* u301 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4e>; + shunt-resistor = <1000>; /* R33023 */ + }; + + vcc_mipi_ina: power-monitor@4f { /* u297 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4f>; + shunt-resistor = <1000>; /* R33011 */ + }; + + /* pmbus - j105 - disable main PMBUS - also going to j102 connector */ + vcc_pslp: regulator@15 { /* u24 */ + compatible = "ti,tps546b24a"; + reg = <0x15>; + }; + + vccaux_pmc: regulator@17 { /* u26 */ + compatible = "ti,tps546b24a"; + reg = <0x17>; + }; + + vcco_500: regulator@18 { /* u27 */ + compatible = "ti,tps546b24a"; + reg = <0x18>; + }; + + vcco_501: regulator@19 { /* u28 */ + compatible = "ti,tps546b24a"; + reg = <0x19>; + }; + + vcco_502: regulator@1a { /* u29 */ + compatible = "ti,tps546b24a"; + reg = <0x1a>; + }; + + vcco_503: regulator@1b { /* u30 */ + compatible = "ti,tps546b24a"; + reg = <0x1b>; + }; + + vcc_ddr5_rdimm: regulator@1c { /* u31 */ + compatible = "ti,tps546b24a"; + reg = <0x1c>; + }; + + gtm_avcc: regulator@22 { /* u37 */ + compatible = "ti,tps546b24a"; + reg = <0x22>; + }; + + gtm_avtt: regulator@20 { /* u38 */ + compatible = "ti,tps546b24a"; + reg = <0x20>; + }; + + gtm_avccaux: regulator@21 { /* u39 */ + compatible = "ti,tps546b24a"; + reg = <0x21>; + }; + + vccint_gt: regulator@2a { /* u44 */ + compatible = "ti,tps546b24a"; + reg = <0x2a>; + }; + + util_1v8: regulator@2b { /* u1839 */ + compatible = "ti,tps546b24a"; + reg = <0x2b>; + }; + + vcc_pmc: regulator@2c { /* u46 */ + compatible = "ti,tps546b24a"; + reg = <0x2c>; + }; + + /* pmbus via U62 as ext_pmbus - disable via j104 */ + vccint: regulator@10 { /* u18 */ + compatible = "ti,tps546b24"; + reg = <0x10>; + }; + + vccsoc: regulator@11 { /* u20 */ + compatible = "ti,tps546b24"; + reg = <0x11>; + }; + + vcc_io: regulator@12 { /* u21 */ + compatible = "ti,tps546b24"; + reg = <0x12>; + }; + + vcc_psfp: regulator@13 { /* u22 */ + compatible = "ti,tps546b24"; + reg = <0x13>; + }; + + vcc_ram: regulator@14 { /* u23 */ + compatible = "ti,tps546b24"; + reg = <0x14>; + }; + + vccaux: regulator@16 { /* u25 */ + compatible = "ti,tps546b24"; + reg = <0x16>; + }; + + lp5_1v0: regulator@1d { /* u32 */ + compatible = "ti,tps546b24"; + reg = <0x1d>; + }; + + vcc_fmc: regulator@1e { /* u33 */ + compatible = "ti,tps546b24"; + reg = <0x1e>; + }; + + lp5_vdd1: regulator@25 { /* u40 */ + compatible = "ti,tps546b24"; + reg = <0x25>; + }; + + lp5_vdd2: regulator@26 { /* u41 */ + compatible = "ti,tps546b24"; + reg = <0x26>; + }; + + lp5_vddq: regulator@27 { /* u42 */ + compatible = "ti,tps546b24"; + reg = <0x27>; + }; + + vcco_hdio: regulator@29 { /* u43 */ + compatible = "ti,tps546b24"; + reg = <0x29>; + }; + + vcc_mipi: regulator@1f { /* u47 */ + compatible = "ti,tps546b24"; + reg = <0x1f>; + }; + + /* connected via J425 connector + ucd90320: power-sequencer@73 { // u16 + compatible = "ti,ucd90320"; + reg = <0x73>; + };*/ +}; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index d95a05e2159..8056f6b176e 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -247,6 +247,9 @@ pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 0d96c6f9f04..2037686b9b4 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -93,6 +93,9 @@ status = "okay"; non-removable; disable-wp; /* We don't have a write-protect detection */ + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index 4768fac71d0..f281c7fb9fd 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -105,6 +105,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index c5945067cd5..c9051360931 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -509,6 +509,9 @@ xlnx,mio-bank = <0>; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index d5f63f4a7ed..22671d4bbfd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -12,13 +12,13 @@ #include <asm/armv8/sec_firmware.h> struct icid_id_table { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD const char *compat; phys_addr_t compat_addr; #endif phys_addr_t reg_addr; u32 reg; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD u32 id; #endif bool le; @@ -35,7 +35,7 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void); void fdt_fixup_icid(void *blob); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ { .reg = regA, \ .reg_addr = addr, \ diff --git a/arch/arm/include/asm/arch-imx8/boot0.h b/arch/arm/include/asm/arch-imx8/boot0.h index 5ce781adb75..fc580b20a46 100644 --- a/arch/arm/include/asm/arch-imx8/boot0.h +++ b/arch/arm/include/asm/arch-imx8/boot0.h @@ -3,7 +3,7 @@ * Copyright 2019 NXP */ -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) /* * We use absolute address not PC relative address to jump. * When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000, diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 4675dc3c533..b499d975526 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -16,7 +16,7 @@ void lpc32xx_slc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); void lpc32xx_ssp_init(void); void lpc32xx_usb_init(void); -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) void ddr_init(const struct emc_dram_settings *dram); #endif #endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-mx6/litesom.h b/arch/arm/include/asm/arch-mx6/litesom.h index 37a16d2c309..642ed22bffc 100644 --- a/arch/arm/include/asm/arch-mx6/litesom.h +++ b/arch/arm/include/asm/arch-mx6/litesom.h @@ -8,7 +8,7 @@ int litesom_mmc_init(struct bd_info *bis); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void litesom_init_f(void); #endif diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index dbc97b25df8..ad9c1ac906a 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -5,7 +5,7 @@ #ifndef __ASM_ARCH_MX6_DDR_H__ #define __ASM_ARCH_MX6_DDR_H__ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #ifdef CONFIG_MX6Q #include "mx6q-ddr.h" #else @@ -488,7 +488,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, const struct mx6_mmdc_calibration *, const void *); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define MX6_MMDC_P0_MDCTL 0x021b0000 #define MX6_MMDC_P0_MDPDC 0x021b0004 diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 17afd1b29e4..f8a56495acd 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -14,7 +14,7 @@ int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int), int (*cd)(int)); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if defined(CONFIG_MX23) #include <asm/arch/iomux-mx23.h> diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h index 6bf3828c84e..eaf81554f5b 100644 --- a/arch/arm/include/asm/arch-rk3066/boot0.h +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -10,7 +10,7 @@ * (containing the magic 'RK30'). This magic constant will be written into * the final image by the rkimage tool, but we need to reserve space for it here. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD b 1f /* if overwritten, entry-address is at the next word */ 1: #endif @@ -68,7 +68,7 @@ back_to_bootrom: pop {r1-r12, pc} #endif -#if (defined(CONFIG_SPL_BUILD)) +#if (defined(CONFIG_XPL_BUILD)) /* U-Boot proper of armv7 does not need this */ b reset #endif diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 0c375e543a5..edb2a31c348 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -12,7 +12,7 @@ * To make life easier for everyone, we build the SPL binary with * space for this 4-byte header already included in the binary. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * We need to add 4 bytes of space for the 'RK33' at the * beginning of the executable. However, as we want to keep @@ -39,7 +39,7 @@ entry_counter: .word 0 #endif -#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64)) +#if (defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARM64)) /* U-Boot proper of armv7 do not need this */ b reset #endif @@ -54,7 +54,7 @@ _start: ARM_VECTORS #endif -#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \ +#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_XPL_BUILD) && \ (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h index b66277fc7f3..504459bd93d 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_px30.h +++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h @@ -464,5 +464,12 @@ enum { UART0_CLK_SEL_UART0_FRAC, UART0_DIVNP5_SHIFT = 0, UART0_DIVNP5_MASK = 0x1f << UART0_DIVNP5_SHIFT, + + /* CRU_PMU_CLKSEL5_CON */ + CLK_UART_FRAC_NUMERATOR_SHIFT = 16, + CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << CLK_UART_FRAC_NUMERATOR_SHIFT, + CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, + CLK_UART_FRAC_DENOMINATOR_MASK = + 0xffff << CLK_UART_FRAC_DENOMINATOR_SHIFT, }; #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h index 49a1f763795..ae273de3144 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h @@ -11,7 +11,7 @@ #define KHz 1000 #define OSC_HZ (24 * MHz) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define APLL_HZ (1008 * MHz) #else #define APLL_HZ (816 * MHz) @@ -20,7 +20,7 @@ #define CPLL_HZ (500 * MHz) #define HPLL_HZ (1400 * MHz) #define PCLK_PDPMU_HZ (100 * MHz) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define ACLK_PDBUS_HZ (396 * MHz) #else #define ACLK_PDBUS_HZ (500 * MHz) @@ -32,7 +32,7 @@ #define HCLK_PDCORE_HZ (200 * MHz) #define HCLK_PDAUDIO_HZ (150 * MHz) #define CLK_OSC0_DIV_HZ (32768) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define ACLK_PDVI_HZ (297 * MHz) #define CLK_ISP_HZ (297 * MHz) #define ACLK_PDISPP_HZ (297 * MHz) @@ -324,7 +324,7 @@ enum { DCLK_VOP_DIV_SHIFT = 0, DCLK_VOP_DIV_MASK = 0xff, -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) /* CRU_CLK_SEL49_CON */ ACLK_PDVI_SEL_SHIFT = 6, ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT, @@ -397,7 +397,7 @@ enum { CLK_GMAC_SRC_DIV_SHIFT = 0, CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT, -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) /* CRU_CLK_SEL68_CON */ ACLK_PDISPP_SEL_SHIFT = 6, ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT, diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index cad25c50bc6..6b2bb5a4586 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -5,7 +5,7 @@ #include <asm/arch/cpu.h> -#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_XPL_BUILD) /* reserve space for BOOT0 header information */ b reset .space 1532 @@ -49,7 +49,7 @@ .word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr .word SUNXI_SRAMC_BASE .word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_TEXT_BASE diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h index 064602292b6..92c7721a530 100644 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -23,7 +23,7 @@ void sdelay(unsigned long); void return_to_fel(uint32_t lr, uint32_t sp); /* Board / SoC level designware gmac init */ -#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC +#if !defined CONFIG_XPL_BUILD && defined CONFIG_SUN7I_GMAC void eth_init_board(void); #else static inline void eth_init_board(void) {} diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 7a4e0972fb7..a399c94213b 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -68,8 +68,9 @@ struct timerus { /* These are the available SKUs (product types) for Tegra */ enum { - SKU_ID_T20_7 = 0x7, + SKU_ID_AP20 = 0x7, SKU_ID_T20 = 0x8, + SKU_ID_AP20H = 0xf, SKU_ID_T25SE = 0x14, SKU_ID_AP25 = 0x17, SKU_ID_T25 = 0x18, diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index 6e6ea1443cb..2ae109ab6c1 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -336,10 +336,13 @@ struct usb_ctlr { #define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25 #define UTMIP_XCVR_HSSLEW_MSB_MASK \ (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_MSB_SHIFT 22 -#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT) -#define UTMIP_XCVR_SETUP_SHIFT 0 -#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT) + +#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) +#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) +#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) +#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) +#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) +#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) /* USBx_UTMIP_XCVR_CFG1_0 */ #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18 diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h index 2e8b3359161..05414061a23 100644 --- a/arch/arm/include/asm/arch-tegra30/funcmux.h +++ b/arch/arm/include/asm/arch-tegra30/funcmux.h @@ -16,5 +16,6 @@ enum { /* UART configs */ FUNCMUX_UART1_ULPI = 0, + FUNCMUX_UART5_SDMMC1 = 1, }; #endif /* _TEGRA30_FUNCMUX_H_ */ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 15627c96e90..382a6d420a2 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,8 +8,8 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_CHAIN_OF_TRUST -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif /* #ifndef CONFIG_XPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index d4ac567e7ed..19d12696a1e 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -47,6 +47,8 @@ #define ELE_ATTEST_REQ (0xDB) #define ELE_RELEASE_PATCH_REQ (0xDC) #define ELE_OTP_SEQ_SWITH_REQ (0xDD) +#define ELE_WRITE_SHADOW_REQ (0xF2) +#define ELE_READ_SHADOW_REQ (0xF3) /* ELE failure indications */ #define ELE_ROM_PING_FAILURE_IND (0x0A) @@ -154,4 +156,6 @@ int ele_release_m33_trout(void); int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response); int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response); int ele_start_rng(void); +int ele_write_shadow_fuse(u32 fuse_id, u32 fuse_val, u32 *response); +int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); #endif diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h index a96a8382fb6..514086a1bc4 100644 --- a/arch/arm/include/asm/ti-common/sys_proto.h +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -57,7 +57,7 @@ static inline u8 uboot_loaded_by_spl(void) */ static inline u32 omap_hw_init_context(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD return OMAP_INIT_CONTEXT_SPL; #else if (uboot_loaded_by_spl()) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index cf760514505..1c95dd6fed2 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -21,7 +21,7 @@ else obj-y += setjmp.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifdef CONFIG_ARM64 obj-y += relocate_64.o else @@ -34,7 +34,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o else -obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o +obj-$(CONFIG_$(PHASE_)FRAMEWORK) += spl.o ifdef CONFIG_SPL_FRAMEWORK obj-$(CONFIG_CMD_BOOTI) += image.o obj-$(CONFIG_CMD_BOOTZ) += zimage.o @@ -42,14 +42,14 @@ endif obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o endif ifdef CONFIG_ARM64 -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset-arm64.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy-arm64.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset-arm64.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy-arm64.o else -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy.o endif -obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o -obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o +obj-$(CONFIG_$(PHASE_)SYS_L2_PL310) += cache-pl310.o +obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),) obj-y += save_prev_bl_data.o @@ -74,7 +74,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_$(SPL_TPL_)SYSRESET +ifndef CONFIG_$(PHASE_)SYSRESET obj-y += reset.o endif @@ -96,7 +96,7 @@ endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL ifndef CONFIG_HAS_THUMB2 @@ -131,11 +131,3 @@ CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI) CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI) CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI) - -extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC) -# TODO: As of v2019.01 the relocation code for the EFI application cannot -# be built on ARMv7-M. -ifndef CONFIG_CPU_V7M -#extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC) -endif -extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 648edf308f6..516754caeaf 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -60,7 +60,7 @@ int check_cache_range(unsigned long start, unsigned long stop) ok = 0; if (!ok) { - warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + warn_non_xpl("CACHE: Misaligned operation at range [%08lx, %08lx]\n", start, stop); } diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index a0311438b45..3e4906e273d 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -102,7 +102,7 @@ ENTRY(_main) #if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) ldr r0, =(CONFIG_TPL_STACK) -#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr r0, =(CONFIG_SPL_STACK) #else ldr r0, =(SYS_INIT_SP_ADDR) @@ -119,14 +119,14 @@ ENTRY(_main) bl debug_uart_init #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS) CLEAR_BSS #endif mov r0, #0 bl board_init_f -#if ! defined(CONFIG_SPL_BUILD) +#if ! defined(CONFIG_XPL_BUILD) /* * Set up intermediate environment (new sp and gd) and call @@ -171,13 +171,13 @@ here: bl c_runtime_cpu_setup /* we still call old routine here */ #endif -#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) +#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) -#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS) +#if !defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS) CLEAR_BSS #endif -# ifdef CONFIG_SPL_BUILD +# ifdef CONFIG_XPL_BUILD /* Use a DRAM stack for the rest of SPL, if requested */ bl spl_relocate_stack_gd cmp r0, #0 @@ -185,7 +185,7 @@ here: movne r9, r0 # endif -#if ! defined(CONFIG_SPL_BUILD) +#if ! defined(CONFIG_XPL_BUILD) bl coloured_LED_init bl red_led_on #endif diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index dcc924dd2f4..32401f544a7 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -71,7 +71,7 @@ ENTRY(_main) */ #if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) ldr x0, =(CONFIG_TPL_STACK) -#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) #elif defined(CONFIG_INIT_SP_RELATIVE) #if CONFIG_POSITION_INDEPENDENT @@ -99,7 +99,7 @@ ENTRY(_main) mov x0, #0 bl board_init_f -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /* * Set up intermediate environment (new sp and gd) and call * relocate_code(addr_moni). Trick here is that we'll return @@ -139,9 +139,9 @@ relocation_return: * Set up final (full) environment */ bl c_runtime_cpu_setup /* still call old routine */ -#endif /* !CONFIG_SPL_BUILD */ -#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) -#if defined(CONFIG_SPL_BUILD) +#endif /* !CONFIG_XPL_BUILD */ +#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK) +#if defined(CONFIG_XPL_BUILD) bl spl_relocate_stack_gd /* may return NULL */ /* set up gd here, outside any C code, if new stack is returned */ cmp x0, #0 diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index 0a96ba1355f..602efe04c04 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -12,7 +12,7 @@ int raise (int signum) { /* Even if printf() is available, it's large. Punt it for SPL builds */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) printf("raise: Signal # %d caught\n", signum); #endif return 0; diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index 2b21ec0734e..78507b76894 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; int arch_reserve_stacks(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ gd->irq_sp = gd->start_addr_sp; #else diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index b6b879339df..cf3f6c3e65c 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -133,7 +133,7 @@ _fiq: .word fiq /* SPL interrupt handling: just hang */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE) .align 5 @@ -166,7 +166,7 @@ fiq: b 1b /* hang and never return */ #endif -#else /* !CONFIG_SPL_BUILD */ +#else /* !CONFIG_XPL_BUILD */ /* IRQ stack memory (calculated at run-time) + 8 bytes */ .globl IRQ_STACK_START_IN @@ -332,4 +332,4 @@ fiq: bad_save_user_regs bl do_fiq -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c index 51287251b3f..7e1cd4dd8bc 100644 --- a/arch/arm/lib/zimage.c +++ b/arch/arm/lib/zimage.c @@ -24,14 +24,14 @@ int bootz_setup(ulong image, ulong *start, ulong *end) if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC && zi->zi_magic != BAREBOX_IMAGE_MAGIC) { - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) puts("zimage: Bad magic!\n"); return 1; } *start = zi->zi_start; *end = zi->zi_end; - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start, *end); diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile index 448d3201aff..18f9f75e8ef 100644 --- a/arch/arm/mach-aspeed/ast2600/Makefile +++ b/arch/arm/mach-aspeed/ast2600/Makefile @@ -1,2 +1,2 @@ obj-y += lowlevel_init.o board_common.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/arch/arm/mach-aspeed/ast2600/lowlevel_init.S b/arch/arm/mach-aspeed/ast2600/lowlevel_init.S index 594963d039d..d1c31068685 100644 --- a/arch/arm/mach-aspeed/ast2600/lowlevel_init.S +++ b/arch/arm/mach-aspeed/ast2600/lowlevel_init.S @@ -97,7 +97,7 @@ .globl lowlevel_init lowlevel_init: -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD) mov pc, lr #else /* setup ARM arch timer frequency */ diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index cbd0ed68c27..447cd80642c 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o -ifneq ($(CONFIG_SPL_BUILD),) +ifneq ($(CONFIG_XPL_BUILD),) obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index a8916862b3f..8f0bc5d997e 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o obj-$(CONFIG_SAM9X60) += sam9x60_devices.o obj-y += clock.o obj-y += cpu.o -ifndef CONFIG_$(SPL_TPL_)SYSRESET +ifndef CONFIG_$(PHASE_)SYSRESET obj-y += reset.o endif ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) @@ -32,7 +32,7 @@ obj-y += lowlevel_init.o endif endif -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cache.o := -marm diff --git a/arch/arm/mach-at91/config.mk b/arch/arm/mach-at91/config.mk index 5426394651e..a31612b8179 100644 --- a/arch/arm/mach-at91/config.mk +++ b/arch/arm/mach-at91/config.mk @@ -3,7 +3,7 @@ PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) endif ifeq ($(CONFIG_CPU_V7A),y) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-y += u-boot.img endif endif diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h index c1d92739e47..09b8f0586c6 100644 --- a/arch/arm/mach-at91/include/mach/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -11,6 +11,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> #include <asm/global_data.h> +#include <asm/io.h> #define GCK_CSS_SLOW_CLK 0 #define GCK_CSS_MAIN_CLK 1 diff --git a/arch/arm/mach-bcmbca/bcm6846/Kconfig b/arch/arm/mach-bcmbca/bcm6846/Kconfig index 229ab88dbb0..1f5639f46df 100644 --- a/arch/arm/mach-bcmbca/bcm6846/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6846/Kconfig @@ -8,6 +8,10 @@ if BCM6846 config TARGET_BCM96846 bool "Broadcom 6846 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM + imply MTD_RAW_NAND + imply NAND_BRCMNAND + imply NAND_BRCMNAND_BCMBCA config SYS_SOC default "bcm6846" diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index ae171e3ee22..c994f97bab8 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -9,7 +9,7 @@ obj-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o obj-$(CONFIG_SOC_DA850) += da850_pinmux.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o endif diff --git a/arch/arm/mach-davinci/config.mk b/arch/arm/mach-davinci/config.mk index edbac8e8e21..3b972a26c0c 100644 --- a/arch/arm/mach-davinci/config.mk +++ b/arch/arm/mach-davinci/config.mk @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2012, Texas Instruments, Incorporated - https://www.ti.com/ -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais endif diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 6c97e5810cd..07125eac7cd 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index dd097cf5418..ebdc3b89d05 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o obj-$(CONFIG_EXYNOS5420) += sec_boot.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 0967ab995a9..0c50b2e2b99 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -221,8 +221,8 @@ int do_lowlevel_init(void) if (actions & DO_CLOCKS) { system_clock_init(); #ifdef CONFIG_DEBUG_UART -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ - !defined(CONFIG_SPL_BUILD) +#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ + !defined(CONFIG_XPL_BUILD) exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); debug_uart_init(); #endif diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 07d19fd17ba..48c325190d5 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -171,7 +171,7 @@ static int exynos5420_mmc_config(int peripheral, int flags) * this same assumption. */ if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD gpio_request(i, "sdmmc0_vdden"); #endif gpio_set_value(i, 1); diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index f8903afc92e..21d955b4aef 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -10,7 +10,7 @@ obj-y = iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),imx8m)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o @@ -22,7 +22,7 @@ obj-y += cpu.o endif ifeq ($(SOC),$(filter $(SOC),imx8m imx9)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-y += fdt.o endif endif @@ -38,7 +38,7 @@ endif ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imx9 imxrt)) obj-y += misc.o obj-$(CONFIG_CMD_PRIBLOB) += priblob.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o @@ -46,7 +46,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o endif ifeq ($(SOC),$(filter $(SOC),mx7 imx8m)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o endif endif @@ -57,10 +57,10 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mx7)) obj-y += cache.o init.o obj-$(CONFIG_FEC_MXC) += mac.o obj-$(CONFIG_IMX_RDC) += rdc-sema.o -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif -obj-$(CONFIG_$(SPL_)SATA) += sata.o +obj-$(CONFIG_$(XPL_)SATA) += sata.o obj-$(CONFIG_IMX_HAB) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif @@ -73,18 +73,18 @@ obj-y += ddrmc-vf610.o obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o endif ifeq ($(SOC),$(filter $(SOC),imx8)) -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif endif -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o endif -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o endif @@ -128,7 +128,7 @@ container.cfg: $(IMX_CONTAINER_CFG) FORCE ifeq ($(CONFIG_ARCH_IMX8), y) CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh IMAGE_TYPE := imx8image -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi) endif DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi) diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index 9f37e611a1e..8f66de699c5 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -143,6 +143,6 @@ U_BOOT_LONGHELP(mfgprot, U_BOOT_CMD( mfgprot, 4, 1, do_mfgprot, - "Manufacturing Protection\n", + "Manufacturing Protection", mfgprot_help_text ); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index ceee31eecd7..17de9ff98ec 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -39,7 +39,7 @@ u32 get_imx_reset_cause(void) if (reset_cause == -1) { reset_cause = readl(&src_regs->srsr); /* preserve the value for U-Boot proper */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) writel(reset_cause, &src_regs->srsr); #endif } @@ -47,7 +47,7 @@ u32 get_imx_reset_cause(void) return reset_cause; } -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) static char *get_reset_cause(void) { switch (get_imx_reset_cause()) { @@ -92,7 +92,7 @@ static char *get_reset_cause(void) } #endif -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) const char *get_imx_type(u32 imxtype) { diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index 85d90686f68..a8107f46ae5 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -245,7 +245,7 @@ void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset, return ret; } -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */ @@ -727,7 +727,7 @@ U_BOOT_CMD( "" ); -#endif /* !defined(CONFIG_SPL_BUILD) */ +#endif /* !defined(CONFIG_XPL_BUILD) */ /* Get CSF Header length */ static int get_hab_hdr_len(struct hab_hdr *hdr) @@ -939,7 +939,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, puts("Dumping CSF Header\n"); print_buffer(ivt->csf, (void *)(uintptr_t)(ivt->csf), 4, 0x10, 0); -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) get_hab_status(); #endif @@ -989,7 +989,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, } hab_exit_failure_print_status: -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) get_hab_status(); #endif diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index ed44df394b1..324e010bb2c 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -345,9 +345,9 @@ int ahab_close(void) u16 lc; err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in get lifecycle\n"); - return -EIO; + return err; } if (lc != 0x20) { @@ -357,9 +357,9 @@ int ahab_close(void) } err = sc_seco_forward_lifecycle(-1, 16); - if (err != SC_ERR_NONE) { + if (err) { printf("Error in forward lifecycle to OEM closed\n"); - return -EIO; + return err; } return 0; diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 834aca82bcf..37a5473ac7c 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -48,7 +48,7 @@ static char *get_reset_cause(void) { sc_pm_reset_reason_t reason; - if (sc_pm_reset_reason(-1, &reason) != SC_ERR_NONE) + if (sc_pm_reset_reason(-1, &reason)) return "Unknown reset"; switch (reason) { @@ -89,11 +89,11 @@ __weak void reset_cpu(void) int arch_cpu_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) spl_save_restore_data(); #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct pass_over_info_t *pass_over; if (is_soc_rev(CHIP_REV_A)) { @@ -160,6 +160,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) sc_faddr_t tcml_addr; u32 tcml_size = SZ_128K; ulong addr; + int ret; switch (core_id) { case 0: @@ -187,10 +188,12 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Power on M4 and MU\n"); - if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON); + if (ret) + return ret; - if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON); + if (ret) return -EIO; printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr); @@ -199,7 +202,8 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) memcpy((void *)tcml_addr, (void *)addr, tcml_size); printf("Start M4 %u\n", core_id); - if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE) + ret = sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr); + if (ret) return -EIO; printf("bootaux complete\n"); @@ -214,6 +218,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) sc_faddr_t aux_core_ram; u32 size; ulong addr; + int ret; switch (core_id) { case 0: @@ -242,20 +247,23 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Power on aux core %d\n", core_id); - if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON); + if (ret) + return ret; if (mu_rsrc != SC_R_NONE) { - if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + ret = sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON); + if (ret) return -EIO; } if (core_id == 1) { struct power_domain pd; - if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) { + ret = sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false); + if (ret) { printf("Error enable clock\n"); - return -EIO; + return ret; } if (!imx8_power_domain_lookup_name("audio_sai0", &pd)) { @@ -286,8 +294,9 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); - if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE) - return -EIO; + ret = sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram); + if (ret) + return ret; printf("bootaux complete\n"); return 0; @@ -313,7 +322,7 @@ int arch_auxiliary_core_check_up(u32 core_id) return 0; } - if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE) + if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode)) return 0; if (power_mode != SC_PM_PW_MODE_OFF) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index d1fdaec7043..9d1fabe91c0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -197,6 +197,7 @@ config TARGET_IMX8MP_DEBIX_MODEL_A select IMX8MP select IMX8M_LPDDR4 select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_IMX8MP_DH_DHCOM_PDK2 bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d7fd102c955..d5745f67262 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -51,7 +51,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 43e677deae2..2f53430b4d0 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -611,7 +611,7 @@ void dram_disable_bypass(void) CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void dram_pll_init(ulong pll_val) { u32 val; @@ -791,7 +791,7 @@ int clock_init(void) /* * Dump some clockes. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 46974bf0618..a72329ea919 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -45,7 +45,7 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = { int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); @@ -255,7 +255,7 @@ int dram_init(void) return ret; /* rom_pointer[1] contains the size of TEE occupies */ - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) gd->ram_size = sdram_size - rom_pointer[1]; else gd->ram_size = sdram_size; @@ -284,7 +284,7 @@ int dram_init_banksize(void) } gd->bd->bi_dram[bank].start = PHYS_SDRAM; - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; @@ -329,7 +329,7 @@ phys_size_t get_effective_memsize(void) sdram_b1_size = sdram_size; } - if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && + if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { /* We will relocate u-boot to Top of dram1. Tee position has two cases: * 1. At the top of dram1, Then return the size removed optee size. @@ -612,7 +612,7 @@ static void early_enable_caches(void) phys_size_t sdram_size; int entry, ret; - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return; if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) @@ -646,7 +646,7 @@ int arch_cpu_init(void) * ROM might disable clock for SCTR, * enable the clock before timer_init. */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) clock_enable(CCGR_SCTR, 1); /* * Init timer at very early state, because sscg pll setting @@ -654,7 +654,7 @@ int arch_cpu_init(void) */ timer_init(); - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { clock_init(); imx_set_wdog_powerdown(false); @@ -1004,6 +1004,7 @@ int disable_vpu_nodes(void *blob) "/soc@0/video-codec@38300000", "/soc@0/video-codec@38310000", "/soc@0/blk-ctrl@38330000", + "/soc@0/blk-ctl@38330000", }; if (is_imx8mq()) @@ -1476,7 +1477,7 @@ int arch_misc_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) bool serror_need_skip = true; diff --git a/arch/arm/mach-imx/imx8ulp/Makefile b/arch/arm/mach-imx/imx8ulp/Makefile index 2c9938fcdf0..b478dab59d0 100644 --- a/arch/arm/mach-imx/imx8ulp/Makefile +++ b/arch/arm/mach-imx/imx8ulp/Makefile @@ -6,6 +6,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += upower/ endif diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index fadf165ece2..c390f20d769 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -519,7 +519,7 @@ u32 get_lpuart_clk(void) return pcc_clock_get_rate(lpuart_pcc[index], lpuart_pcc_slots[index]); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S index 791c26407c9..9ede695dbba 100644 --- a/arch/arm/mach-imx/imx8ulp/lowlevel_init.S +++ b/arch/arm/mach-imx/imx8ulp/lowlevel_init.S @@ -16,7 +16,7 @@ rom_pointer: .global save_boot_params save_boot_params: -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* The firmware provided ATAG/FDT address can be found in r2/x0 */ adr x0, rom_pointer stp x1, x2, [x0], #16 diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index c3722c60836..b5dc45296d1 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -104,7 +104,7 @@ enum bt_mode get_boot_mode(void) bool m33_image_booted(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { u32 gp6 = 0; /* DGO_GP6 */ @@ -124,7 +124,7 @@ bool m33_image_booted(void) bool rdc_enabled_in_boot(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { u32 val = 0; int ret; bool rdc_en = true; /* Default assume DBD_EN is set */ @@ -146,7 +146,7 @@ bool rdc_enabled_in_boot(void) static void spl_pass_boot_info(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { bool m33_booted = m33_image_booted(); bool rdc_en = rdc_enabled_in_boot(); u32 val = 0; @@ -164,7 +164,7 @@ static void spl_pass_boot_info(void) bool is_m33_handshake_necessary(void) { /* Only need handshake in u-boot */ - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) return (m33_image_booted() || rdc_enabled_in_boot()); else return false; @@ -716,7 +716,7 @@ void set_lpav_qos(void) int arch_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* Enable System Reset Interrupt using WDOG_AD */ setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13)); /* Clear AD_PERIPH Power switch domain out of reset interrupt flag */ @@ -805,7 +805,7 @@ int imx8ulp_dm_post_init(void) } EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init); -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 4d32c28670d..5c1054138fc 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -23,6 +23,13 @@ choice prompt "NXP i.MX9 board select" optional +config TARGET_IMX93_9X9_QSB + bool "imx93_qsb" + select OF_BOARD_FIXUP + select IMX93 + select IMX9_LPDDR4X + imply OF_UPSTREAM + config TARGET_IMX93_11X11_EVK bool "imx93_11x11_evk" select OF_BOARD_FIXUP @@ -42,6 +49,7 @@ config TARGET_PHYCORE_IMX93 endchoice source "board/freescale/imx93_evk/Kconfig" +source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index e1b09ab5341..45a9105a75a 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -5,6 +5,6 @@ obj-y += lowlevel_init.o obj-y += soc.o clock.o clock_root.o trdc.o -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD obj-y += imx_bootaux.o #endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 12685f970de..c00be19c4fa 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -35,6 +35,7 @@ static struct imx_intpll_rate_table imx9_intpll_tbl[] = { static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ + FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */ FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1), FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1), @@ -640,7 +641,7 @@ void enable_usboh3_clk(unsigned char enable) } } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void dram_pll_init(ulong pll_val) { configure_fracpll(DRAM_PLL_CLK, pll_val); @@ -950,7 +951,7 @@ int set_clk_enet(enum enet_freq type) /* * Dump some clockes. */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { u32 freq; diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 47106fffefb..5dbc398e97f 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -7,9 +7,10 @@ #include <config.h> #include <command.h> +#include <asm/arch/ccm_regs.h> #include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/ccm_regs.h> #include <asm/global_data.h> #include <linux/iopoll.h> diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S index 1dc1dbfcddc..97d85911041 100644 --- a/arch/arm/mach-imx/imx9/lowlevel_init.S +++ b/arch/arm/mach-imx/imx9/lowlevel_init.S @@ -16,7 +16,7 @@ rom_pointer: .global save_boot_params save_boot_params: -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* The firmware provided ATAG/FDT address can be found in r2/x0 */ adr x0, rom_pointer stp x1, x2, [x0], #16 diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 04b21207a28..7c28fa39e14 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -383,7 +383,7 @@ int dram_init(void) return ret; /* rom_pointer[1] contains the size of TEE occupies */ - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) gd->ram_size = sdram_size - rom_pointer[1]; else gd->ram_size = sdram_size; @@ -412,7 +412,7 @@ int dram_init_banksize(void) } gd->bd->bi_dram[bank].start = PHYS_SDRAM; - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; @@ -457,7 +457,7 @@ phys_size_t get_effective_memsize(void) else sdram_b1_size = sdram_size; - if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { /* We will relocate u-boot to top of dram1. TEE position has two cases: * 1. At the top of dram1, Then return the size removed optee size. * 2. In the middle of dram1, return the size of dram1. @@ -629,7 +629,7 @@ static int low_drive_freq_update(void *blob) } #ifdef CONFIG_OF_BOARD_FIXUP -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int board_fix_fdt(void *fdt) { /* Update dtb clocks for low drive mode */ @@ -701,7 +701,7 @@ static void save_reset_cause(void) int arch_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* Disable wdog */ init_wdog(); @@ -745,7 +745,7 @@ EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu); int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; unsigned long freq = readl(&sctr->cntfid0); diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 0b8a10fd729..41116e2c6a2 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -940,7 +940,7 @@ void mxc_set_sata_internal_clock(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx6/Makefile b/arch/arm/mach-imx/mx6/Makefile index 7ea8f91e4f0..da461b0be9b 100644 --- a/arch/arm/mach-imx/mx6/Makefile +++ b/arch/arm/mach-imx/mx6/Makefile @@ -7,7 +7,7 @@ obj-y := soc.o clock.o obj-$(CONFIG_IMX_MODULE_FUSE) += module_fuse.o -obj-$(CONFIG_SPL_BUILD) += ddr.o +obj-$(CONFIG_XPL_BUILD) += ddr.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_MX6UL_LITESOM) += litesom.o obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index fb9f56d2e63..b5aa606b8d0 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1367,7 +1367,7 @@ void disable_ipu_clock(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 03e1214c060..c6bf933df94 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -78,7 +78,7 @@ int litesom_mmc_init(struct bd_info *bis) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <linux/libfdt.h> #include <spl.h> #include <asm/arch/mx6-ddr.h> diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index 340e6147b63..6a79dcb5bd1 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -79,7 +79,7 @@ int dram_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #include <asm/arch/mx6-ddr.h> #include <linux/libfdt.h> #include <spl.h> @@ -210,4 +210,4 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 2c0c77e1a56..9b40fe9235a 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -37,7 +37,7 @@ struct scu_regs { u32 fpga_rev; }; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx6_thermal_plat = { .regs = (void *)ANATOP_BASE_ADDR, .fuse_bank = 1, @@ -565,7 +565,7 @@ int board_postclk_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * cfg_val will be used for * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] @@ -600,7 +600,7 @@ const struct boot_mode soc_boot_modes[] = { void reset_misc(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO) lcdif_power_down(); #endif diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 2e68557d6a9..4e0e8ed0582 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -17,13 +17,6 @@ config MX7D select ROM_UNIFIED_SECTIONS imply CMD_FUSE -config TEXT_BASE - default 0x87800000 - -config SPL_TEXT_BASE - depends on SPL - default 0x00912000 - choice prompt "MX7 board select" optional diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index a8606fa9b24..a8328a0b224 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -1100,7 +1100,7 @@ void epdc_clock_disable(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 16c77cbf7be..1b891a2db3d 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -432,7 +432,7 @@ void s_init(void) return; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD const struct boot_mode soc_boot_modes[] = { {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, {"primary", MAKE_CFGVAL_PRIMARY_BOOT}, @@ -450,7 +450,7 @@ int boot_mode_getprisec(void) void reset_misc(void) { -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO) lcdif_power_down(); #endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index fb19c62a520..eca92955a17 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -327,7 +327,7 @@ void hab_caam_clock_enable(unsigned char enable) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * Dump some core clockes. */ diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 198ae2d919c..980e0226156 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -171,7 +171,7 @@ static bool ldo_mode_is_enabled(void) return false; } -#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) +#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_XPL_BUILD)) #if defined(CONFIG_LDO_ENABLED_MODE) static void init_ldo_mode(void) { diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 922f851c56b..96fe2c7c17b 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec) return usec; } -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_SPL_BUILD) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_XPL_BUILD) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile index 1717ca343d6..e2ef88196f8 100644 --- a/arch/arm/mach-k3/am62ax/Makefile +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o -obj-$(CONFIG_SPL_BUILD) += am62a7_init.o +obj-$(CONFIG_XPL_BUILD) += am62a7_init.o diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile index eed91a033eb..3165435f265 100644 --- a/arch/arm/mach-k3/am62px/Makefile +++ b/arch/arm/mach-k3/am62px/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o -obj-$(CONFIG_SPL_BUILD) += am62p5_init.o +obj-$(CONFIG_XPL_BUILD) += am62p5_init.o diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/am62x/Makefile index 8494cdda482..ca10b6a8d3d 100644 --- a/arch/arm/mach-k3/am62x/Makefile +++ b/arch/arm/mach-k3/am62x/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o -obj-$(CONFIG_SPL_BUILD) += am625_init.o +obj-$(CONFIG_XPL_BUILD) += am625_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am62x/am625_fdt.c b/arch/arm/mach-k3/am62x/am625_fdt.c index 8fe200a4231..ab9b573f3cf 100644 --- a/arch/arm/mach-k3/am62x/am625_fdt.c +++ b/arch/arm/mach-k3/am62x/am625_fdt.c @@ -5,6 +5,7 @@ #include <asm/hardware.h> #include <fdt_support.h> +#include <fdtdec.h> #include "../common_fdt.h" @@ -75,12 +76,47 @@ static void fdt_fixup_thermal_zone_nodes_am625(void *blob, int maxc) } } +static void fdt_fixup_thermal_cooling_device_cpus_am625(void *blob, int core_nr) +{ + static const char * const thermal_path[] = { + "/thermal-zones/main0-thermal/cooling-maps/map0", + "/thermal-zones/main1-thermal/cooling-maps/map0" + }; + + int node, cnt, i, ret; + u32 cooling_dev[12]; + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + int new_count = core_nr * 3; /* Each CPU has 3 entries */ + int j; + + node = fdt_path_offset(blob, thermal_path[i]); + if (node < 0) + continue; /* Not found, skip it */ + + cnt = fdtdec_get_int_array_count(blob, node, "cooling-device", + cooling_dev, ARRAY_SIZE(cooling_dev)); + if (cnt < 0) + continue; + + for (j = 0; j < new_count; j++) + cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]); + + ret = fdt_setprop(blob, node, "cooling-device", cooling_dev, + new_count * sizeof(u32)); + if (ret < 0) + printf("Error %s, cooling-device setprop failed %d\n", + thermal_path[i], ret); + } +} + int ft_system_setup(void *blob, struct bd_info *bd) { fdt_fixup_cores_nodes_am625(blob, k3_get_core_nr()); fdt_fixup_gpu_nodes_am625(blob, k3_has_gpu()); fdt_fixup_pru_node_am625(blob, k3_has_pru()); fdt_fixup_thermal_zone_nodes_am625(blob, k3_get_max_temp()); + fdt_fixup_thermal_cooling_device_cpus_am625(blob, k3_get_core_nr()); fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); diff --git a/arch/arm/mach-k3/am64x/Makefile b/arch/arm/mach-k3/am64x/Makefile index d0b286276c8..053a8239999 100644 --- a/arch/arm/mach-k3/am64x/Makefile +++ b/arch/arm/mach-k3/am64x/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += am642_init.o +obj-$(CONFIG_XPL_BUILD) += am642_init.o obj-y += boot.o diff --git a/arch/arm/mach-k3/am65x/Makefile b/arch/arm/mach-k3/am65x/Makefile index 20d5f1d3bf1..34734f24ff7 100644 --- a/arch/arm/mach-k3/am65x/Makefile +++ b/arch/arm/mach-k3/am65x/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o -obj-$(CONFIG_SPL_BUILD) += am654_init.o +obj-$(CONFIG_XPL_BUILD) += am654_init.o diff --git a/arch/arm/mach-k3/arm64/cache.S b/arch/arm/mach-k3/arm64/cache.S index 17cfb12f108..6a507ae3af5 100644 --- a/arch/arm/mach-k3/arm64/cache.S +++ b/arch/arm/mach-k3/arm64/cache.S @@ -7,7 +7,7 @@ #include <config.h> #include <linux/linkage.h> -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) ENTRY(__asm_invalidate_l3_dcache) /* Invalidate SPL address range */ mov x0, #CONFIG_SPL_TEXT_BASE diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index df48ec8d479..fa8cd93d664 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -28,6 +28,8 @@ #include <env.h> #include <elf.h> #include <soc.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> #include <asm/arch/k3-qos.h> @@ -246,12 +248,32 @@ void spl_enable_cache(void) #endif } -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +static __maybe_unused void k3_dma_remove(void) +{ + struct udevice *dev; + int rc; + + rc = uclass_find_device(UCLASS_DMA, 0, &dev); + if (!rc && dev) { + rc = device_remove(dev, DM_REMOVE_NORMAL); + if (rc) + pr_warn("Cannot remove dma device '%s' (err=%d)\n", + dev->name, rc); + } else + pr_warn("DMA Device not found (err=%d)\n", rc); +} + void spl_board_prepare_for_boot(void) { +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) dcache_disable(); +#endif +#if IS_ENABLED(CONFIG_SPL_DMA) && IS_ENABLED(CONFIG_SPL_DM_DEVICE_REMOVE) + k3_dma_remove(); +#endif } +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) void spl_board_prepare_for_linux(void) { dcache_disable(); @@ -310,14 +332,3 @@ void setup_qos(void) writel(qos_data[i].val, (uintptr_t)qos_data[i].reg); } #endif - -void efi_add_known_memory(void) -{ - if (IS_ENABLED(CONFIG_EFI_LOADER)) - /* - * Memory over ram_top can be used by various firmware - * Declare to EFI only memory area below ram_top - */ - efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base, - EFI_CONVENTIONAL_MEMORY); -} diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile index 982b88db57d..e4b0e5a8193 100644 --- a/arch/arm/mach-k3/j721e/Makefile +++ b/arch/arm/mach-k3/j721e/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o -obj-$(CONFIG_SPL_BUILD) += j721e_init.o +obj-$(CONFIG_XPL_BUILD) += j721e_init.o diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile index ceef68297c9..051ef1b11d8 100644 --- a/arch/arm/mach-k3/j721s2/Makefile +++ b/arch/arm/mach-k3/j721s2/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o -obj-$(CONFIG_SPL_BUILD) += j721s2_init.o +obj-$(CONFIG_XPL_BUILD) += j721s2_init.o diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index 05453fcad41..6ce3eb87efb 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -312,9 +312,12 @@ void do_dt_magic(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { + struct udevice *dev; + int ret; + k3_spl_init(); #if defined(CONFIG_SPL_OF_LIST) && defined(CONFIG_TI_I2C_BOARD_DETECT) do_dt_magic(); @@ -325,6 +328,13 @@ void board_init_f(ulong dummy) setup_navss_nb(); setup_qos(); + + if (IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_AVS0)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs), + &dev); + if (ret) + printf("AVS init failed: %d\n", ret); + } } #endif diff --git a/arch/arm/mach-k3/j722s/Makefile b/arch/arm/mach-k3/j722s/Makefile index 2b1fec131ed..9b0dd8afd8b 100644 --- a/arch/arm/mach-k3/j722s/Makefile +++ b/arch/arm/mach-k3/j722s/Makefile @@ -4,4 +4,4 @@ # Jayesh Choudhary <j-choudhary@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j722s_fdt.o -obj-$(CONFIG_SPL_BUILD) += j722s_init.o +obj-$(CONFIG_XPL_BUILD) += j722s_init.o diff --git a/arch/arm/mach-k3/j784s4/Makefile b/arch/arm/mach-k3/j784s4/Makefile index 6d1841e3f9e..1d51bcf6e8c 100644 --- a/arch/arm/mach-k3/j784s4/Makefile +++ b/arch/arm/mach-k3/j784s4/Makefile @@ -4,4 +4,4 @@ # Andrew Davis <afd@ti.com> obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o -obj-$(CONFIG_SPL_BUILD) += j784s4_init.o +obj-$(CONFIG_XPL_BUILD) += j784s4_init.o diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile index d3886caa064..f533c5e7743 100644 --- a/arch/arm/mach-k3/r5/Makefile +++ b/arch/arm/mach-k3/r5/Makefile @@ -16,6 +16,6 @@ obj-y += common.o obj-y += lowlevel_init.o obj-y += r5_mpu.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 793bcac9324..97d969271ec 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -67,6 +67,16 @@ static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = { "gluelogic_hfosc0_clkout", }; +static const char * const wkup_usart_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv3_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_usart_mcupll_bypass_out0_parents[] = { + "wkup_usart_clksel_out0", + "gluelogic_hfosc0_clkout", +}; + static const char * const main_pll_hfosc_sel_out0_parents[] = { "gluelogic_hfosc0_clkout", "board_0_hfosc1_clk_out", @@ -206,7 +216,7 @@ static const struct clk_data clk_list[] = { CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000), CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000), CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0), - CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0, 96000000), CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0), CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666), CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), @@ -216,6 +226,8 @@ static const struct clk_data clk_list[] = { CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0), + CLK_MUX("wkup_usart_mcupll_bypass_out0", wkup_usart_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0), @@ -409,6 +421,10 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"), DEV_CLK(395, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(397, 0, "wkup_usart_mcupll_bypass_out0"), + DEV_CLK(397, 1, "wkup_usart_clksel_out0"), + DEV_CLK(397, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(397, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(398, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"), diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index d66ba8b16e0..b32b4ba9588 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -62,6 +62,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(149, &soc_lpsc_list[0]), PSC_DEV(167, &soc_lpsc_list[1]), PSC_DEV(279, &soc_lpsc_list[1]), + PSC_DEV(397, &soc_lpsc_list[1]), PSC_DEV(161, &soc_lpsc_list[2]), PSC_DEV(162, &soc_lpsc_list[3]), PSC_DEV(160, &soc_lpsc_list[4]), diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 7c46914d9dd..3468a370a45 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -126,7 +126,7 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size) * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile index 6c7c25090a2..c864317baea 100644 --- a/arch/arm/mach-keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile @@ -10,7 +10,7 @@ obj-y += psc.o obj-y += clock.o obj-y += mon.o CFLAGS_REMOVE_mon.o := $(LTO_CFLAGS) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cmd_clock.o obj-y += cmd_mon.o obj-y += cmd_poweroff.o diff --git a/arch/arm/mach-keystone/config.mk b/arch/arm/mach-keystone/config.mk index 8eccbdb3018..925a2deee23 100644 --- a/arch/arm/mach-keystone/config.mk +++ b/arch/arm/mach-keystone/config.mk @@ -7,7 +7,7 @@ include $(srctree)/arch/arm/mach-omap2/config_secure.mk -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifeq ($(CONFIG_TI_SECURE_DEVICE),y) INPUTS-y += u-boot_HS_MLO else @@ -25,7 +25,7 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE $(call if_changed,pad_cat) -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) -n U-Boot MLO: u-boot.bin FORCE diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index b945e19ec77..f99b9fbca2e 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -134,7 +134,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile index 6303570beea..f551abb4772 100644 --- a/arch/arm/mach-lpc32xx/Makefile +++ b/arch/arm/mach-lpc32xx/Makefile @@ -5,4 +5,4 @@ obj-y = cpu.o clk.o devices.o timer.o -obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o +obj-$(CONFIG_XPL_BUILD) += dram.o lowlevel_init.o diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 46bdab88206..3d9e4684fb4 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += cpu.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT7622) += mt7622/ diff --git a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S index 0a0672cbea7..9f19003e43b 100644 --- a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S +++ b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S @@ -16,7 +16,7 @@ ENTRY(lowlevel_init) -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Return to U-Boot via saved link register */ mov pc, lr #else diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 329c2e49153..35fd2d0a1d2 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -22,7 +22,7 @@ else # CONFIG_ARCH_KIRKWOOD obj-y = cpu.o obj-y += dram.o obj-y += lowlevel.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o @@ -110,11 +110,11 @@ $(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ include/config/auto.conf $(call cmd,kwbcfg) -endif # CONFIG_SPL_BUILD +endif # CONFIG_XPL_BUILD obj-y += gpio.o obj-y += mbus.o -obj-$(CONFIG_SPL_BUILD) += spl.o -obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += lowlevel_spl.o obj-$(CONFIG_ARMADA_38X) += serdes/a38x/ obj-$(CONFIG_ARMADA_XP) += serdes/axp/ diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 8a145a5f742..da44727cf4f 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -52,7 +52,7 @@ void lowlevel_init(void) */ } -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) +#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) void reset_cpu(void) { struct mvebu_system_registers *reg = @@ -549,7 +549,7 @@ static void ahci_mvebu_mbus_config(void __iomem *base) int i; /* mbus is not initialized in SPL; keep the ROM settings */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) return; dram = mvebu_mbus_dram_info(); diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index af6ce2920e6..37a00501214 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -66,7 +66,7 @@ enum cpu_attrib { /* * Default Device Address MAP BAR values */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_ARMADA_38X #define MBUS_PCI_MEM_BASE 0x88000000 #define MBUS_PCI_MEM_SIZE ((3 * 128) << 20) @@ -81,19 +81,19 @@ enum cpu_attrib { #define MBUS_PCI_IO_BASE 0xF1100000 #define MBUS_PCI_IO_SIZE ((MBUS_PCI_MAX_PORTS * 64) << 10) #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define MBUS_SPI_BASE 0xD4000000 #define MBUS_SPI_SIZE (64 << 20) #else #define MBUS_SPI_BASE 0xF4000000 #define MBUS_SPI_SIZE (8 << 20) #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #define MBUS_DFX_BASE 0xF6000000 #define MBUS_DFX_SIZE (1 << 20) #endif #define MBUS_BOOTROM_BASE 0xF8000000 -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define MBUS_BOOTROM_SIZE (128 << 20) #else #define MBUS_BOOTROM_SIZE (8 << 20) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index dc68d406f99..495530d8452 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -36,7 +36,7 @@ /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700) +#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARMADA_3700) /* * The SPL U-Boot version still runs with the default * address for the internal registers, configured by diff --git a/arch/arm/mach-mvebu/serdes/a38x/Makefile b/arch/arm/mach-mvebu/serdes/a38x/Makefile index 5a70b375966..c33e272217d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/Makefile +++ b/arch/arm/mach-mvebu/serdes/a38x/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec-38x.o -obj-$(CONFIG_SPL_BUILD) += seq_exec.o -obj-$(CONFIG_SPL_BUILD) += sys_env_lib.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec-38x.o +obj-$(CONFIG_XPL_BUILD) += seq_exec.o +obj-$(CONFIG_XPL_BUILD) += sys_env_lib.o diff --git a/arch/arm/mach-mvebu/serdes/axp/Makefile b/arch/arm/mach-mvebu/serdes/axp/Makefile index 897afb703ad..7d48f8da9ed 100644 --- a/arch/arm/mach-mvebu/serdes/axp/Makefile +++ b/arch/arm/mach-mvebu/serdes/axp/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o -obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o +obj-$(CONFIG_XPL_BUILD) = high_speed_env_lib.o +obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec.o diff --git a/arch/arm/mach-nexell/include/mach/display.h b/arch/arm/mach-nexell/include/mach/display.h index b0ee9126057..3a4e2c47f5e 100644 --- a/arch/arm/mach-nexell/include/mach/display.h +++ b/arch/arm/mach-nexell/include/mach/display.h @@ -265,7 +265,7 @@ int dp_plane_set_enable(int module, int layer, int on); int dp_plane_set_address(int module, int layer, unsigned int address); int dp_plane_wait_vsync(int module, int layer, int fps); -#if defined CONFIG_SPL_BUILD || \ +#if defined CONFIG_XPL_BUILD || \ (!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL)) int nx_display_probe(struct nx_display_plat *plat); #endif diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d683c64566a..fb5ea97e56e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -11,7 +11,7 @@ obj-y += reset.o ifeq ($(CONFIG_TIMER),) obj-y += timer.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += timer.o endif endif @@ -26,7 +26,7 @@ obj-y += vc.o obj-y += abb.o endif -ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),) +ifeq ($(CONFIG_$(PHASE_)SYS_DCACHE_OFF),) obj-y += omap-cache.o endif diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 3f1af7f1633..6f3587f01d0 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -11,7 +11,7 @@ endif obj-y += sys_info.o obj-y += ddr.o -ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),) obj-y += emif4.o endif obj-y += board.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index abdc1e40335..4e9ad8935e3 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -209,7 +209,7 @@ int cpu_mmc_init(struct bd_info *bis) /* AM33XX has two MUSB controllers which can be host or gadget */ #if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \ - defined(CONFIG_SPL_BUILD) + defined(CONFIG_XPL_BUILD) static struct musb_hdrc_config musb_config = { .multipoint = 1, @@ -282,7 +282,7 @@ int arch_misc_init(void) #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ - (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) + (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) static void rtc32k_unlock(struct davinci_rtc *rtc) { /* @@ -295,7 +295,7 @@ static void rtc32k_unlock(struct davinci_rtc *rtc) } #endif -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) /* * Write contents of the RTC_SCRATCH1 register based on board type * Two things are passed @@ -331,7 +331,7 @@ int board_early_init_f(void) { set_mux_conf_regs(); prcm_init(); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) update_rtc_magic(); #endif return 0; @@ -379,7 +379,7 @@ static void watchdog_disable(void) ; } -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) /* * Check if we are executing rtc-only + DDR mode, and resume from it if needed */ @@ -455,7 +455,7 @@ am43xx_wait: void s_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT) rtc_only(); #endif } @@ -474,7 +474,7 @@ void early_system_init(void) set_uart_mux_conf(); setup_early_clocks(); uart_soft_reset(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, @@ -483,7 +483,7 @@ void early_system_init(void) save_omap_boot_params(); #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD spl_early_init(); #endif @@ -497,7 +497,7 @@ void early_system_init(void) #endif } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { hw_data_init(); @@ -526,7 +526,7 @@ EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init); #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { - if (u_boot_first_phase()) { + if (xpl_is_first_phase()) { hw_data_init(); set_uart_mux_conf(); setup_early_clocks(); diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 649bc07047a..ddd7eeaf052 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -173,7 +173,7 @@ void save_omap_boot_params(void) #endif } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 spl_boot_device(void) { return gd->arch.omap_boot_device; @@ -208,7 +208,7 @@ void spl_boot_ipu(void) int ret, size; u32 loadaddr = IPU1_LOAD_ADDR; - if (!IS_ENABLED(CONFIG_SPL_BUILD) || + if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) return; @@ -286,7 +286,7 @@ void spl_soc_init(void) #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) hw_watchdog_init(); #endif - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) spl_boot_ipu(); } diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 18d099145c5..f05b16797ec 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -24,7 +24,7 @@ #include <asm/omap_gpio.h> #include <asm/emif.h> -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * printing to console doesn't work unless * this code is executed from SPL diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk index 30d8fb1b1d9..02b26733ee6 100644 --- a/arch/arm/mach-omap2/config.mk +++ b/arch/arm/mach-omap2/config.mk @@ -5,7 +5,7 @@ include $(srctree)/arch/arm/mach-omap2/config_secure.mk -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifeq ($(CONFIG_TI_SECURE_DEVICE),y) # Refer to README.ti-secure for more info # On DRA7xx/AM57xx: # diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index 40db1aec142..62ac27dfa90 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -4,7 +4,7 @@ quiet_cmd_mkomapsecimg = SECURE $@ ifneq ($(TI_SECURE_DEV_PKG),) ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),) -ifneq ($(CONFIG_SPL_BUILD),) +ifneq ($(CONFIG_XPL_BUILD),) cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_SPL_TEXT_BASE) \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index bb67e50fd56..b1e486a99d9 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -113,7 +113,7 @@ static void omap_rev_string(void) puts("\n"); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void spl_display_print(void) { omap_rev_string(); @@ -175,7 +175,7 @@ void __weak init_package_revision(void) */ int early_system_init(void) { -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) int ret; int rescan; #endif @@ -183,19 +183,19 @@ int early_system_init(void) hw_data_init(); init_package_revision(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD if (warm_reset()) force_emif_self_refresh(); #endif watchdog_init(); set_mux_conf_regs(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD srcomp_enable(); do_io_settings(); #endif setup_early_clocks(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, @@ -206,7 +206,7 @@ int early_system_init(void) #endif do_board_detect(); -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) /* * Board detection has been done. * Let us see if another dtb wouldn't be a better match @@ -228,7 +228,7 @@ int early_system_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { early_system_init(); diff --git a/arch/arm/mach-omap2/omap3/Makefile b/arch/arm/mach-omap2/omap3/Makefile index 151bdf6ebc9..159633e7f6d 100644 --- a/arch/arm/mach-omap2/omap3/Makefile +++ b/arch/arm/mach-omap2/omap3/Makefile @@ -15,7 +15,7 @@ obj-y += clock.o obj-y += sys_info.o obj-y += prcm-regs.o obj-y += hw_data.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o endif diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 1de343ff48e..4b6ce6940a9 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -211,7 +211,7 @@ void s_init(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void board_init_f(ulong dummy) { early_system_init(); @@ -280,7 +280,7 @@ void abort(void) { } -#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_XPL_BUILD) /****************************************************************************** * OMAP3 specific command to switch between NAND HW and SW ecc *****************************************************************************/ @@ -331,7 +331,7 @@ U_BOOT_CMD( "nandecc sw - Switch to NAND software ecc algorithm." ); -#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ +#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_XPL_BUILD */ #ifdef CONFIG_DISPLAY_BOARDINFO /** diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 404333689f6..24fae484369 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -146,7 +146,7 @@ static void do_sdrc_init(u32 cs, u32 early) * then set cs_cfg to the appropriate value then try and * setup CS1. */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* set/modify board-specific timings */ get_board_mem_timings(&timings); #endif @@ -166,7 +166,7 @@ static void do_sdrc_init(u32 cs, u32 early) writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD write_sdrc_timings(CS0, sdrc_actim_base0, &timings); make_cs1_contiguous(); write_sdrc_timings(CS1, sdrc_actim_base1, &timings); diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index 7f41e85c4a6..42f9c63fe12 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -50,7 +50,7 @@ void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) writel(pad->val, base + pad->offset); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* LPDDR2 specific IO settings */ static void io_settings_lpddr2(void) { diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 16bbc93f4a3..b1d11a4d1a4 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -178,7 +178,7 @@ auth_exit: * via YMODEM. This is done to avoid disturbing the YMODEM serial * protocol transactions. */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + if (!(IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && spl_boot_device() == BOOT_DEVICE_UART)) printf("Authentication passed\n"); diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index a8b87f6d710..3c381dedaf8 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -11,13 +11,13 @@ obj-y = cpu.o obj-y += dram.o obj-y += timer.o -ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT +ifndef CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif # some files can only build in ARM or THUMB2, not THUMB1 -ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD +ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD ifndef CONFIG_HAS_THUMB2 CFLAGS_cpu.o := -marm diff --git a/arch/arm/mach-orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index 58ee67eca50..4eba69a6909 100644 --- a/arch/arm/mach-orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c @@ -235,7 +235,7 @@ int arch_cpu_init(void) /* Enable and invalidate L2 cache in write through mode */ invalidate_l2_cache(); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD orion5x_config_adr_windows(); #endif diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index aa3fcf7c301..358d2a49fbb 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -69,7 +69,7 @@ lowlevel_init: -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Use 'r2 as the base for internal register accesses */ ldr r2, =ORION5X_REGS_PHY_BASE @@ -280,7 +280,7 @@ lowlevel_init: ldr r0, =0x7fff0001 str r0, [r3, #0x504] -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* Return to U-Boot via saved link register */ mov pc, lr diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index 1d8c3eea99c..fe88a2e0373 100644 --- a/arch/arm/mach-renesas/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h @@ -9,7 +9,7 @@ _start: ARM_VECTORS -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .word 0x0badc0d3; .word 0x0badc0d3; .word 0x0badc0d3; diff --git a/arch/arm/mach-renesas/lowlevel_init_ca15.S b/arch/arm/mach-renesas/lowlevel_init_ca15.S index 059cd738785..ecefa3d5c43 100644 --- a/arch/arm/mach-renesas/lowlevel_init_ca15.S +++ b/arch/arm/mach-renesas/lowlevel_init_ca15.S @@ -11,7 +11,7 @@ #include <system-constants.h> ENTRY(lowlevel_init) -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD mrc p15, 0, r4, c0, c0, 5 /* mpidr */ orr r4, r4, r4, lsr #6 and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index fc1b638ff01..269c219a6f8 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -257,7 +257,6 @@ config ROCKCHIP_RK3399 select SPL_SYSCON if SPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS - select SPL_SERIAL select CLK select FIT select PINCTRL @@ -288,6 +287,7 @@ config ROCKCHIP_RK3399 imply SPL_DM_SEQ_ALIAS imply SPL_FIT_SIGNATURE imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SERIAL imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT imply TPL_CLK imply TPL_DM diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 3b13891ec24..5e7edc99cdc 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -15,7 +15,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) # Always include boot_mode.o, as we bypass it (i.e. turn it off) # inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way, @@ -29,7 +29,7 @@ ifeq ($(CONFIG_TPL_BUILD),) obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o endif -obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o +obj-$(CONFIG_$(PHASE_)RAM) += sdram.o obj-$(CONFIG_ROCKCHIP_PX30) += px30/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ @@ -51,5 +51,5 @@ obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/ obj-spl-$(CONFIG_TPL_BUILD) = # Now add SPL/TPL objects back into the main build -obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y) +obj-$(CONFIG_XPL_BUILD) += $(obj-spl-y) obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 3fadf7e4122..75d6693e28a 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -472,9 +472,18 @@ __weak int misc_init_r(void) __weak int board_rng_seed(struct abuf *buf) { struct udevice *dev; - size_t len = 0x8; + ulong len = env_get_ulong("rng_seed_size", 10, 64); u64 *data; + if (len < 64) { + /* + * rng_seed_size should be at least 32 bytes for Linux 5.19+, + * or 64 for older Linux kernel versions + */ + log_warning("Value for rng_seed_size (%lu) too low, Linux kernel RNG may fail to initialize early\n", + len); + } + data = malloc(len); if (!data) { printf("Out of memory\n"); diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8b1509e55f2..8ce9ac561f0 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -244,7 +244,7 @@ int arch_cpu_init(void) static struct px30_cru * const cru = (void *)CRU_BASE; u32 __maybe_unused val; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* We do some SoC one time setting here. */ /* Disable the ddr secure region setting to make it non-secure */ writel(0x0, DDR_FW_BASE + FW_DDR_CON); diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 299fc50635d..038180c275c 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -6,7 +6,7 @@ obj-y += clk_rk3036.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += syscon_rk3036.o endif diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c index 70b55ca8abf..b8c177a4d0d 100644 --- a/arch/arm/mach-rockchip/rk3066/rk3066.c +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -27,7 +27,7 @@ void board_debug_uart_init(void) void spl_board_init(void) { - if (!IS_ENABLED(CONFIG_SPL_BUILD)) + if (!IS_ENABLED(CONFIG_XPL_BUILD)) return; if (IS_ENABLED(CONFIG_SPL_DM_MMC)) { diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c index 53b2eaa2d53..7cce1112fbd 100644 --- a/arch/arm/mach-rockchip/rk3188/rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -51,7 +51,7 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int arch_cpu_init(void) { struct rk3188_grf *grf; @@ -106,7 +106,7 @@ int rk_board_late_init(void) return rk3188_board_late_init(); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static int setup_led(void) { #ifdef CONFIG_SPL_LED diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c index 712c0524266..e35ca7778e7 100644 --- a/arch/arm/mach-rockchip/rk322x/rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -51,7 +51,7 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define SGRF_BASE 0x10150000 static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE; diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index d1170f7e23d..62dd9da6578 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -31,7 +31,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void configure_l2ctlr(void) { u32 l2ctlr; @@ -72,7 +72,7 @@ int rk3288_qos_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD configure_l2ctlr(); #else /* We do some SoC one time setting here. */ diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 6f88638d156..c6b1a35f47e 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -185,7 +185,7 @@ __weak void board_debug_uart_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) int arch_cpu_init(void) { static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE; diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index c86d11943d6..12ad17d9e8b 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -62,7 +62,7 @@ struct mm_region *mem_map = rk3328_mem_map; int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 reg; /* We do some SoC one time setting here. */ diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index f589bf67328..97b9500da25 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -93,7 +93,7 @@ int arch_early_init_r(void) } #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * The SPL (and also the full U-Boot stage on the RK3368) will run in * secure mode (i.e. EL3) and an ATF will eventually be booted before diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 2d7d0f82a2f..edccb2a3980 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -51,7 +51,7 @@ static struct mm_region rk3399_mem_map[] = { struct mm_region *mem_map = rk3399_mem_map; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define TIMER_END_COUNT_L 0x00 #define TIMER_END_COUNT_H 0x04 @@ -83,7 +83,7 @@ void rockchip_stimer_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct rk3399_pmusgrf_regs *sgrf; struct rk3399_grf_regs *grf; @@ -136,7 +136,7 @@ void board_debug_uart_init(void) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { rk_setreg(&grf->io_vsel, 1 << 0); @@ -169,7 +169,7 @@ void board_debug_uart_init(void) } #endif -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) static void rk3399_force_power_on_reset(void) { ofnode node; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 899cf909fbb..e646f714c92 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -22,6 +22,11 @@ config TARGET_ODROID_M1_RK3568 help Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC. +config TARGET_ODROID_M1S_RK3566 + bool "ODROID-M1S" + help + Hardkernel ODROID-M1S single board computer with a RK3566 SoC. + config TARGET_POWKIDDY_X55_RK3566 bool "Powkiddy X55" help @@ -62,6 +67,7 @@ config TEXT_BASE source "board/rockchip/evb_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" +source "board/hardkernel/odroid_m1s/Kconfig" source "board/pine64/quartz64_rk3566/Kconfig" source "board/powkiddy/x55/Kconfig" source "board/radxa/zero3-rk3566/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 1b3e40074e3..c9a32287e92 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -26,6 +26,8 @@ #define PMU_BASE_ADDR 0xfdd90000 #define PMU_NOC_AUTO_CON0 (0x70) #define PMU_NOC_AUTO_CON1 (0x74) +#define PMU_PWR_GATE_SFTCON (0xa0) +#define PMU_PD_VO_DWN_ENA BIT(7) #define EDP_PHY_GRF_BASE 0xfdcb0000 #define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00) #define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28) @@ -105,7 +107,7 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * When perform idle operation, corresponding clock can * be opened or gated automatically. @@ -130,6 +132,10 @@ int arch_cpu_init(void) writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); + + /* Enable VO power domain for display */ + writel((PMU_PD_VO_DWN_ENA << 16), + PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); #endif return 0; } diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index a76a470cc98..6f28a313325 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -134,6 +134,12 @@ config TARGET_NOVA_RK3588 includes socket for eMMC storage, an SDMMC slot, and a 40-pin GPIO header for expansion. +config TARGET_ODROID_M2_RK3588S + bool "Hardkernel ODROID-M2" + select BOARD_LATE_INIT + help + Hardkernel ODROID-M2 single board computer with a RK3588S2 SoC. + config TARGET_RK3588_NEU6 bool "Edgeble Neural Compute Module 6(Neu6) SoM" select BOARD_LATE_INIT @@ -366,6 +372,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" +source "board/hardkernel/odroid_m2/Kconfig" source "board/indiedroid/nova/Kconfig" source "board/pine64/quartzpro64-rk3588/Kconfig" source "board/turing/turing-rk1-rk3588/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index d3162d3447e..e2dac2a5b80 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -111,7 +111,7 @@ void board_debug_uart_init(void) GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void rockchip_stimer_init(void) { /* If Timer already enabled, don't re-init it */ @@ -130,7 +130,7 @@ void rockchip_stimer_init(void) #ifndef CONFIG_TPL_BUILD int arch_cpu_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE; #endif diff --git a/arch/arm/mach-rockchip/rv1108/Makefile b/arch/arm/mach-rockchip/rv1108/Makefile index 9035a1a8923..283fc966e7b 100644 --- a/arch/arm/mach-rockchip/rv1108/Makefile +++ b/arch/arm/mach-rockchip/rv1108/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += syscon_rv1108.o endif obj-y += rv1108.o diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c index 1c10e9b9f23..27ed5dc19e1 100644 --- a/arch/arm/mach-rockchip/rv1126/rv1126.c +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -66,7 +66,7 @@ int arch_cpu_init(void) * since they are unsecure. * (Note: only secure-world can access this register) */ - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_XPL_BUILD)) writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG); return 0; diff --git a/arch/arm/mach-sc5xx/Makefile b/arch/arm/mach-sc5xx/Makefile index cac768ba565..47b28200a03 100644 --- a/arch/arm/mach-sc5xx/Makefile +++ b/arch/arm/mach-sc5xx/Makefile @@ -19,5 +19,5 @@ obj-$(CONFIG_SC59X) += sc59x-spl.o obj-$(CONFIG_SC59X_64) += sc59x_64.o obj-$(CONFIG_SC59X_64) += sc59x_64-spl.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_SYSCON) += rcu.o diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk index 580964e559c..e7e4c9a1181 100644 --- a/arch/arm/mach-sc5xx/config.mk +++ b/arch/arm/mach-sc5xx/config.mk @@ -8,7 +8,7 @@ # Contact: Greg Malysa <greg.malysa@timesys.com> # -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD INPUTS-y += $(obj)/u-boot-spl.ldr endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec5..5fc61b4a5c6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -80,7 +80,7 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o obj-y += freeze_controller.o diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index feaf5ce4596..24a15f7903f 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -102,7 +102,7 @@ u8 socfpga_get_board_id(void) u32 jtag_usercode; int err; -#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) +#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) err = smc_get_usercode(&jtag_usercode); #else u32 resp_len = 1; @@ -130,7 +130,7 @@ u8 socfpga_get_board_id(void) return board_id; } -#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) int board_fit_config_name_match(const char *name) { char board_name[10]; @@ -154,7 +154,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, } #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT) +#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_FIT) void board_prep_linux(struct bootm_headers *images) { bool use_fit = false; diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 160f6e73ca9..134eaf08e0a 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -99,7 +99,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void) } #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 58b9321131a..5674194f4d1 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -12,7 +12,7 @@ #include <asm/arch/clock_manager.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void sdelay(unsigned long loops); u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h index c78def5066e..2676d6c8283 100644 --- a/arch/arm/mach-socfpga/include/mach/boot0.h +++ b/arch/arm/mach-socfpga/include/mach/boot0.h @@ -9,7 +9,7 @@ _start: ARM_VECTORS -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD .balignl 64,0xf33db33f; .word 0x1337c0d3; /* SoCFPGA preloader validation word */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h index 553ebe660de..80d5047b469 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h @@ -62,7 +62,7 @@ #define CLKMGR_INTER CLKMGR_A10_INTER #define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int cm_basic_init(const void *blob); #endif diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 875927cc4d9..8926c2d1d9c 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -13,7 +13,7 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 4c86f1e9917..2b4f26040fe 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -400,7 +400,7 @@ error: int mbox_reset_cold(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) psci_system_reset(); #else int ret; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 495ba2a0d41..46f9c82bbb2 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -180,7 +180,7 @@ int arch_cpu_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 34c21317894..c442af02888 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -58,7 +58,7 @@ static Altera_desc altera_fpga[] = { }, }; -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) static struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index b898b6f8f22..b136691c685 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -213,7 +213,7 @@ int arch_early_init_r(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index dd0383c7c76..a634c11a028 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -58,7 +58,7 @@ void socfpga_per_reset_all(void) void socfpga_bridges_reset(int enable) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) +#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) u64 arg = enable; int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0); diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index 4347bf6e792..e931f1043b3 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -120,7 +120,7 @@ int socfpga_vendor_authentication(void **p_image, size_t *p_size) debug("mbox_relocate_data_addr = 0x%p\n", mbox_relocate_data_addr); do { - if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { + if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { /* Invoke SMC call to ATF to send the VAB certificate to SDM */ ret = smc_send_mailbox(MBOX_VAB_SRC_CERT, mbox_data_sz, (u32 *)mbox_relocate_data_addr, 0, &resp_len, diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 80933586319..1a4e7c0e7e2 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -14,7 +14,7 @@ */ int timer_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int enable = 0x3; /* timer enable + output signal masked */ int loadval = ~0; @@ -56,4 +56,4 @@ __always_inline void __udelay(unsigned long usec) while (__get_time_stamp() < tmp + 1) /* loop till event */ ; -}
\ No newline at end of file +} diff --git a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c index f13581033e6..60ba557d390 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_soc64.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c @@ -11,7 +11,7 @@ const struct cm_config * const cm_get_default_config(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD struct cm_config *cm_handoff_cfg = (struct cm_config *) (SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA); u32 *conversion = (u32 *)cm_handoff_cfg; @@ -32,7 +32,7 @@ const struct cm_config * const cm_get_default_config(void) const unsigned int cm_get_osc_clk_hz(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC); @@ -50,7 +50,7 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA); writel(clock, diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index d5934a92771..25663a99464 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -39,6 +39,7 @@ choice config STM32MP13X bool "Support STMicroelectronics STM32MP13x Soc" + select ARCH_EARLY_INIT_R select ARM_SMCCC select CPU_V7A select CPU_V7_HAS_NONSEC @@ -57,6 +58,7 @@ config STM32MP13X config STM32MP15X bool "Support STMicroelectronics STM32MP15x Soc" + select ARCH_EARLY_INIT_R select ARCH_SUPPORT_PSCI select BINMAN select CPU_V7A diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index ee8a5428feb..db7ed19bd91 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_STM32MP13X) += stm32mp1/ obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cmd_stm32prog/ obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o obj-$(CONFIG_TFABOOT) += boot_params.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 9ba7a6c9a89..9cbe6a52623 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -409,7 +409,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) u32 tmp_data = 0; int ret; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_OTP, otp, 0, val); @@ -440,7 +440,7 @@ static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc(STM32_SMC_BSEC, STM32_SMC_READ_SHADOW, otp, 0, val); @@ -469,7 +469,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_PROG_OTP, otp, val); @@ -484,7 +484,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) { struct stm32mp_bsec_plat *plat; - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRITE_SHADOW, otp, val); @@ -504,7 +504,7 @@ static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) return 0; /* nothing to do */ } - if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD)) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRLOCK_OTP, otp, 0); @@ -762,7 +762,7 @@ static int stm32mp_bsec_probe(struct udevice *dev) * update unlocked shadow for OTP cleared by the rom code * only executed in SPL, it is done in TF-A for TFABOOT */ - if (IS_ENABLED(CONFIG_SPL_BUILD) && !data->ta) { + if (IS_ENABLED(CONFIG_XPL_BUILD) && !data->ta) { plat = dev_get_plat(dev); /* here 57 is the value for STM32MP15x ROM code, only MPU with SPL support*/ diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 198785353f1..b06105768b3 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -25,8 +25,11 @@ int optee_get_reserved_memory(u32 *start, u32 *size) ofnode node; node = ofnode_path("/reserved-memory/optee"); - if (!ofnode_valid(node)) - return -ENOENT; + if (!ofnode_valid(node)) { + node = ofnode_path("/reserved-memory/optee_core"); + if (!ofnode_valid(node)) + return -ENOENT; + } fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); *start = fdt_start; @@ -62,7 +65,6 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - int ret; phys_size_t size; phys_addr_t reg; u32 optee_start, optee_size; @@ -75,10 +77,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) * if the effective available memory is bigger */ gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + + /* add 8M for U-Boot reserved memory: display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); - ret = optee_get_reserved_memory(&optee_start, &optee_size); - reg = (!ret ? optee_start : gd->ram_top) - size; + reg = gd->ram_top - size; + + /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */ + if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) { + if (!optee_get_reserved_memory(&optee_start, &optee_size)) + reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); + } /* before relocation, mark the U-Boot memory as cacheable by default */ if (!(gd->flags & GD_FLG_RELOC)) @@ -86,14 +95,3 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return reg + size; } - -void efi_add_known_memory(void) -{ - if (IS_ENABLED(CONFIG_EFI_LOADER)) - /* - * Memory over ram_top is reserved to OPTEE. - * Declare to EFI only memory area below ram_top - */ - efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base, - EFI_CONVENTIONAL_MEMORY); -} diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile index ebae50f66c9..db160c24cbc 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -8,12 +8,12 @@ obj-y += cpu.o obj-$(CONFIG_STM32MP13X) += stm32mp13x.o obj-$(CONFIG_STM32MP15X) += stm32mp15x.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += tzc400.o else obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_$(XPL_)STM32MP15_PWR) += pwr_regulator.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 64480da9f8d..62cc98910a7 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -57,7 +57,7 @@ void dram_bank_mmu_setup(int bank) bool use_lmb = false; enum dcache_option option; - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { /* STM32_SYSRAM_BASE exist only when SPL is supported */ #ifdef CONFIG_SPL start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); @@ -133,7 +133,7 @@ int mach_cpu_init(void) if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; - else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) + else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD)) debug_uart_init(); return 0; @@ -143,6 +143,11 @@ void enable_caches(void) { /* I-cache is already enabled in start.S: icache_enable() not needed */ + /* keep D-cache configuration done before relocation, wait arch_early_init_r*/ +} + +int arch_early_init_r(void) +{ /* deactivate the data cache, early enabled in arch_cpu_init() */ dcache_disable(); /* @@ -150,6 +155,8 @@ void enable_caches(void) * warning: the TLB location udpated in board_f.c::reserve_mmu */ dcache_enable(); + + return 0; } static void setup_boot_mode(void) @@ -339,7 +346,7 @@ uintptr_t get_stm32mp_bl2_dtb(void) return nt_fw_dtb; } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c index ca202bec8ee..4f1d783649b 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -214,13 +214,13 @@ static void update_bootmode(void) /* weak function: STM32MP15x mach init for boot without TFA */ void stm32mp_cpu_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (IS_ENABLED(CONFIG_XPL_BUILD)) { security_init(); update_bootmode(); } /* reset copro state in SPL, when used, or in U-Boot */ - if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_XPL_BUILD)) { /* Reset Coprocessor state unless it wakes up from Standby power mode */ if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 17666814c52..8065161e61e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -108,6 +108,23 @@ config DRAM_SUN50I_H616_TPR12 default 0x0 help TPR12 value from vendor DRAM settings. + +choice + prompt "H616 PHY pin mapping selection" + default DRAM_SUN50I_H616_PHY_ADDR_MAP_0 + +config DRAM_SUN50I_H616_PHY_ADDR_MAP_0 + bool "H313/H616/H618" + help + The pin mapping selection used by the H313, H616, H618, and + possibly other dies which use the H616 DRAM controller. + +config DRAM_SUN50I_H616_PHY_ADDR_MAP_1 + bool "H700" + help + The pin mapping selection used by the H700 and possibly other + dies which use the H616 DRAM controller. +endchoice endif config SUN6I_PRCM @@ -437,6 +454,7 @@ config MACH_SUN50I_H616 select ARM64 select DRAM_SUN50I_H616 select SUN50I_GEN_H6 + imply OF_UPSTREAM endchoice diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 3f83c0280ef..eb6a49119a1 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -29,7 +29,7 @@ ifndef CONFIG_ARM64 obj-y += timer.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += clock.o obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 2b64ddc0dc7..701899ee4b2 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -74,7 +74,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) } #endif /* CONFIG_ARM64 */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static int gpio_init(void) { __maybe_unused uint val; @@ -209,7 +209,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image, return 0; } SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #define SUNXI_INVALID_BOOT_SOURCE -1 @@ -258,7 +258,7 @@ static int sunxi_get_boot_source(void) * proper, just return MMC0 as a placeholder, for now. */ if (IS_ENABLED(CONFIG_MACH_SUNIV) && - !IS_ENABLED(CONFIG_SPL_BUILD)) + !IS_ENABLED(CONFIG_XPL_BUILD)) return SUNXI_BOOTED_FROM_MMC0; if (IS_ENABLED(CONFIG_MACH_SUNIV)) @@ -314,7 +314,7 @@ uint32_t sunxi_get_boot_device(void) return -1; /* Never reached */ } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD uint32_t sunxi_get_spl_size(void) { struct boot_file_head *egon_head = (void *)SPL_ADDR; @@ -478,7 +478,7 @@ void board_init_f(ulong dummy) #endif sunxi_board_init(); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ #if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) diff --git a/arch/arm/mach-sunxi/clock_sun4i.c b/arch/arm/mach-sunxi/clock_sun4i.c index 6458d066f7e..1367b439b83 100644 --- a/arch/arm/mach-sunxi/clock_sun4i.c +++ b/arch/arm/mach-sunxi/clock_sun4i.c @@ -13,7 +13,7 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -175,7 +175,7 @@ void clock_set_pll1(unsigned int hz) &ccm->cpu_ahb_apb0_cfg); sdelay(20); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index cc2ee336416..b424a7893ea 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -3,7 +3,7 @@ #include <asm/arch/clock.h> #include <asm/arch/prcm.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = @@ -131,7 +131,7 @@ int clock_twi_onoff(int port, int state) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* PLL_PERIPH0 clock, used by the MMC driver */ unsigned int clock_get_pll6(void) diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 59f7e15ffe8..657736c7ac2 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -16,7 +16,7 @@ #include <linux/bitops.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -169,7 +169,7 @@ void clock_set_pll1(unsigned int clk) &ccm->cpu_axi_cfg); } } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* video, DRAM, PLL_PERIPH clocks */ void clock_set_pll3(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index c00d16a918d..f593749028c 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -15,7 +15,7 @@ #include <asm/arch/sys_proto.h> #include <linux/delay.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { struct sunxi_ccm_reg * const ccm = @@ -100,7 +100,7 @@ void clock_set_pll1(unsigned int clk) CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, &ccm->cpu_axi_cfg); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ void clock_set_pll5(unsigned int clk) diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index abdab405445..5f99071f21b 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -14,7 +14,7 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD static void clock_set_pll2(unsigned int clk) { @@ -188,7 +188,7 @@ int clock_twi_onoff(int port, int state) return 0; } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ /* PLL_PERIPH0 clock (used by the MMC driver) */ unsigned int clock_get_pll4_periph0(void) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 37c139e0eea..863c4f1d7a8 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -55,8 +55,8 @@ static void mbus_configure_port(u8 port, writel_relaxed(cfg1, &mctl_com->master[port].cfg1); } -#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \ - mbus_configure_port(port, bwlimit, false, \ +#define MBUS_CONF(port, priority, qos, acs, bwl0, bwl1, bwl2) \ + mbus_configure_port(port, true, priority, \ MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2) static void mctl_set_master_priority(void) @@ -68,24 +68,25 @@ static void mctl_set_master_priority(void) writel(399, &mctl_com->tmr); writel(BIT(16), &mctl_com->bwcr); - MBUS_CONF( 0, true, HIGHEST, 0, 256, 128, 100); - MBUS_CONF( 1, true, HIGH, 0, 1536, 1400, 256); - MBUS_CONF( 2, true, HIGHEST, 0, 512, 256, 96); - MBUS_CONF( 3, true, HIGH, 0, 256, 100, 80); - MBUS_CONF( 4, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF( 5, true, HIGH, 2, 100, 64, 32); - MBUS_CONF( 6, true, HIGH, 2, 100, 64, 32); - MBUS_CONF( 8, true, HIGH, 0, 256, 128, 64); - MBUS_CONF(11, true, HIGH, 0, 256, 128, 100); - MBUS_CONF(14, true, HIGH, 0, 1024, 256, 64); - MBUS_CONF(16, true, HIGHEST, 6, 8192, 2800, 2400); - MBUS_CONF(21, true, HIGHEST, 6, 2048, 768, 512); - MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32); - MBUS_CONF(26, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF(37, true, HIGH, 0, 256, 128, 64); - MBUS_CONF(38, true, HIGH, 2, 100, 64, 32); - MBUS_CONF(39, true, HIGH, 2, 8192, 5500, 5000); - MBUS_CONF(40, true, HIGH, 2, 100, 64, 32); + MBUS_CONF(0, false, HIGHEST, 0, 256, 128, 100); + MBUS_CONF(1, false, HIGH, 0, 1536, 1400, 256); + MBUS_CONF(2, false, HIGHEST, 0, 512, 256, 96); + MBUS_CONF(3, false, HIGH, 0, 256, 100, 80); + MBUS_CONF(4, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(5, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(6, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(8, false, HIGH, 0, 256, 128, 64); + MBUS_CONF(11, false, HIGH, 0, 256, 128, 100); + MBUS_CONF(14, false, HIGH, 0, 1024, 256, 64); + MBUS_CONF(16, false, HIGHEST, 6, 8192, 2800, 2400); + MBUS_CONF(21, false, HIGHEST, 6, 2048, 768, 512); + MBUS_CONF(22, false, HIGH, 0, 256, 128, 100); + MBUS_CONF(25, true, HIGHEST, 0, 100, 64, 32); + MBUS_CONF(26, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(37, false, HIGH, 0, 256, 128, 64); + MBUS_CONF(38, false, HIGH, 2, 100, 64, 32); + MBUS_CONF(39, false, HIGH, 2, 8192, 5500, 5000); + MBUS_CONF(40, false, HIGH, 2, 100, 64, 32); dmb(); } @@ -225,6 +226,26 @@ static void mctl_set_addrmap(const struct dram_config *config) mctl_ctl->addrmap[8] = 0x3F3F; } +#ifdef CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_1 +static const u8 phy_init[] = { +#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 + 0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b, + 0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a, + 0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19, + 0x06, 0x09, 0x0f +#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3) + 0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19, + 0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07, + 0x08, 0x01, 0x1a +#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4) + 0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01, + 0x18, 0x04, 0x1a +#endif +}; +#else /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */ static const u8 phy_init[] = { #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19, @@ -243,7 +264,7 @@ static const u8 phy_init[] = { 0x18, 0x03, 0x1a #endif }; - +#endif /* CONFIG_DRAM_SUN50I_H616_PHY_ADDR_MAP_0 */ #define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f) static void mctl_phy_configure_odt(const struct dram_para *para) { @@ -293,14 +314,22 @@ static void mctl_phy_configure_odt(const struct dram_para *para) dmb(); } -static bool mctl_phy_write_leveling(const struct dram_config *config) +static bool mctl_phy_write_leveling(const struct dram_para *para, + const struct dram_config *config) { bool result = true; u32 val; clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0xc0, 0x80); - writel(4, SUNXI_DRAM_PHY0_BASE + 0xc); - writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10); + + if (para->type == SUNXI_DRAM_TYPE_LPDDR4) { + /* MR2 value */ + writel(0x1b, SUNXI_DRAM_PHY0_BASE + 0xc); + writel(0, SUNXI_DRAM_PHY0_BASE + 0x10); + } else { + writel(4, SUNXI_DRAM_PHY0_BASE + 0xc); + writel(0x40, SUNXI_DRAM_PHY0_BASE + 0x10); + } setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4); @@ -859,9 +888,9 @@ static void mctl_phy_ca_bit_delay_compensation(const struct dram_para *para, } break; case SUNXI_DRAM_TYPE_LPDDR4: - if (para->tpr2 & 1) { - writel(val, SUNXI_DRAM_PHY0_BASE + 0x788); - } else { + writel(val, SUNXI_DRAM_PHY0_BASE + 0x788); + if (config->ranks == 2) { + val = (para->tpr10 >> 11) & 0x1e; writel(val, SUNXI_DRAM_PHY0_BASE + 0x794); }; break; @@ -986,12 +1015,16 @@ static bool mctl_phy_init(const struct dram_para *para, clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 0xe0, 0x20); } + clrbits_le32(&mctl_com->unk_0x500, 0x200); + udelay(1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8); mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4); + udelay(1000); + writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58); - clrbits_le32(&mctl_com->unk_0x500, 0x200); writel(0, &mctl_ctl->swctl); setbits_le32(&mctl_ctl->dfimisc, 1); @@ -1010,6 +1043,8 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->swstat, 1, 1); mctl_await_completion(&mctl_ctl->statr, 3, 1); + udelay(200); + writel(0, &mctl_ctl->swctl); clrbits_le32(&mctl_ctl->dfimisc, 1); @@ -1080,19 +1115,27 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xb04, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xc72, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0xe09, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); writel(0x1624, &mctl_ctl->mrctrl1); + udelay(10); writel(0x80000030, &mctl_ctl->mrctrl0); + udelay(10); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); break; case SUNXI_DRAM_TYPE_DDR4: @@ -1108,7 +1151,7 @@ static bool mctl_phy_init(const struct dram_para *para, if (para->tpr10 & TPR10_WRITE_LEVELING) { for (i = 0; i < 5; i++) - if (mctl_phy_write_leveling(config)) + if (mctl_phy_write_leveling(para, config)) break; if (i == 5) { debug("write leveling failed!\n"); @@ -1234,9 +1277,6 @@ static bool mctl_ctrl_init(const struct dram_para *para, setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30)); setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30)); - if (para->type == SUNXI_DRAM_TYPE_LPDDR4) - setbits_le32(&mctl_ctl->dbictl, 0x1); - setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); @@ -1248,8 +1288,10 @@ static bool mctl_ctrl_init(const struct dram_para *para, setbits_le32(&mctl_ctl->clken, BIT(8)); clrsetbits_le32(&mctl_com->unk_0x500, BIT(24), 0x300); + udelay(1); /* this write seems to enable PHY MMIO region */ setbits_le32(&mctl_com->unk_0x500, BIT(24)); + udelay(1); if (!mctl_phy_init(para, config)) return false; @@ -1321,28 +1363,33 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para, static void mctl_auto_detect_dram_size(const struct dram_para *para, struct dram_config *config) { - /* detect row address bits */ - config->cols = 8; - config->rows = 18; + unsigned int shift; + + /* max. config for columns, but not rows */ + config->cols = 11; + config->rows = 13; mctl_core_init(para, config); - for (config->rows = 13; config->rows < 18; config->rows++) { - /* 8 banks, 8 bit per byte and 16/32 bit width */ - if (mctl_mem_matches((1 << (config->rows + config->cols + - 4 + config->bus_full_width)))) + shift = config->bus_full_width + 1; + + /* detect column address bits */ + for (config->cols = 8; config->cols < 11; config->cols++) { + if (mctl_mem_matches(1ULL << (config->cols + shift))) break; } + debug("detected %u columns\n", config->cols); - /* detect column address bits */ - config->cols = 11; + /* reconfigure to make sure that all active rows are accessible */ + config->rows = 18; mctl_core_init(para, config); - for (config->cols = 8; config->cols < 11; config->cols++) { - /* 8 bits per byte and 16/32 bit width */ - if (mctl_mem_matches(1 << (config->cols + 1 + - config->bus_full_width))) + /* detect row address bits */ + shift = config->bus_full_width + 4 + config->cols; + for (config->rows = 13; config->rows < 18; config->rows++) { + if (mctl_mem_matches(1ULL << (config->rows + shift))) break; } + debug("detected %u rows\n", config->rows); } static unsigned long mctl_calc_size(const struct dram_config *config) diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c index e6446b9180d..6f5c4acbd62 100644 --- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c +++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c @@ -23,7 +23,7 @@ void mctl_set_timing_params(const struct dram_para *para) u8 trcd = max(ns_to_t(18), 2); u8 trc = ns_to_t(65); u8 txp = max(ns_to_t(8), 2); - u8 trtp = max(ns_to_t(8), 4); + u8 trtp = 4; u8 trp = ns_to_t(21); u8 tras = ns_to_t(42); u16 trefi = ns_to_t(3904) / 32; diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c index a058fea6bef..aa93defb25e 100644 --- a/arch/arm/mach-sunxi/gtbus_sun9i.c +++ b/arch/arm/mach-sunxi/gtbus_sun9i.c @@ -11,7 +11,7 @@ #include <asm/arch/gtbus_sun9i.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void gtbus_init(void) { diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 1d22dc3942f..ebac3473a1f 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -5,7 +5,7 @@ # (C) Copyright 2000-2008 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += spl.o obj-y += cpu.o else @@ -16,7 +16,7 @@ obj-$(CONFIG_TEGRA_GP_PADCTRL) += ap.o obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o -obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o +obj-$(CONFIG_$(XPL_)TEGRA_CRYPTO) += crypto.o obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o @@ -25,7 +25,7 @@ obj-y += dt-setup.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_GPU) += gpu.o obj-$(CONFIG_TEGRA_IVC) += ivc.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index 1ea620e4ab5..f35bdba4d48 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -32,7 +32,7 @@ int tegra_get_chip(void) * Tegra30, 0x35 for T114, and 0x40 for Tegra124. */ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; - debug("%s: CHIPID is 0x%02X\n", __func__, rev); + debug("%s: CHIPID is 0x%02x\n", __func__, rev); return rev; } @@ -43,7 +43,7 @@ int tegra_get_sku_info(void) struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; sku_id = readl(&fuse->sku_info) & 0xff; - debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); + debug("%s: SKU info byte is 0x%02x\n", __func__, sku_id); return sku_id; } @@ -58,8 +58,9 @@ int tegra_get_chip_sku(void) switch (chip_id) { case CHIPID_TEGRA20: switch (sku_id) { - case SKU_ID_T20_7: + case SKU_ID_AP20: case SKU_ID_T20: + case SKU_ID_AP20H: return TEGRA_SOC_T20; case SKU_ID_T25SE: case SKU_ID_AP25: @@ -103,8 +104,8 @@ int tegra_get_chip_sku(void) } /* unknown chip/sku id */ - printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", - __func__, chip_id, sku_id); + printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02x/0x%02x)\n", + __func__, chip_id, sku_id); return TEGRA_SOC_UNKNOWN; } diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index c382e042860..7ca56a3b081 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -47,7 +47,7 @@ enum { static bool from_spl __section(".data"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, unsigned long r3) { @@ -181,7 +181,7 @@ static int uart_configs[] = { -1, -1, -1, - -1, + FUNCMUX_UART5_SDMMC1, /* UARTE */ #elif defined(CONFIG_TEGRA114) -1, -1, diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 5c5838629b2..6e9ef68caf9 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -6,6 +6,7 @@ #include <config.h> #include <dm.h> +#include <dm/root.h> #include <env.h> #include <errno.h> #include <init.h> @@ -46,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ U_BOOT_DRVINFO(tegra_gpios) = { "gpio_tegra" @@ -457,3 +458,18 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } + +#if IS_ENABLED(CONFIG_DTB_RESELECT) +int embedded_dtb_select(void) +{ + int ret, rescan; + + ret = fdtdec_resetup(&rescan); + if (!ret && rescan) { + dm_uninit(); + dm_init_and_scan(true); + } + + return 0; +} +#endif diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index 346d6cb5696..f1c1042b4e2 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -2,6 +2,6 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -obj-$(CONFIG_SPL_BUILD) += cpu.o +obj-$(CONFIG_XPL_BUILD) += cpu.o obj-y += clock.o diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index fb016aa46c9..84c8f86bad0 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -21,8 +21,8 @@ config TARGET_CEI_TK1_SOM bool "Colorado Engineering Inc Tegra124 TK1-som board" select ARCH_SUPPORT_PSCI select BOARD_LATE_INIT - select CPU_V7_HAS_NONSEC if !SPL_BUILD - select CPU_V7_HAS_VIRT if !SPL_BUILD + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT help The Colorado Engineering Tegra TK1-SOM is a very compact (51mmx58mm) board that is functionally almost the same as diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index 6ea511e7b25..dee790015a3 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -5,13 +5,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SPL_BUILD) += cpu.o +obj-$(CONFIG_XPL_BUILD) += cpu.o obj-y += clock.o obj-y += pmc.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ARMV7_NONSEC) += psci.o endif diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index c2ae98eb376..32c1866b099 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -2,8 +2,8 @@ # # (C) Copyright 2010,2011 Nvidia Corporation. -obj-$(CONFIG_SPL_BUILD) += cpu.o -obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o +obj-$(CONFIG_XPL_BUILD) += cpu.o +obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index ee0e6f5b948..b36657a432f 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -2,7 +2,7 @@ # # Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -obj-$(CONFIG_SPL_BUILD) += cpu.o -obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o +obj-$(CONFIG_XPL_BUILD) += cpu.o +obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o obj-y += clock.o diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5172efac0c4..d1ec8195dcb 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += boards.o obj-y += spl_board_init.o diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile index b41aba7e29a..c8ce67ac05a 100644 --- a/arch/arm/mach-uniphier/arm32/Makefile +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += lowlevel_init.o obj-$(CONFIG_DEBUG_LL) += debug_ll.o else diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 1e6bc8433f7..9d0fe5c8583 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -214,7 +214,7 @@ int uniphier_boot_from_backend(void) return !!(readl(sg_base + SG_PINMON0) & BIT(27)); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int do_pinmon(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -267,4 +267,4 @@ U_BOOT_CMD( "" ); -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index c49e44754c0..0e47beb5f22 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile b/arch/arm/mach-uniphier/debug-uart/Makefile index 81e9314a50d..4202cb3503b 100644 --- a/arch/arm/mach-uniphier/debug-uart/Makefile +++ b/arch/arm/mach-uniphier/debug-uart/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c index 1ba012ca45d..6836eb63bfa 100644 --- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c +++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c @@ -26,7 +26,7 @@ static void _debug_uart_putc(int c) writel(c, base + UNIPHIER_UART_TX); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void sg_set_pinsel(unsigned int pin, unsigned int muxval, unsigned int mux_bits, unsigned int reg_stride) { @@ -56,7 +56,7 @@ void sg_set_iectrl(unsigned int pin) void _debug_uart_init(void) { -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); unsigned int divisor; diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 7d11315d07f..36188c38cf9 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \ ddrphy-training.o ddrphy-ld4.o diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index d9b2b999e10..8545331c54a 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -12,4 +12,4 @@ obj-y += slcr.o obj-y += clk.o obj-y += lowlevel_init.o AFLAGS_lowlevel_init.o := -mfpu=neon -obj-$(CONFIG_SPL_BUILD) += spl.o ps7_spl_init.o +obj-$(CONFIG_XPL_BUILD) += spl.o ps7_spl_init.o diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 5b6d765099d..74dddc25988 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -52,7 +52,7 @@ static const struct { int arch_cpu_init(void) { zynq_slcr_unlock(); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 38be1627eeb..ff426044797 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -5,10 +5,10 @@ obj-y += aes.o clk.o cpu.o obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o +obj-$(CONFIG_XPL_BUILD) += spl.o handoff.o psu_spl_init.o obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o -obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o +obj-$(CONFIG_$(XPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o -endif # !CONFIG_SPL_BUILD +endif # !CONFIG_XPL_BUILD diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 07668c94689..960ffac2105 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -112,19 +112,32 @@ u64 get_page_table_size(void) return 0x14000; } -#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(u8 mode) { - puts("WARNING: Initializing TCM overwrites TCM content\n"); - initialize_tcm(mode); - memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); + int ret; + + ret = check_tcm_mode(mode); + if (!ret) { + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(mode); + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); + } + + if (ret == -EACCES) + printf("ERROR: Split to lockstep mode required reset/disable cpu\n"); + + /* Ignore if ret is -EAGAIN, trying to initialize same mode again */ } #endif #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU int arm_reserve_mmu(void) { - tcm_init(TCM_LOCK); + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(TCM_LOCK); + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); + gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; @@ -187,7 +200,7 @@ int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) { - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) return zynqmp_mmio_rawwrite(address, mask, value); #if defined(CONFIG_ZYNQMP_FIRMWARE) else @@ -205,7 +218,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value) if (!value) return ret; - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { ret = zynqmp_mmio_rawread(address, value); } #if defined(CONFIG_ZYNQMP_FIRMWARE) diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 15b69e77712..9af3ab5d6b6 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -48,9 +48,10 @@ enum { unsigned int zynqmp_get_silicon_version(void); +int check_tcm_mode(bool mode); void initialize_tcm(bool mode); void mem_map_fill(void); -#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(u8 mode); #endif diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 9b46a25a1cb..6e6da8008f4 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -12,7 +12,9 @@ #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <linux/bitfield.h> #include <linux/delay.h> +#include <linux/errno.h> #include <linux/string.h> #define LOCK 0 @@ -264,6 +266,28 @@ void initialize_tcm(bool mode) } } +int check_tcm_mode(bool mode) +{ + u32 tmp, cpu_state; + bool mode_prev; + + tmp = readl(&rpu_base->rpu_glbl_ctrl); + mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp); + + tmp = readl(&crlapb_base->rst_lpd_top); + cpu_state = FIELD_GET(ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp); + cpu_state = cpu_state ? false : true; + + if ((mode_prev == SPLIT && mode == LOCK) && cpu_state) + return -EACCES; + + if (mode_prev == mode) + return -EAGAIN; + + return 0; +} + static void mark_r5_used(u32 nr, u8 mode) { u32 mask = 0; diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c index 3b4d9c60e5c..8ee25e4c316 100644 --- a/arch/arm/mach-zynqmp/zynqmp.c +++ b/arch/arm/mach-zynqmp/zynqmp.c @@ -151,14 +151,12 @@ static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, if (argc != cmdtp->maxargs) return CMD_RET_USAGE; - if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) { - printf("mode param should be lockstep or split\n"); - return CMD_RET_FAILURE; - } - - mode = hextoul(argv[2], NULL); - if (mode != TCM_LOCK && mode != TCM_SPLIT) { - printf("Mode should be either 0(lock)/1(split)\n"); + if (!strcmp(argv[2], "lockstep") || !strcmp(argv[2], "0")) { + mode = TCM_LOCK; + } else if (!strcmp(argv[2], "split") || !strcmp(argv[2], "1")) { + mode = TCM_SPLIT; + } else { + printf("Mode should be either lockstep/split\n"); return CMD_RET_FAILURE; } @@ -429,7 +427,7 @@ U_BOOT_LONGHELP(zynqmp, " initialized before accessing to avoid ECC\n" " errors. mode specifies in which mode TCM has\n" " to be initialized. Supported modes will be\n" - " lock(0)/split(1)\n" + " lockstep(0)/split(1)\n" #endif "zynqmp pmufw address size - load PMU FW configuration object\n" "zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n" diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 7988522eb98..8b354b9c570 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -20,12 +20,5 @@ dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h index d419824806c..5decf73a1d1 100644 --- a/arch/m68k/include/asm/ptrace.h +++ b/arch/m68k/include/asm/ptrace.h @@ -9,6 +9,8 @@ */ #ifndef __ASSEMBLY__ +#include <linux/types.h> + struct pt_regs { ulong d0; ulong d1; diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 64c3f313195..53244046f19 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -11,7 +11,7 @@ PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections LDFLAGS_FINAL += --gc-sections -ifeq ($(CONFIG_SPL_BUILD),) +ifeq ($(CONFIG_XPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC LDFLAGS_u-boot += -pic endif diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index b8c1dcbe14f..4d4919c3e3f 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -7,4 +7,4 @@ extra-y = start.o obj-y = irq.o obj-y += interrupts.o cache.o exception.o cpuinfo.o relocate.o obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index c1e0fcda0a4..69c4efdad7f 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -26,7 +26,7 @@ _start: mts rslr, r0 mts rshr, r20 -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) addi r1, r0, CONFIG_SPL_STACK #else add r1, r0, r20 @@ -83,7 +83,7 @@ uboot_sym_start: brlid r15, board_init_f_init_reserve nop -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /* Setup vectors with pre-relocation symbols */ or r5, r0, r0 brlid r15, __setup_exceptions @@ -122,7 +122,7 @@ clear_bss: brlid r15, debug_uart_init nop #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD or r5, r0, r0 /* flags - empty */ bri board_init_f #else @@ -130,7 +130,7 @@ clear_bss: #endif 1: bri 1b -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD .text .ent __setup_exceptions .align 2 diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile index 427a8f9aaca..9be902d3bb1 100644 --- a/arch/microblaze/dts/Makefile +++ b/arch/microblaze/dts/Makefile @@ -4,12 +4,5 @@ dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a007914590f..453c7885075 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -2,7 +2,7 @@ head-y := arch/mips/cpu/start.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) head-$(CONFIG_ARCH_JZ47XX) := arch/mips/mach-jz47xx/start.o head-$(CONFIG_SOC_MT7621) := arch/mips/mach-mtmips/mt7621/spl/start.o endif diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 745f03190e9..ad2ea11f72c 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -53,7 +53,7 @@ PLATFORM_ELFFLAGS += -B mips $(OBJCOPYFLAGS) # LDFLAGS_vmlinux += -G 0 -static -n -nostdlib # MODFLAGS += -mlong-calls # -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD OBJCOPYFLAGS += -j .data.reloc -j .dtb.init.rodata LDFLAGS_FINAL += --emit-relocs endif diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 14fbce597b9..752e771514f 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -39,13 +39,5 @@ dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 1621cc9a1ff..79841dbe5ed 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -12,6 +12,6 @@ obj-y += traps.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o diff --git a/arch/mips/mach-jz47xx/Makefile b/arch/mips/mach-jz47xx/Makefile index dbb8229f785..5621a09b6dd 100644 --- a/arch/mips/mach-jz47xx/Makefile +++ b/arch/mips/mach-jz47xx/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -extra-$(CONFIG_SPL_BUILD) := start.o +extra-$(CONFIG_XPL_BUILD) := start.o obj-$(CONFIG_SOC_JZ4780) += jz4780/ diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780.h b/arch/mips/mach-jz47xx/include/mach/jz4780.h index 880445dac39..9f9a8cf9438 100644 --- a/arch/mips/mach-jz47xx/include/mach/jz4780.h +++ b/arch/mips/mach-jz47xx/include/mach/jz4780.h @@ -94,7 +94,7 @@ void jz4780_efuse_init(u32 ahb2_rate); void jz4780_tcu_wdt_start(void); -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD int jz_mmc_init(void __iomem *base); #endif diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index 1d6fb6a4e27..504fd27d285 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -19,7 +19,7 @@ #include <mmc.h> #include <spl.h> -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* Pointer to the global data structure for SPL */ DECLARE_GLOBAL_DATA_PTR; gd_t gdata __section(".bss"); @@ -73,7 +73,7 @@ void board_init_f(ulong dummy) hang(); } -#endif /* CONFIG_SPL_BUILD */ +#endif /* CONFIG_XPL_BUILD */ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { diff --git a/arch/mips/mach-jz47xx/start.S b/arch/mips/mach-jz47xx/start.S index 760d0215493..0d40e637a68 100644 --- a/arch/mips/mach-jz47xx/start.S +++ b/arch/mips/mach-jz47xx/start.S @@ -18,7 +18,7 @@ .globl _start .text _start: -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* magic value ("MSPL") */ .word 0x4d53504c @@ -95,4 +95,4 @@ enable_caches: .end enable_caches #endif /* CONFIG_SOC_JZ4780 */ -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/mips/mach-mtmips/Makefile b/arch/mips/mach-mtmips/Makefile index 19f1e07033e..2f35b1a925c 100644 --- a/arch/mips/mach-mtmips/Makefile +++ b/arch/mips/mach-mtmips/Makefile @@ -5,7 +5,7 @@ obj-y += cpu.o ifneq ($(CONFIG_SOC_MT7621),y) obj-y += ddr_init.o obj-y += ddr_cal.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o endif obj-$(CONFIG_SOC_MT7620) += mt7620/ diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c index 243938a0ebb..982a5889df8 100644 --- a/arch/mips/mach-mtmips/cpu.c +++ b/arch/mips/mach-mtmips/cpu.c @@ -21,7 +21,7 @@ int dram_init(void) return 0; } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static int last_stage_init(void) { void *src, *dst; diff --git a/arch/mips/mach-mtmips/mt7620/Makefile b/arch/mips/mach-mtmips/mt7620/Makefile index 649f6c3798f..d2d79e3424b 100644 --- a/arch/mips/mach-mtmips/mt7620/Makefile +++ b/arch/mips/mach-mtmips/mt7620/Makefile @@ -5,6 +5,6 @@ obj-y += init.o obj-y += dram.o obj-y += serial.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += sysc.o endif diff --git a/arch/mips/mach-mtmips/mt7621/Makefile b/arch/mips/mach-mtmips/mt7621/Makefile index bf1b0bb688b..f48083e3559 100644 --- a/arch/mips/mach-mtmips/mt7621/Makefile +++ b/arch/mips/mach-mtmips/mt7621/Makefile @@ -3,7 +3,7 @@ obj-y += init.o obj-y += serial.o -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) ifeq ($(CONFIG_TPL_BUILD),y) obj-y += tpl/ else diff --git a/arch/mips/mach-mtmips/mt7628/Makefile b/arch/mips/mach-mtmips/mt7628/Makefile index 7e139d5adfd..63acf54536b 100644 --- a/arch/mips/mach-mtmips/mt7628/Makefile +++ b/arch/mips/mach-mtmips/mt7628/Makefile @@ -3,4 +3,4 @@ obj-y += lowlevel_init.o obj-y += init.o obj-y += ddr.o -obj-$(CONFIG_SPL_BUILD) += serial.o +obj-$(CONFIG_XPL_BUILD) += serial.o diff --git a/arch/nios2/dts/Makefile b/arch/nios2/dts/Makefile index 2b29fa90f6c..d77db9762a1 100644 --- a/arch/nios2/dts/Makefile +++ b/arch/nios2/dts/Makefile @@ -4,12 +4,5 @@ dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 725a4f48aad..dd0124cace1 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -27,7 +27,7 @@ PLATFORM_CPPFLAGS+= -D__PPC__ endif # Only test once -ifneq ($(CONFIG_SPL_BUILD),y) +ifneq ($(CONFIG_XPL_BUILD),y) archprepare: checkgcc4 # GCC 3.x is reported to have problems generating the type of relocation diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 1255f533e34..9974239f881 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -7,7 +7,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index ceb54867894..78762f000df 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -41,11 +41,11 @@ #endif #if defined(CONFIG_NAND_SPL) || \ - (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) + (defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) #define MINIMAL_SPL #endif -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ +#if !defined(CONFIG_XPL_BUILD) && !defined(CONFIG_NAND_SPL) && \ !defined(CONFIG_SYS_RAMBOOT) #define CFG_SYS_FLASHBOOT #endif @@ -168,7 +168,7 @@ _start: /* time t 0 */ /* Initialise the E300 processor core */ /*------------------------------------------*/ -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ +#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \ defined(CONFIG_NAND_SPL) /* The FCM begins execution after only the first page * is loaded. Wait for the rest before branching diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f3ee7d34949..bf74228efde 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -8,7 +8,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y @@ -26,7 +26,7 @@ else obj-$(CONFIG_MP) += release.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 574510fa088..75bfc07fe97 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -179,7 +179,7 @@ void cpu_init_early_f(void *fdt) invalidate_tlb(1); #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \ - !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \ + !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_XPL_BUILD)) && \ !defined(CONFIG_NAND_SPL) disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); #endif diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 3e24a90233c..89bce5bed69 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -28,7 +28,7 @@ #define LAW_EN 0x80000000 #if defined(CONFIG_NAND_SPL) || \ - (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) + (defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)) #define MINIMAL_SPL #endif @@ -58,16 +58,16 @@ END_GOT #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD) /* Maximal size of the image */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #define MAX_IMAGE_SIZE (CONFIG_SPL_MAX_SIZE - (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512)) #else #define MAX_IMAGE_SIZE CONFIG_SYS_L2_SIZE #endif -#if defined(CONFIG_SPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 +#if defined(CONFIG_XPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 #error "CONFIG_SPL_MAX_SIZE is too small for CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA" #endif @@ -1138,10 +1138,10 @@ create_init_ram_area: /* * For Targets without CONFIG_SPL like P3, P5 * and for targets with CONFIG_SPL like T1, T2, T4, only for - * u-boot-spl i.e. CONFIG_SPL_BUILD + * u-boot-spl i.e. CONFIG_XPL_BUILD */ #elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \ - (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)) /* create a temp mapping in AS = 1 for mapping CONFIG_VAL(SYS_MONITOR_BASE) * to L3 Address configured by PBL for ISBC code */ @@ -1617,7 +1617,7 @@ relocate_code: mr r10,r5 /* Save copy of Destination Address */ GET_GOT -#if !defined(CONFIG_SPL_SKIP_RELOCATE) || !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_SKIP_RELOCATE) || !defined(CONFIG_XPL_BUILD) mr r3,r5 /* Destination Address */ lis r4,CONFIG_VAL(SYS_MONITOR_BASE)@h /* Source Address */ ori r4,r4,CONFIG_VAL(SYS_MONITOR_BASE)@l diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 32b68a169a4..415ab1096c6 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -45,7 +45,7 @@ __weak void init_tlbs(void) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) + (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, phys_addr_t *rpn) { @@ -313,7 +313,7 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, print_size(memsize > CFG_MAX_MEM_MAPPED ? memsize - CFG_MAX_MEM_MAPPED + size : size, " of DDR memory left unmapped in U-Boot\n"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD puts(" "); #endif } diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index e3a536d4f8c..a44b5165d74 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -4,7 +4,7 @@ MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 3a82e60a247..638c3a6fee5 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -241,7 +241,7 @@ int pamu_init(void) spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; /* Allocate space for Primary PAACT Table */ -#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR)) +#if (defined(CONFIG_XPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR)) ppaact = (void *)CFG_SPL_PPAACT_ADDR; #else ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); @@ -251,7 +251,7 @@ int pamu_init(void) memset(ppaact, 0, ppaact_size); /* Allocate space for Secondary PAACT Table */ -#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR)) +#if (defined(CONFIG_XPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR)) sec = (void *)CFG_SPL_SPAACT_ADDR; #else sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index b4695cc99cb..3fd80eb29c0 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -78,7 +78,7 @@ void disable_law(u8 idx) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) + (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) static int get_law_entry(u8 i, struct law_entry *e) { u32 lawar; @@ -109,7 +109,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) } #if !defined(CONFIG_NAND_SPL) && \ - (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) + (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL)) int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 831a11736cc..bd3f69b469e 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -28,7 +28,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) i++; #endif -#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) +#if (defined(CONFIG_XPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) tbl->start_addr[i] = (uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR); tbl->size[i] = 256 * 1024; /* 256K CPC flash */ diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 321c644804e..766b0c05951 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -35,13 +35,5 @@ dtb-$(CONFIG_TARGET_CMPCPRO) += cmpcpro.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 221f9d842a8..f12830984c6 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -36,7 +36,7 @@ #endif /* #ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_CHAIN_OF_TRUST -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init * due to space crunch on CPC and thus malloc will not work. @@ -45,10 +45,10 @@ #define CFG_SPL_SPAACT_ADDR 0x2f000000 #define CFG_SPL_JR0_LIODN_S 454 #define CFG_SPL_JR0_LIODN_NS 458 -#endif /* ifdef CONFIG_SPL_BUILD */ +#endif /* ifdef CONFIG_XPL_BUILD */ -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD #include <config_fsl_chain_trust.h> -#endif /* #ifndef CONFIG_SPL_BUILD */ +#endif /* #ifndef CONFIG_XPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index ecc2aba8f3c..c0caa703caa 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -9,7 +9,7 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _lshrdi3.o MINIMAL= -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_INIT_MINIMAL MINIMAL=y @@ -45,6 +45,6 @@ obj-y += time.o obj-y += traps.o endif # not minimal -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_$(SPL_TPL)_FRAMEWORK) += spl.o +ifdef CONFIG_XPL_BUILD +obj-$(CONFIG_$(PHASE_)FRAMEWORK) += spl.o endif diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index c36a8533e0f..4e6f347038d 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -48,7 +48,7 @@ endif ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) -ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y) +ifeq ($(CONFIG_$(XPL_)FRAMEPOINTER),y) ARCH_FLAGS += -fno-omit-frame-pointer endif diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile index 043fb961a51..69759c55658 100644 --- a/arch/riscv/cpu/fu540/Makefile +++ b/arch/riscv/cpu/fu540/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2020 SiFive, Inc # Pragnesh Patel <pragnesh.patel@sifive.com> -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += spl.o else obj-y += dram.o diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile index 1d1ad98ba7c..9071c831992 100644 --- a/arch/riscv/cpu/fu740/Makefile +++ b/arch/riscv/cpu/fu740/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2020-2021 SiFive, Inc # Pragnesh Patel <pragnesh.patel@sifive.com> -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += spl.o else obj-y += dram.o diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile index 951c95631e9..0939c1061d0 100644 --- a/arch/riscv/cpu/jh7110/Makefile +++ b/arch/riscv/cpu/jh7110/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2022 StarFive Technology Co., Ltd. -ifeq ($(CONFIG_SPL_BUILD),y) +ifeq ($(CONFIG_XPL_BUILD),y) obj-y += spl.o else obj-y += cpu.o diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8e58f641f1b..3f78932aa9d 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -90,7 +90,7 @@ _start: * Set stackpointer in internal/ex RAM to call board_init_f */ call_board_init_f: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK) li t0, CONFIG_SPL_STACK #else li t0, SYS_INIT_SP_ADDR @@ -218,7 +218,7 @@ wait_for_gd_init: la t5, board_init_f jalr t5 /* jump to board_init_f() */ -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD spl_clear_bss: la t0, __bss_start la t1, __bss_end @@ -271,7 +271,7 @@ spl_call_board_init_r: j board_init_r #endif -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) /* * void relocate_code(addr_sp, gd, addr_moni) * @@ -420,7 +420,7 @@ call_board_init_r: * jump to it ... */ jr t4 /* jump to board_init_r() */ -#endif /* !defined(CONFIG_SPL_BUILD) */ +#endif /* !defined(CONFIG_XPL_BUILD) */ #if CONFIG_IS_ENABLED(SMP) hart_out_of_bounds_loop: diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index c4c44057bad..f3dfd751cb4 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -15,12 +15,5 @@ dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 65dc49f6fa5..268116f3757 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -11,20 +11,20 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o -ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) -obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += aclint_ipi.o +ifeq ($(CONFIG_$(XPL_)RISCV_MMODE),y) +obj-$(CONFIG_$(XPL_)RISCV_ACLINT) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif obj-y += interrupts.o -ifeq ($(CONFIG_$(SPL_)SYSRESET),) +ifeq ($(CONFIG_$(XPL_)SYSRESET),) obj-y += reset.o endif obj-y += setjmp.o -obj-$(CONFIG_$(SPL_)SMP) += smp.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_$(XPL_)SMP) += smp.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-y += fdt_fixup.o obj-$(CONFIG_$(SPL)CMD_BDI) += bdinfo.o @@ -36,15 +36,11 @@ CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI) CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI) CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI) -extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC) -extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC) -extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC) +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMMOVE) += memmove.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_STRLEN) += strlen_zbb.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_STRCMP) += strcmp_zbb.o +obj-$(CONFIG_$(PHASE_)USE_ARCH_STRNCMP) += strncmp_zbb.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRLEN) += strlen_zbb.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRCMP) += strcmp_zbb.o -obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_STRNCMP) += strncmp_zbb.o - -obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o +obj-$(CONFIG_$(PHASE_)SEMIHOSTING) += semihosting.o diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index d8fe1dfa958..d74544b93d8 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -10,7 +10,7 @@ #include <dm/device-internal.h> #include <dm/uclass-internal.h> -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD void enable_caches(void) { struct udevice *dev; @@ -45,4 +45,4 @@ void enable_caches(void) probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev); } -#endif /* !CONFIG_SPL_BUILD */ +#endif /* !CONFIG_XPL_BUILD */ diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 7c5c52652f5..bfcdc335d32 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -8,7 +8,7 @@ obj-y := cache.o cpu.o state.o extra-y := start.o os.o extra-$(CONFIG_SANDBOX_SDL) += sdl.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_ETH_SANDBOX_RAW) += eth-raw-os.o # os.c is build in the system environment, so needs standard includes diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 51ce40e7f08..06f8c13fab9 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -165,7 +165,7 @@ phys_addr_t virt_to_phys(void *ptr) void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { -#if defined(CONFIG_PCI) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_PCI) && !defined(CONFIG_XPL_BUILD) unsigned long plen = len; void *ptr; diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 1c33a520c64..7056cfd0180 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -27,8 +27,8 @@ int sandbox_find_next_phase(char *fname, int maxlen, bool use_img) const char *cur_prefix, *next_prefix; int ret; - cur_prefix = spl_phase_prefix(spl_phase()); - next_prefix = spl_phase_prefix(spl_next_phase()); + cur_prefix = xpl_prefix(xpl_phase()); + next_prefix = xpl_prefix(xpl_next_phase()); ret = os_find_u_boot(fname, maxlen, use_img, cur_prefix, next_prefix); if (ret) return log_msg_ret("find", ret); @@ -55,9 +55,10 @@ void board_init_f(ulong flag) void board_boot_order(u32 *spl_boot_list) { + struct sandbox_state *state = state_get_current(); + spl_boot_list[0] = BOOT_DEVICE_VBE; - spl_boot_list[1] = BOOT_DEVICE_UPL; - spl_boot_list[2] = BOOT_DEVICE_BOARD; + spl_boot_list[1] = state->upl ? BOOT_DEVICE_UPL : BOOT_DEVICE_BOARD; } static int spl_board_load_file(struct spl_image_info *spl_image, @@ -91,7 +92,7 @@ static int load_from_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { struct sandbox_state *state = state_get_current(); - enum u_boot_phase next_phase; + enum xpl_phase_t next_phase; const char *fname; ulong pos, size; int full_size; @@ -101,7 +102,7 @@ static int load_from_image(struct spl_image_info *spl_image, if (!IS_ENABLED(CONFIG_SANDBOX_VPL)) return -ENOENT; - next_phase = spl_next_phase(); + next_phase = xpl_next_phase(); pos = spl_get_image_pos(); size = spl_get_image_size(); if (pos == BINMAN_SYM_MISSING || size == BINMAN_SYM_MISSING) { diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 9ad5d46271a..81752edc9f8 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -129,7 +129,7 @@ static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg) } SANDBOX_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help"); -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD int sandbox_main_loop_init(void) { struct sandbox_state *state = state_get_current(); @@ -206,7 +206,7 @@ static int sandbox_cmdline_cb_test_fdt(struct sandbox_state *state, char *relname; int len; - if (spl_phase() <= PHASE_SPL) + if (xpl_phase() <= PHASE_SPL) relname = "../arch/sandbox/dts/test.dtb"; else relname = "arch/sandbox/dts/test.dtb"; diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index f810b4752f5..1c9fb4a4566 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -10,12 +10,5 @@ dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - +# Add any required device tree compiler flags here DTC_FLAGS += -R 4 -p 0x1000 - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb *.dtbo diff --git a/arch/sandbox/dts/cedit.dtsi b/arch/sandbox/dts/cedit.dtsi index 9bd84e62936..facd7a49bef 100644 --- a/arch/sandbox/dts/cedit.dtsi +++ b/arch/sandbox/dts/cedit.dtsi @@ -39,6 +39,9 @@ /* IDs for the menu items */ item-id = <ID_CPU_SPEED_1 ID_CPU_SPEED_2 ID_CPU_SPEED_3>; + + /* values for the menu items */ + item-value = <0 3 6>; }; power-loss { diff --git a/arch/sandbox/dts/sandbox_pmic.dtsi b/arch/sandbox/dts/sandbox_pmic.dtsi index 565c382ed45..ff2cb42844c 100644 --- a/arch/sandbox/dts/sandbox_pmic.dtsi +++ b/arch/sandbox/dts/sandbox_pmic.dtsi @@ -10,6 +10,7 @@ &sandbox_pmic { compatible = "sandbox,pmic"; + sandbox,emul = <&emul_pmic0>; buck1 { regulator-name = "SUPPLY_1.2V"; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9599a8db9c5..3017b33d67b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -101,6 +101,11 @@ bootscr-ram-offset = /bits/ 64 <0x12345678>; bootscr-flash-offset = /bits/ 64 <0>; bootscr-flash-size = /bits/ 64 <0x2000>; + boot-led = "sandbox:green"; + activity-led = "sandbox:red"; + testing-bool; + testing-int = <123>; + testing-str = "testing"; }; }; diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index d3c480e79ed..99acc599965 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -33,8 +33,9 @@ static inline void cache_wback_all(void) } } -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 +#define CACHE_ENABLE 0 +#define CACHE_DISABLE 1 +#define CACHE_INVALIDATE 2 static int cache_control(unsigned int cmd) { @@ -46,7 +47,9 @@ static int cache_control(unsigned int cmd) if (ccr & CCR_CACHE_ENABLE) cache_wback_all(); - if (cmd == CACHE_DISABLE) + if (cmd == CACHE_INVALIDATE) + outl(CCR_CACHE_ICI | ccr, CCR); + else if (cmd == CACHE_DISABLE) outl(CCR_CACHE_STOP, CCR); else outl(CCR_CACHE_INIT, CCR); @@ -103,7 +106,7 @@ void icache_disable(void) void invalidate_icache_all(void) { - puts("No arch specific invalidate_icache_all available!\n"); + cache_control(CACHE_INVALIDATE); } int icache_status(void) diff --git a/arch/sh/dts/Makefile b/arch/sh/dts/Makefile index 144fd3e7d22..e9153e42534 100644 --- a/arch/sh/dts/Makefile +++ b/arch/sh/dts/Makefile @@ -2,13 +2,5 @@ dtb-y += sh7751-r2dplus.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - # Add any required device tree compiler flags here DTC_FLAGS += - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb *_HS diff --git a/arch/x86/Makefile b/arch/x86/Makefile index f1afc74fff8..fd409b9f720 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0+ ifeq ($(CONFIG_EFI_APP),) -ifdef CONFIG_$(SPL_)X86_64 +ifdef CONFIG_$(XPL_)X86_64 head-y := arch/x86/cpu/start64.o else -ifeq ($(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),y) +ifeq ($(CONFIG_$(PHASE_)X86_16BIT_INIT),y) head-y := arch/x86/cpu/start.o else ifndef CONFIG_SPL head-y := arch/x86/cpu/start.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD head-y = arch/x86/cpu/start_from_tpl.o else head-y = arch/x86/cpu/start_from_spl.o @@ -20,8 +20,8 @@ endif endif endif # EFI -head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o -head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o +head-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += arch/x86/cpu/start16.o +head-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o libs-y += arch/x86/cpu/ libs-y += arch/x86/lib/ diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 2e3a7119e79..6d4839dfb38 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -10,7 +10,7 @@ PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD IS_32BIT := y else ifndef CONFIG_X86_64 @@ -26,7 +26,7 @@ endif ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 else -PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -march=core2 -m64 +PLATFORM_CPPFLAGS += $(if $(CONFIG_XPL_BUILD),,-fpic) -fno-common -march=core2 -m64 ifndef CONFIG_X86_HARDFP PLATFORM_CPPFLAGS += -mno-mmx -mno-sse @@ -86,12 +86,12 @@ ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -mregparm=3 endif KBUILD_LDFLAGS += --emit-relocs -LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie) +LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_XPL_BUILD),,-pie) endif ifdef CONFIG_X86_64 -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD PLATFORM_CPPFLAGS += -D__x86_64__ else PLATFORM_CPPFLAGS += -D__I386__ diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 16e67e3da24..39c8b0835cc 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -6,16 +6,16 @@ # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. -ifeq ($(CONFIG_$(SPL_)X86_64),y) +ifeq ($(CONFIG_$(XPL_)X86_64),y) extra-y = start64.o else -ifeq ($(CONFIG_$(SPL_TPL_)X86_16BIT_INIT),y) +ifeq ($(CONFIG_$(PHASE_)X86_16BIT_INIT),y) extra-y = start.o else ifndef CONFIG_SPL extra-y = start.o else -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD extra-y = start_from_tpl.o else extra-y = start_from_spl.o @@ -24,14 +24,14 @@ endif endif endif -extra-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += resetvec.o start16.o +extra-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += resetvec.o start16.o obj-y += cpu.o ifndef CONFIG_TPL_BUILD obj-y += cpu_x86.o endif -ifndef CONFIG_$(SPL_)X86_64 +ifndef CONFIG_$(XPL_)X86_64 AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) AFLAGS_call32.o := -fpic -fshort-wchar \ @@ -54,23 +54,23 @@ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-$(CONFIG_APIC) += lapic.o ioapic.o -obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o +obj-$(CONFIG_$(PHASE_)ACPI_GPE) += acpi_gpe.o obj-$(CONFIG_QFW) += qfw_cpu.o ifndef CONFIG_SYS_COREBOOT -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += irq.o endif -ifndef CONFIG_$(SPL_)X86_64 -obj-$(CONFIG_$(SPL_)SMP) += mp_init.o +ifndef CONFIG_$(XPL_)X86_64 +obj-$(CONFIG_$(XPL_)SMP) += mp_init.o endif obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o -ifndef CONFIG_$(SPL_)X86_64 +ifndef CONFIG_$(XPL_)X86_64 obj-$(CONFIG_SMP) += sipi_vector.o endif obj-y += turbo.o obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.o -ifeq ($(CONFIG_$(SPL_)X86_64),y) +ifeq ($(CONFIG_$(XPL_)X86_64),y) obj-y += x86_64/ else obj-y += i386/ diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 2ddf4af62c5..f481f40d9bb 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -2,20 +2,20 @@ # # Copyright 2019 Google LLC -obj-$(CONFIG_SPL_BUILD) += cpu_spl.o -obj-$(CONFIG_SPL_BUILD) += spl.o -obj-$(CONFIG_SPL_BUILD) += systemagent.o +obj-$(CONFIG_XPL_BUILD) += cpu_spl.o +obj-$(CONFIG_XPL_BUILD) += spl.o +obj-$(CONFIG_XPL_BUILD) += systemagent.o obj-y += cpu_common.o ifndef CONFIG_TPL_BUILD obj-y += cpu.o obj-y += punit.o obj-y += fsp_bindings.o -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += fsp_m.o endif endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += acpi.o obj-y += fsp_s.o endif diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8798fa79d4c..8198667fa50 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -184,9 +184,9 @@ int arch_cpu_init(void) { int ret = 0; - if (spl_phase() == PHASE_TPL) + if (xpl_phase() == PHASE_TPL) ret = arch_cpu_init_tpl(); - else if (spl_phase() == PHASE_SPL) + else if (xpl_phase() == PHASE_SPL) ret = arch_cpu_init_spl(); if (ret) printf("%s: Error %d\n", __func__, ret); diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index f6fbddce922..b4bb677f5cd 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -247,7 +247,7 @@ static int fsp_update_config_from_dtb(ofnode node, u8 *cfg, return 0; } -#if defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_XPL_BUILD) const struct fsp_binding fsp_m_bindings[] = { { .type = FSP_UINT32, @@ -653,7 +653,7 @@ int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg) } #endif -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if !defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) const struct fsp_binding fsp_s_bindings[] = { { .type = FSP_UINT8, diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 9ee362239ef..039236df02d 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -255,7 +255,7 @@ static int apl_hostbridge_of_to_plat(struct udevice *dev) static int apl_hostbridge_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) + if (xpl_phase() == PHASE_TPL) return apl_hostbridge_early_init(dev); return 0; diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index 531ff1cd91f..f34c199bf73 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -80,7 +80,7 @@ int lpc_open_pmio_window(uint base, uint size) lgir_reg_num = find_unused_pmio_window(); if (lgir_reg_num < 0) { - if (spl_phase() > PHASE_TPL) { + if (xpl_phase() > PHASE_TPL) { log_err("LPC: Cannot open IO window: %lx size %lx\n", bridge_base, size - bridged_size); log_err("No more IO windows\n"); diff --git a/arch/x86/cpu/apollolake/pch.c b/arch/x86/cpu/apollolake/pch.c index 32190312ff8..07ef26f6bde 100644 --- a/arch/x86/cpu/apollolake/pch.c +++ b/arch/x86/cpu/apollolake/pch.c @@ -12,7 +12,7 @@ static int apl_set_spi_protect(struct udevice *dev, bool protect) { - if (spl_phase() == PHASE_SPL) + if (xpl_phase() == PHASE_SPL) return lpc_set_spi_protect(dev, BIOS_CTRL, protect); return 0; diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index 32fd0344861..bfb8a07d47a 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -115,7 +115,7 @@ int apl_pmc_ofdata_to_uc_plat(struct udevice *dev) ARRAY_SIZE(base)); if (ret) return log_msg_ret("Missing/short early-regs", ret); - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { upriv->pmc_bar0 = (void *)base[0]; upriv->pmc_bar2 = (void *)base[2]; @@ -186,7 +186,7 @@ static int enable_pmcbar(struct udevice *dev) static int apl_pmc_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { return enable_pmcbar(dev); } else { struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev); diff --git a/arch/x86/cpu/apollolake/punit.c b/arch/x86/cpu/apollolake/punit.c index b1503c25140..9c708e9df55 100644 --- a/arch/x86/cpu/apollolake/punit.c +++ b/arch/x86/cpu/apollolake/punit.c @@ -77,7 +77,7 @@ static int punit_init(struct udevice *dev) static int apl_punit_probe(struct udevice *dev) { - if (spl_phase() == PHASE_SPL) + if (xpl_phase() == PHASE_SPL) return punit_init(dev); return 0; diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c index b351d73e7d8..510f8c4350f 100644 --- a/arch/x86/cpu/apollolake/spl.c +++ b/arch/x86/cpu/apollolake/spl.c @@ -116,7 +116,7 @@ static int spl_fast_spi_load_image(struct spl_image_info *spl_image, return ret; spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */ - spl_image->entry_point = spl_phase() == PHASE_TPL ? + spl_image->entry_point = xpl_phase() == PHASE_TPL ? CONFIG_SPL_TEXT_BASE : CONFIG_TEXT_BASE; spl_image->load_addr = spl_image->entry_point; spl_image->os = IH_OS_U_BOOT; diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile index 3e1f76d6118..dfe013e3833 100644 --- a/arch/x86/cpu/broadwell/Makefile +++ b/arch/x86/cpu/broadwell/Makefile @@ -2,23 +2,23 @@ # # Copyright (c) 2016 Google, Inc -obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += cpu.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += cpu_full.o +obj-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += cpu.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += cpu_full.o ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += cpu_from_spl.o obj-y += cpu_full.o obj-y += refcode.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD # obj-y += cpu_from_spl.o obj-y += adsp.o obj-y += sata.o endif endif -ifeq ($(CONFIG_$(SPL_TPL_)X86_32BIT_INIT),) +ifeq ($(CONFIG_$(PHASE_)X86_32BIT_INIT),) #obj-y += cpu_from_spl.o endif @@ -29,5 +29,5 @@ obj-y += northbridge.o obj-y += pch.o obj-y += pinctrl_broadwell.o obj-y += power_state.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += refcode.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += sdram.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += refcode.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += sdram.o diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index dc6717eca40..8127d31e57e 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -68,7 +68,7 @@ int arch_cpu_init(void) post_code(POST_CPU_INIT); /* Do a mini-init if TPL has already done the full init */ - if (IS_ENABLED(CONFIG_TPL) && spl_phase() != PHASE_TPL) + if (IS_ENABLED(CONFIG_TPL) && xpl_phase() != PHASE_TPL) return x86_cpu_reinit_f(); else return x86_cpu_init_f(); @@ -88,18 +88,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - char processor_name[CPU_MAX_NAME_LEN]; - const char *name; - - /* Print processor name */ - name = cpu_get_name(processor_name); - printf("CPU: %s\n", name); - - return 0; -} - void board_debug_uart_init(void) { /* com1 / com2 decode range */ diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index c43fb7a608b..529dab18d5d 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -84,7 +84,7 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD) int arch_cpu_init(void) { return 0; diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c index 2c8b7380d96..5b6147432a7 100644 --- a/arch/x86/cpu/broadwell/pch.c +++ b/arch/x86/cpu/broadwell/pch.c @@ -606,7 +606,7 @@ static int broadwell_pch_probe(struct udevice *dev) return broadwell_pch_early_init(dev); else return broadwell_pch_init(dev); - } else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_SPL_BUILD)) { + } else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_XPL_BUILD)) { return broadwell_pch_init(dev); } else { return 0; diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 87e242a2065..6acdf9b3b23 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -9,7 +9,7 @@ LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC) LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) ifdef CONFIG_X86_64 -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_EFI_APP),) +ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_EFI_APP),) LDSCRIPT = $(srctree)/arch/x86/cpu/u-boot-64.lds endif endif diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index a6cdb9a1485..a6c7d0e56d5 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -14,7 +14,7 @@ ifndef CONFIG_SPL obj-y += car.o endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD obj-y += coreboot_spl.o else obj-y += sdram.o diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d474c79e25e..fa7430b436f 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -38,16 +38,6 @@ int arch_cpu_init(void) return 0; } -int checkcpu(void) -{ - return 0; -} - -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} - static void board_final_init(void) { /* @@ -82,7 +72,9 @@ static void board_final_init(void) static int last_stage_init(void) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + timestamp_add_to_bootstage(); + + if (IS_ENABLED(CONFIG_XPL_BUILD)) return 0; board_final_init(); diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c index ec4003c4e77..681191d85bb 100644 --- a/arch/x86/cpu/coreboot/timestamp.c +++ b/arch/x86/cpu/coreboot/timestamp.c @@ -6,13 +6,12 @@ */ #include <bootstage.h> +#include <errno.h> #include <asm/arch/timestamp.h> #include <asm/cb_sysinfo.h> #include <asm/u-boot-x86.h> #include <linux/compiler.h> -static struct timestamp_table *ts_table __section(".data"); - void timestamp_init(void) { timestamp_add_now(TS_U_BOOT_INITTED); @@ -20,6 +19,8 @@ void timestamp_init(void) void timestamp_add(enum timestamp_id id, uint64_t ts_time) { + const struct sysinfo_t *info = cb_get_sysinfo(); + struct timestamp_table *ts_table = info->tstamp_table; struct timestamp_entry *tse; if (!ts_table || (ts_table->num_entries == ts_table->max_entries)) @@ -37,13 +38,15 @@ void timestamp_add_now(enum timestamp_id id) int timestamp_add_to_bootstage(void) { + const struct sysinfo_t *info = cb_get_sysinfo(); + const struct timestamp_table *ts_table = info->tstamp_table; uint i; if (!ts_table) - return -1; + return -ENOENT; for (i = 0; i < ts_table->num_entries; i++) { - struct timestamp_entry *tse = &ts_table->entries[i]; + const struct timestamp_entry *tse = &ts_table->entries[i]; const char *name = NULL; switch (tse->entry_id) { diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index ad21fdb457a..a8b21406ac0 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -163,8 +163,11 @@ char *cpu_get_name(char *name) return ptr; } -int default_print_cpuinfo(void) +#if !CONFIG_IS_ENABLED(CPU) +int print_cpuinfo(void) { + post_code(POST_CPU_INFO); + printf("CPU: %s, vendor %s, device %xh\n", cpu_has_64bit() ? "x86_64" : "x86", cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); @@ -176,6 +179,7 @@ int default_print_cpuinfo(void) return 0; } +#endif #if CONFIG_IS_ENABLED(SHOW_BOOT_PROGRESS) void show_boot_progress(int val) @@ -185,7 +189,7 @@ void show_boot_progress(int val) #endif #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) && \ - !defined(CONFIG_SPL_BUILD) + !defined(CONFIG_XPL_BUILD) /* * Implement a weak default function for boards that need to do some final init * before the system is ready. @@ -247,7 +251,7 @@ static int last_stage_init(void) } EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); -#endif /* !SYS_COREBOOT && !EFI_STUB && !SPL_BUILD */ +#endif /* !SYS_COREBOOT && !EFI_STUB && !XPL_BUILD */ static int x86_init_cpus(void) { @@ -336,7 +340,7 @@ int reserve_arch(void) } #endif -long detect_coreboot_table_at(ulong start, ulong size) +static long detect_coreboot_table_at(ulong start, ulong size) { u32 *ptr, *end; diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 6c53f0ea821..6c32ae499df 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -7,6 +7,7 @@ #include <dm.h> #include <errno.h> #include <asm/cpu.h> +#include <asm/cpu_x86.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index 218a68c4642..84fe50e2f2f 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -19,11 +19,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} - void board_final_init(void) { } diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 642a87a37d8..6845ce72ff9 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -144,11 +144,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} - /* Find any available tables and copy them to a safe place */ int reserve_arch(void) { diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 934e98ac582..a51a24498a7 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -263,6 +263,49 @@ static int build_vendor_name(char *vendor_name) } #endif +int x86_cpu_vendor_info(char *name) +{ + uint cpu_device; + + cpu_device = 0; + + /* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */ +#ifndef CONFIG_TPL_BUILD + *name = '\0'; /* Unset */ + + /* Find the id and vendor_name */ + if (!has_cpuid()) { + /* Its a 486 if we can modify the AC flag */ + if (flag_is_changeable_p(X86_EFLAGS_AC)) + cpu_device = 0x00000400; /* 486 */ + else + cpu_device = 0x00000300; /* 386 */ + if (cpu_device == 0x00000400 && test_cyrix_52div()) { + /* If we ever care we can enable cpuid here */ + memcpy(name, "CyrixInstead", 13); + + /* Detect NexGen with old hypercode */ + } else if (deep_magic_nexgen_probe()) { + memcpy(name, "NexGenDriven", 13); + } + } else { + int cpuid_level; + + cpuid_level = build_vendor_name(name); + name[12] = '\0'; + + /* Intel-defined flags: level 0x00000001 */ + if (cpuid_level >= 0x00000001) + cpu_device = cpuid_eax(0x00000001); + else + /* Have CPUID level 0 only unheard of */ + cpu_device = 0x00000400; + } +#endif /* CONFIG_TPL_BUILD */ + + return cpu_device; +} + static void identify_cpu(struct cpu_device_id *cpu) { cpu->device = 0; /* fix gcc 4.4.4 warning */ @@ -271,7 +314,7 @@ static void identify_cpu(struct cpu_device_id *cpu) * Do a quick and dirty check to save space - Intel and AMD only and * just the vendor. This is enough for most TPL code. */ - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { struct cpuid_result result; result = cpuid(0x00000000); @@ -289,46 +332,19 @@ static void identify_cpu(struct cpu_device_id *cpu) return; } -/* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */ #ifndef CONFIG_TPL_BUILD - char vendor_name[16]; - int i; - - vendor_name[0] = '\0'; /* Unset */ - - /* Find the id and vendor_name */ - if (!has_cpuid()) { - /* Its a 486 if we can modify the AC flag */ - if (flag_is_changeable_p(X86_EFLAGS_AC)) - cpu->device = 0x00000400; /* 486 */ - else - cpu->device = 0x00000300; /* 386 */ - if ((cpu->device == 0x00000400) && test_cyrix_52div()) { - memcpy(vendor_name, "CyrixInstead", 13); - /* If we ever care we can enable cpuid here */ - } - /* Detect NexGen with old hypercode */ - else if (deep_magic_nexgen_probe()) - memcpy(vendor_name, "NexGenDriven", 13); - } else { - int cpuid_level; - - cpuid_level = build_vendor_name(vendor_name); - vendor_name[12] = '\0'; - - /* Intel-defined flags: level 0x00000001 */ - if (cpuid_level >= 0x00000001) { - cpu->device = cpuid_eax(0x00000001); - } else { - /* Have CPUID level 0 only unheard of */ - cpu->device = 0x00000400; - } - } - cpu->vendor = X86_VENDOR_UNKNOWN; - for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { - if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { - cpu->vendor = x86_vendors[i].vendor; - break; + { + char vendor_name[16]; + int i; + + cpu->device = x86_cpu_vendor_info(vendor_name); + + cpu->vendor = X86_VENDOR_UNKNOWN; + for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) { + if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) { + cpu->vendor = x86_vendors[i].vendor; + break; + } } } #endif @@ -485,6 +501,11 @@ int x86_cpu_reinit_f(void) return 0; } +void x86_get_identity_for_timer(void) +{ + setup_identity(); +} + void x86_enable_caches(void) { unsigned long cr0; diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index b3f4214acdb..6f78b072cde 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -237,7 +237,7 @@ void *x86_get_idt(void) return &idt_ptr; } -void __do_irq(int irq) +static void __do_irq(int irq) { printf("Unhandled IRQ : %d\n", irq); } diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 1dc17b45879..a28e6c77c9c 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -5,19 +5,19 @@ obj-$(CONFIG_INTEL_ACPIGEN) += acpi.o ifdef CONFIG_HAVE_MRC -obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o +obj-$(CONFIG_$(PHASE_)X86_16BIT_INIT) += car.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += me_status.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += report_platform.o +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += mrc.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o endif ifdef CONFIG_INTEL_CAR_CQOS obj-$(CONFIG_TPL_BUILD) += car2.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += car2_uninit.o endif endif @@ -26,10 +26,10 @@ obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o obj-y += lpss.o -obj-$(CONFIG_$(SPL_)INTEL_GENERIC_WIFI) += generic_wifi.o +obj-$(CONFIG_$(XPL_)INTEL_GENERIC_WIFI) += generic_wifi.o ifndef CONFIG_EFI_APP -obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o -ifndef CONFIG_$(SPL_)X86_64 +obj-$(CONFIG_$(PHASE_)X86_32BIT_INIT) += microcode.o +ifndef CONFIG_$(XPL_)X86_64 obj-y += microcode.o endif endif @@ -38,7 +38,7 @@ obj-$(CONFIG_HAVE_ITSS) += itss.o obj-$(CONFIG_HAVE_P2SB) += p2sb.o ifdef CONFIG_SPL -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifndef CONFIG_SYS_COREBOOT obj-y += cpu_from_spl.o endif diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index c834c05d130..baa1f0e32d6 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -259,7 +259,7 @@ int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage) return ret; delay = dev_read_u32_default(dev, "fspm,training-delay", 0); - if (spl_phase() == PHASE_SPL) { + if (xpl_phase() == PHASE_SPL) { if (delay) printf("SDRAM training (%d seconds)...", delay); else diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index 7aad8f8ca56..406c41013fc 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -96,7 +96,7 @@ int p2sb_of_to_plat(struct udevice *dev) return log_msg_ret("Missing/short early-regs", ret); plat->mmio_base = base[0]; /* TPL sets up the initial BAR */ - if (spl_phase() == PHASE_TPL) { + if (xpl_phase() == PHASE_TPL) { plat->bdf = pci_get_devfn(dev); if (plat->bdf < 0) return log_msg_ret("Cannot get p2sb PCI address", @@ -114,9 +114,9 @@ int p2sb_of_to_plat(struct udevice *dev) static int p2sb_probe(struct udevice *dev) { - if (spl_phase() == PHASE_TPL) + if (xpl_phase() == PHASE_TPL) return p2sb_early_init(dev); - else if (spl_phase() == PHASE_SPL) + else if (xpl_phase() == PHASE_SPL) return p2sb_spl_init(dev); return 0; diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 716134e9ff3..471ad8d7ebc 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -5,15 +5,15 @@ ifdef CONFIG_HAVE_FSP obj-y += fsp_configs.o ivybridge.o else -obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o +obj-$(CONFIG_$(XPL_)X86_32BIT_INIT) += cpu.o obj-y += early_me.o obj-y += lpc.o obj-y += northbridge.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-y += sata.o endif -obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o -ifndef CONFIG_$(SPL_)X86_32BIT_INIT +obj-$(CONFIG_$(XPL_)X86_32BIT_INIT) += sdram.o +ifndef CONFIG_$(XPL_)X86_32BIT_INIT obj-y += sdram_nop.o endif endif diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 05691a38d2e..d299068a879 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -182,20 +182,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - char processor_name[CPU_MAX_NAME_LEN]; - const char *name; - - /* Print processor name */ - name = cpu_get_name(processor_name); - printf("CPU: %s\n", name); - - post_code(POST_CPU_INFO); - - return 0; -} - void board_debug_uart_init(void) { /* This enables the debug UART */ diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 50cba5fb88d..07ea89162de 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -87,7 +87,7 @@ void mtrr_read_all(struct mtrr_info *info) } } -void mtrr_write_all(struct mtrr_info *info) +static void mtrr_write_all(struct mtrr_info *info) { int reg_count = mtrr_get_var_count(); struct mtrr_state state; diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index b7dd5bd46c7..1439916ac2d 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> -ifndef CONFIG_$(SPL_)X86_64 +ifndef CONFIG_$(XPL_)X86_64 obj-y += car.o endif obj-y += dram.o diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 262584d01f0..563f63e2bc8 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -109,12 +109,6 @@ int checkcpu(void) { return 0; } - -int print_cpuinfo(void) -{ - post_code(POST_CPU_INFO); - return default_print_cpuinfo(); -} #endif int arch_early_init_r(void) diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index fdf92b2c0c3..07504faaffb 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -266,12 +266,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - post_code(POST_CPU_INFO); - return default_print_cpuinfo(); -} - static void quark_pcie_init(void) { u32 val; diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c index 142c9341cf8..8a5c78595aa 100644 --- a/arch/x86/cpu/slimbootloader/slimbootloader.c +++ b/arch/x86/cpu/slimbootloader/slimbootloader.c @@ -54,8 +54,3 @@ int checkcpu(void) { return 0; } - -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c index 8a8f7d27a9d..b005bc7d9a0 100644 --- a/arch/x86/cpu/tangier/tangier.c +++ b/arch/x86/cpu/tangier/tangier.c @@ -19,8 +19,3 @@ int checkcpu(void) { return 0; } - -int print_cpuinfo(void) -{ - return default_print_cpuinfo(); -} diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 80eab710315..71bc07f872a 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -75,3 +75,9 @@ void board_debug_uart_init(void) /* this was already done in SPL */ } #endif + +void x86_get_identity_for_timer(void) +{ + /* set the vendor to Intel so that native_calibrate_tsc() works */ + gd->arch.x86_vendor = X86_VENDOR_INTEL; +} diff --git a/arch/x86/cpu/x86_64/misc.c b/arch/x86/cpu/x86_64/misc.c index 294511e6eba..fc449ca4ed6 100644 --- a/arch/x86/cpu/x86_64/misc.c +++ b/arch/x86/cpu/x86_64/misc.c @@ -32,9 +32,4 @@ int checkcpu(void) { return 0; } - -int print_cpuinfo(void) -{ - return 0; -} #endif diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index cd77f4c4e81..9a46726e026 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -24,12 +24,4 @@ dtb-y += bayleybay.dtb \ include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - DTC_FLAGS += -R 4 -p $(if $(CONFIG_EFI_APP),0x8000,0x1000) - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 87e0c6f12b6..8c1ef4c8cc1 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -293,4 +293,11 @@ u32 cpu_get_stepping(void); */ int cpu_phys_address_size(void); +void board_final_init(void); +void board_final_cleanup(void); + +#ifndef CONFIG_EFI_STUB +int reserve_arch(void); +#endif + #endif diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index 5c49b0f009b..f6836b74488 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -18,7 +18,7 @@ extern char *strchr(const char *s, int c); * Our assembly routines do not work on in 64-bit mode and we don't do a lot of * copying in SPL, so code size is more important there. */ -#if defined(CONFIG_SPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT) +#if defined(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT) #undef __HAVE_ARCH_MEMCPY extern void *memcpy(void *, const void *, __kernel_size_t); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 3acc58ad74b..ed2f6aa3893 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -44,6 +44,15 @@ int x86_cpu_reinit_f(void); int x86_cpu_init_tpl(void); /** + * x86_get_identity_for_timer() - Set up CPU identity for use by the early timer + * + * The timer can be needed early in board_f if bootstage is enabled. This + * function can be called from the TSC timer to make sure that the CPU-identity + * info has been set up + */ +void x86_get_identity_for_timer(void); + +/** * cpu_reinit_fpu() - Reinit the FPU if something is wrong with it * * The FSP-M code can leave registers in use in the FPU. This functions reinits @@ -51,6 +60,14 @@ int x86_cpu_init_tpl(void); */ void cpu_reinit_fpu(void); +/** + * x86_cpu_vendor_info() - Get the CPU-vendor name and device number + * + * @name: 13-byte area to hold the returned string + * Return: CPU device number read from cpuid + */ +int x86_cpu_vendor_info(char *name); + int cpu_init_f(void); void setup_gdt(struct global_data *id, u64 *gdt_addr); /* @@ -78,7 +95,6 @@ void x86_enable_caches(void); void x86_disable_caches(void); int x86_init_cache(void); phys_addr_t board_get_usable_ram_top(phys_size_t total_size); -int default_print_cpuinfo(void); /* Set up a UART which can be used with printch(), printhex8(), etc. */ int setup_internal_uart(int enable); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 8fc35e1b51e..7677c0c352f 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -5,21 +5,21 @@ obj-y += bdinfo.o -ifndef CONFIG_$(SPL_TPL_)X86_64 +ifndef CONFIG_$(PHASE_)X86_64 obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_X86_32BIT_INIT) += string.o endif -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_CMD_BOOTM) += bootm.o endif obj-y += cmd_boot.o -obj-$(CONFIG_$(SPL_)COREBOOT_SYSINFO) += coreboot/ +obj-$(CONFIG_$(XPL_)COREBOOT_SYSINFO) += coreboot/ obj-$(CONFIG_SEABIOS) += coreboot_table.o obj-y += early_cmos.o obj-y += e820.o @@ -27,7 +27,7 @@ obj-y += init_helpers.o obj-y += interrupts.o obj-y += lpc-uclass.o obj-y += mpspec.o -obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi_nhlt.o +obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_nhlt.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o @@ -44,10 +44,10 @@ obj-y += acpi.o obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o ifndef CONFIG_QEMU obj-y += acpigen.o -obj-$(CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE) += acpi_table.o +obj-$(CONFIG_$(PHASE_)GENERATE_ACPI_TABLE) += acpi_table.o endif obj-y += tables.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_ZBOOT) += zimage.o endif obj-$(CONFIG_USE_HOB) += hob.o @@ -58,7 +58,7 @@ obj-$(CONFIG_FSP_VERSION1) += fsp1/ obj-$(CONFIG_FSP_VERSION2) += fsp2/ endif -ifdef CONFIG_SPL_BUILD +ifdef CONFIG_XPL_BUILD ifdef CONFIG_TPL_BUILD obj-y += tpl.o else @@ -90,13 +90,13 @@ endif ifdef CONFIG_EFI_STUB -ifeq ($(CONFIG_$(SPL_)X86_64),) +ifeq ($(CONFIG_$(XPL_)X86_64),) extra-y += $(EFI_CRT0) $(EFI_RELOC) endif else -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),) extra-y += $(EFI_CRT0) $(EFI_RELOC) endif diff --git a/arch/x86/lib/bdinfo.c b/arch/x86/lib/bdinfo.c index 165e8ab944f..2a78f578dee 100644 --- a/arch/x86/lib/bdinfo.c +++ b/arch/x86/lib/bdinfo.c @@ -19,7 +19,12 @@ void arch_print_bdinfo(void) bdinfo_print_num_l("clock_rate", gd->arch.clock_rate); bdinfo_print_num_l("tsc_base", gd->arch.tsc_base); bdinfo_print_num_l("vendor", gd->arch.x86_vendor); - bdinfo_print_str(" name", cpu_vendor_name(gd->arch.x86_vendor)); + if (!IS_ENABLED(CONFIG_X86_64)) { + char vendor_name[16]; + + x86_cpu_vendor_info(vendor_name); + bdinfo_print_str(" name", vendor_name); + } bdinfo_print_num_l("model", gd->arch.x86_model); bdinfo_print_num_l("phys_addr in bits", cpu_phys_address_size()); bdinfo_print_num_l("table start", gd->arch.table_start); diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c index 122b4f7ca01..d478b7486e3 100644 --- a/arch/x86/lib/e820.c +++ b/arch/x86/lib/e820.c @@ -4,6 +4,7 @@ */ #include <efi_loader.h> +#include <lmb.h> #include <asm/e820.h> #include <asm/global_data.h> @@ -41,15 +42,11 @@ void efi_add_known_memory(void) { struct e820_entry e820[E820MAX]; unsigned int i, num; - u64 start, ram_top; + u64 start; int type; num = install_e820_map(ARRAY_SIZE(e820), e820); - ram_top = (u64)gd->ram_top & ~EFI_PAGE_MASK; - if (!ram_top) - ram_top = 0x100000000ULL; - for (i = 0; i < num; ++i) { start = e820[i].addr; @@ -72,13 +69,41 @@ void efi_add_known_memory(void) break; } - if (type == EFI_CONVENTIONAL_MEMORY) { - efi_add_conventional_memory_map(start, - start + e820[i].size, - ram_top); - } else { + if (type != EFI_CONVENTIONAL_MEMORY) efi_add_memory_map(start, e820[i].size, type); - } } } #endif /* CONFIG_IS_ENABLED(EFI_LOADER) */ + +#if CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP) +void lmb_arch_add_memory(void) +{ + struct e820_entry e820[E820MAX]; + unsigned int i, num; + u64 ram_top; + + num = install_e820_map(ARRAY_SIZE(e820), e820); + + ram_top = (u64)gd->ram_top & ~EFI_PAGE_MASK; + if (!ram_top) + ram_top = 0x100000000ULL; + + for (i = 0; i < num; ++i) { + if (e820[i].type == E820_RAM) { + u64 start, size, rgn_top; + + start = e820[i].addr; + size = e820[i].size; + rgn_top = start + size; + + if (start > ram_top) + continue; + + if (rgn_top > ram_top) + size -= rgn_top - ram_top; + + lmb_add(start, size); + } + } +} +#endif /* CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP) */ diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index da6c0a886ae..0039dd1bf5c 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -4,7 +4,7 @@ obj-y += fsp_common.o obj-y += fsp_dram.o -ifndef CONFIG_SPL_BUILD +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o endif obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index c47e6ca4738..7e4c1476634 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -26,12 +26,6 @@ int checkcpu(void) return 0; } -int print_cpuinfo(void) -{ - post_code(POST_CPU_INFO); - return default_print_cpuinfo(); -} - int fsp_init_phase_pci(void) { u32 status; diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index a50dc985a3c..4c4c8334bdb 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -28,7 +28,7 @@ int dram_init(void) return 0; } - if (spl_phase() == PHASE_SPL) { + if (xpl_phase() == PHASE_SPL) { bool s3wake = false; s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index ecbadaae75c..1a2bf46c5c5 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -25,7 +25,7 @@ int fsp_setup_pinctrl(void) int ret; /* Make sure pads are set up early in U-Boot */ - if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F) + if (!ll_boot_init() || xpl_phase() != PHASE_BOARD_F) return 0; /* Probe all pinctrl devices to set up the pads */ @@ -134,7 +134,7 @@ int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry, return log_msg_ret("Could not get flash mmap", ret); } - if (spl_phase() >= PHASE_BOARD_F) { + if (xpl_phase() >= PHASE_BOARD_F) { if (type != FSP_S) return -EPROTONOSUPPORT; ret = binman_entry_find("intel-fsp-s", entry); diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 7c03dea0711..f7df7e03621 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -103,7 +103,7 @@ int spl_spi_load_image(void) void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { - debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()), + debug("Jumping to %s at %lx\n", xpl_name(xpl_next_phase()), (ulong)spl_image->entry_point); #ifdef DEBUG print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1, diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile index c22c50ac4e5..aa582b85e5c 100644 --- a/arch/xtensa/dts/Makefile +++ b/arch/xtensa/dts/Makefile @@ -4,12 +4,4 @@ dtb-$(CONFIG_XTENSA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb include $(srctree)/scripts/Makefile.dts -targets += $(dtb-y) - DTC_FLAGS += - -PHONY += dtbs -dtbs: $(addprefix $(obj)/, $(dtb-y)) - @: - -clean-files := *.dtb |