5 files changed, 64 insertions, 22 deletions

diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 63bc24cdfc7..d25ecba0e88 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -31,19 +31,34 @@ void harts_early_init(void)
 	/* Enable I/D-cache in SPL */
 	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
 		unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+		unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
 
-		mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
-				   MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
+		mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
+				MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
+				MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
+				MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
+
+		if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
+			mcache_ctl_val |= MCACHE_CTL_IC_EN;
+
+		if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+			mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN);
 
 		csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
 
-		/*
-		 * Check mcache_ctl.DC_COHEN, we assume this platform does
-		 * not support CM if the bit is hard-wired to 0.
-		 */
-		if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
-			/* Wait for DC_COHSTA bit to be set */
-			while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
+		if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+			/*
+			 * Check mcache_ctl.DC_COHEN, we assume this platform does
+			 * not support CM if the bit is hard-wired to 0.
+			 */
+			if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
+				/* Wait for DC_COHSTA bit to be set */
+				while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
+			}
 		}
+
+		mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+
+		csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
 	}
 }
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 6a6b8b694bd..94e42c26811 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -12,7 +12,7 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 	model = "AMD MicroBlaze V 32bit";
-	compatible = "amd,mbv";
+	compatible = "qemu,mbv", "amd,mbv";
 
 	cpus: cpus {
 		#address-cells = <1>;
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 393d51c6dde..028fd01c2f3 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -12,20 +12,25 @@
 
 #define CSR_MCACHE_CTL 0x7ca
 #define CSR_MMISC_CTL 0x7d0
-#define CSR_MARCHID 0xf12
 #define CSR_MCCTLCOMMAND 0x7cc
 
-#define MCACHE_CTL_IC_EN_OFFSET 0
-#define MCACHE_CTL_DC_EN_OFFSET 1
-#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
-#define MCACHE_CTL_DC_COHEN_OFFSET 19
-#define MCACHE_CTL_DC_COHSTA_OFFSET 20
-
-#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET)
-#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET)
-#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET)
-#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET)
-#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET)
+/* mcache_ctl register */
+
+#define MCACHE_CTL_IC_EN		BIT(0)
+#define MCACHE_CTL_DC_EN		BIT(1)
+#define MCACHE_CTL_IC_ECCEN		BIT(3)
+#define MCACHE_CTL_DC_ECCEN		BIT(5)
+#define MCACHE_CTL_CCTL_SUEN		BIT(8)
+#define MCACHE_CTL_IC_PREFETCH_EN	BIT(9)
+#define MCACHE_CTL_DC_PREFETCH_EN	BIT(10)
+#define MCACHE_CTL_DC_WAROUND_EN	BIT(13)
+#define MCACHE_CTL_L2C_WAROUND_EN	BIT(15)
+#define MCACHE_CTL_TLB_ECCEN		BIT(18)
+#define MCACHE_CTL_DC_COHEN		BIT(19)
+#define MCACHE_CTL_DC_COHSTA		BIT(20)
+
+/* mmisc_ctl register */
+#define MMISC_CTL_NON_BLOCKING_EN	BIT(8)
 
 #define CCTL_L1D_WBINVAL_ALL 6
 
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 1a15089cae9..986f951c31a 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -142,6 +142,7 @@
 #define CSR_CYCLEH		0xc80
 #define CSR_TIMEH		0xc81
 #define CSR_INSTRETH		0xc82
+#define CSR_MARCHID		0xf12
 #define CSR_MHARTID		0xf14
 
 #ifndef __ASSEMBLY__
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
index 39b0248c323..d8fe1dfa958 100644
--- a/arch/riscv/lib/sifive_cache.c
+++ b/arch/riscv/lib/sifive_cache.c
@@ -7,7 +7,10 @@
 #include <cpu_func.h>
 #include <log.h>
 #include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 
+#ifndef CONFIG_SPL_BUILD
 void enable_caches(void)
 {
 	struct udevice *dev;
@@ -25,3 +28,21 @@ void enable_caches(void)
 			log_debug("ccache enable failed");
 	}
 }
+#else
+static inline void probe_cache_device(struct driver *driver, struct udevice *dev)
+{
+	for (uclass_find_first_device(UCLASS_CACHE, &dev);
+	     dev;
+	     uclass_find_next_device(&dev)) {
+		if (dev->driver == driver)
+			device_probe(dev);
+	}
+}
+
+void enable_caches(void)
+{
+	struct udevice *dev = NULL;
+
+	probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
+}
+#endif /* !CONFIG_SPL_BUILD */