3 files changed, 40 insertions, 1 deletions
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index ccbeb5c3881..abceeded24a 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -54,4 +54,19 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
 
 source "board/st/stm32mp1/Kconfig"
 
+# currently activated for debug / should be deactivated for real product
+if DEBUG_UART
+
+config DEBUG_UART_BOARD_INIT
+	default y
+
+# debug on UART4 by default
+config DEBUG_UART_BASE
+	default 0x40010000
+
+# clock source is HSI on reset
+config DEBUG_UART_CLOCK
+	default 64000000
+endif
+
 endif
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index dfcbbd23146..2deee096182 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -4,6 +4,7 @@
  */
 #include <common.h>
 #include <clk.h>
+#include <debug_uart.h>
 #include <asm/io.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/sys_proto.h>
@@ -152,6 +153,8 @@ static u32 get_bootmode(void)
  */
 int arch_cpu_init(void)
 {
+	u32 boot_mode;
+
 	/* early armv7 timer init: needed for polling */
 	timer_init();
 
@@ -160,8 +163,17 @@ int arch_cpu_init(void)
 
 	security_init();
 #endif
+
 	/* get bootmode from BootRom context: saved in TAMP register */
-	get_bootmode();
+	boot_mode = get_bootmode();
+
+	if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
+		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#if defined(CONFIG_DEBUG_UART) && \
+	(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+	else
+		debug_uart_init();
+#endif
 
 	return 0;
 }
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index a8142013b08..129f9f558ea 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -17,6 +17,18 @@
 #define STM32_ETZPC_BASE		0x5C007000
 #define STM32_TAMP_BASE			0x5C00A000
 
+#ifdef CONFIG_DEBUG_UART_BASE
+/* hardcoded value can be only used for DEBUG UART */
+#define STM32_USART1_BASE		0x5C000000
+#define STM32_USART2_BASE		0x4000E000
+#define STM32_USART3_BASE		0x4000F000
+#define STM32_UART4_BASE		0x40010000
+#define STM32_UART5_BASE		0x40011000
+#define STM32_USART6_BASE		0x44003000
+#define STM32_UART7_BASE		0x40018000
+#define STM32_UART8_BASE		0x40019000
+#endif
+
 #define STM32_SYSRAM_BASE		0x2FFC0000
 #define STM32_SYSRAM_SIZE		SZ_256K